404 lines
8 KiB
C
404 lines
8 KiB
C
/*
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* external mass media controller (mmc / sd host interface)
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*
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* derived from Richard Miller's bcm/emmc.c
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/sd.h"
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enum {
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Initfreq = 400000, /* initialisation frequency for MMC */
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SDfreq = 25000000, /* standard SD frequency */
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DTO = 14, /* data timeout exponent (guesswork) */
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MMCSelect = 7, /* mmc/sd card select command */
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Setbuswidth = 6, /* mmc/sd set bus width command */
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};
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enum {
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/* Controller registers */
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Sysaddr = 0x00>>2,
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Blksizecnt = 0x04>>2,
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Arg1 = 0x08>>2,
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Cmdtm = 0x0c>>2,
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Resp0 = 0x10>>2,
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Resp1 = 0x14>>2,
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Resp2 = 0x18>>2,
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Resp3 = 0x1c>>2,
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Data = 0x20>>2,
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Status = 0x24>>2,
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Control0 = 0x28>>2,
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Control1 = 0x2c>>2,
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Interrupt = 0x30>>2,
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Irptmask = 0x34>>2,
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Irpten = 0x38>>2,
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Capabilites = 0x40>>2,
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Forceirpt = 0x50>>2,
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Boottimeout = 0x60>>2,
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Dbgsel = 0x64>>2,
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Spiintspt = 0xf0>>2,
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Slotisrver = 0xfc>>2,
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/* Control0 */
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Dwidth4 = 1<<1,
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Dwidth1 = 0<<1,
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/* Control1 */
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Srstdata = 1<<26, /* reset data circuit */
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Srstcmd = 1<<25, /* reset command circuit */
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Srsthc = 1<<24, /* reset complete host controller */
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Datatoshift = 16, /* data timeout unit exponent */
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Datatomask = 0xF0000,
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Clkfreq8shift = 8, /* SD clock base divider LSBs */
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Clkfreq8mask = 0xFF00,
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Clkfreqms2shift = 6, /* SD clock base divider MSBs */
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Clkfreqms2mask = 0xC0,
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Clkgendiv = 0<<5, /* SD clock divided */
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Clkgenprog = 1<<5, /* SD clock programmable */
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Clken = 1<<2, /* SD clock enable */
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Clkstable = 1<<1,
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Clkintlen = 1<<0, /* enable internal EMMC clocks */
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/* Cmdtm */
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Indexshift = 24,
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Suspend = 1<<22,
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Resume = 2<<22,
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Abort = 3<<22,
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Isdata = 1<<21,
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Ixchken = 1<<20,
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Crcchken = 1<<19,
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Respmask = 3<<16,
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Respnone = 0<<16,
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Resp136 = 1<<16,
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Resp48 = 2<<16,
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Resp48busy = 3<<16,
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Multiblock = 1<<5,
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Host2card = 0<<4,
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Card2host = 1<<4,
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Autocmd12 = 1<<2,
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Autocmd23 = 2<<2,
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Blkcnten = 1<<1,
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Dmaen = 1<<0,
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/* Interrupt */
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Acmderr = 1<<24,
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Denderr = 1<<22,
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Dcrcerr = 1<<21,
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Dtoerr = 1<<20,
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Cbaderr = 1<<19,
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Cenderr = 1<<18,
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Ccrcerr = 1<<17,
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Ctoerr = 1<<16,
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Err = 1<<15,
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Cardintr = 1<<8,
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Cardinsert = 1<<6,
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Readrdy = 1<<5,
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Writerdy = 1<<4,
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Dmaintr = 1<<3,
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Datadone = 1<<1,
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Cmddone = 1<<0,
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/* Status */
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Present = 1<<18,
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Bufread = 1<<11,
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Bufwrite = 1<<10,
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Readtrans = 1<<9,
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Writetrans = 1<<8,
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Datactive = 1<<2,
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Datinhibit = 1<<1,
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Cmdinhibit = 1<<0,
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};
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static int cmdinfo[64] = {
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[0] Ixchken,
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[2] Resp136,
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[3] Resp48 | Ixchken | Crcchken,
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[6] Resp48 | Ixchken | Crcchken,
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[7] Resp48busy | Ixchken | Crcchken,
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[8] Resp48 | Ixchken | Crcchken,
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[9] Resp136,
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[12] Resp48busy | Ixchken | Crcchken,
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[13] Resp48 | Ixchken | Crcchken,
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[16] Resp48,
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[17] Resp48 | Isdata | Card2host | Ixchken | Crcchken | Dmaen,
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[18] Resp48 | Isdata | Card2host | Multiblock | Blkcnten | Ixchken | Crcchken | Dmaen,
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[24] Resp48 | Isdata | Host2card | Ixchken | Crcchken | Dmaen,
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[25] Resp48 | Isdata | Host2card | Multiblock | Blkcnten | Ixchken | Crcchken | Dmaen,
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[41] Resp48,
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[55] Resp48 | Ixchken | Crcchken,
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};
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typedef struct Ctlr Ctlr;
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struct Ctlr {
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Rendez r;
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u32int *regs;
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int datadone;
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int fastclock;
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ulong extclk;
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int irq;
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};
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static Ctlr emmc;
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static uint
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clkdiv(uint d)
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{
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uint v;
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assert(d < 1<<10);
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v = (d << Clkfreq8shift) & Clkfreq8mask;
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v |= ((d >> 8) << Clkfreqms2shift) & Clkfreqms2mask;
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return v;
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}
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static void
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interrupt(Ureg*, void*)
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{
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u32int *r;
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int i;
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r = emmc.regs;
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i = r[Interrupt];
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r[Interrupt] = i & (Datadone|Err);
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emmc.datadone = i;
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wakeup(&emmc.r);
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}
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static int
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datadone(void*)
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{
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return emmc.datadone;
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}
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static int
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emmcinit(void)
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{
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u32int *r;
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int i;
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emmc.extclk = 100000000;
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emmc.irq = SDIO1IRQ;
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r = vmap(SDIO_BASE, 0x100);
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emmc.regs = r;
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r[Control1] = Srsthc;
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for(i = 0; i < 100; i++){
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delay(10);
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if((r[Control1] & Srsthc) == 0)
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return 0;
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}
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print("emmc: reset timeout!\n");
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return -1;
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}
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static int
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emmcinquiry(char *inquiry, int inqlen)
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{
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uint ver;
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ver = emmc.regs[Slotisrver] >> 16;
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return snprint(inquiry, inqlen,
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"eMMC SD Host Controller %2.2x Version %2.2x",
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ver&0xFF, ver>>8);
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}
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static void
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emmcenable(void)
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{
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int i;
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emmc.regs[Control1] = clkdiv(emmc.extclk / Initfreq - 1) | DTO << Datatoshift |
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Clkgendiv | Clken | Clkintlen;
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for(i = 0; i < 1000; i++){
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delay(1);
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if(emmc.regs[Control1] & Clkstable)
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break;
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}
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if(i == 1000)
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print("SD clock won't initialise!\n");
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emmc.regs[Irptmask] = ~(Dtoerr|Cardintr|Dmaintr);
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intrenable(emmc.irq, interrupt, nil, LEVEL, sdio.name);
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}
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static int
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emmccmd(u32int cmd, u32int arg, u32int *resp)
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{
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ulong now;
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u32int *r;
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u32int c;
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int i;
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assert(cmd < nelem(cmdinfo) && cmdinfo[cmd] != 0);
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c = (cmd << Indexshift) | cmdinfo[cmd];
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r = emmc.regs;
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if(r[Status] & Cmdinhibit){
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print("emmccmd: need to reset Cmdinhibit intr %ux stat %ux\n",
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r[Interrupt], r[Status]);
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r[Control1] |= Srstcmd;
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while(r[Control1] & Srstcmd)
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;
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while(r[Status] & Cmdinhibit)
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;
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}
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if((c & Isdata || (c & Respmask) == Resp48busy) &&
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r[Status] & Datinhibit){
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print("emmccmd: need to reset Datinhibit intr %ux stat %ux\n",
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r[Interrupt], r[Status]);
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r[Control1] |= Srstdata;
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while(r[Control1] & Srstdata)
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;
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while(r[Status] & Datinhibit)
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;
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}
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r[Arg1] = arg;
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if((i = r[Interrupt]) != 0){
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if(i != Cardinsert)
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print("emmc: before command, intr was %ux\n", i);
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r[Interrupt] = i;
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}
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r[Cmdtm] = c;
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now = m->ticks;
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while(((i=r[Interrupt])&(Cmddone|Err)) == 0)
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if((long)(m->ticks-now) > HZ)
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break;
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if((i&(Cmddone|Err)) != Cmddone){
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if((i&~Err) != Ctoerr)
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print("emmc: cmd %ux error intr %ux stat %ux\n", c, i, r[Status]);
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r[Interrupt] = i;
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if(r[Status]&Cmdinhibit){
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r[Control1] |= Srstcmd;
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while(r[Control1]&Srstcmd)
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;
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}
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error(Eio);
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}
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r[Interrupt] = i & ~(Datadone|Readrdy|Writerdy);
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switch(c & Respmask){
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case Resp136:
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resp[0] = r[Resp0]<<8;
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resp[1] = r[Resp0]>>24 | r[Resp1]<<8;
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resp[2] = r[Resp1]>>24 | r[Resp2]<<8;
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resp[3] = r[Resp2]>>24 | r[Resp3]<<8;
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break;
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case Resp48:
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case Resp48busy:
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resp[0] = r[Resp0];
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break;
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case Respnone:
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resp[0] = 0;
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break;
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}
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if((c & Respmask) == Resp48busy){
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r[Irpten] = Datadone|Err;
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tsleep(&emmc.r, datadone, 0, 3000);
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i = emmc.datadone;
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emmc.datadone = 0;
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r[Irpten] = 0;
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if((i & Datadone) == 0)
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print("emmcio: no Datadone after CMD%d\n", cmd);
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if(i & Err)
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print("emmcio: CMD%d error interrupt %ux\n",
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cmd, r[Interrupt]);
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r[Interrupt] = i;
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}
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/*
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* Once card is selected, use faster clock
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*/
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if(cmd == MMCSelect){
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delay(10);
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r[Control1] = clkdiv(emmc.extclk / SDfreq - 1) |
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DTO << Datatoshift | Clkgendiv | Clken | Clkintlen;
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for(i = 0; i < 1000; i++){
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delay(1);
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if(r[Control1] & Clkstable)
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break;
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}
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delay(10);
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emmc.fastclock = 1;
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}
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/*
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* If card bus width changes, change host bus width
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*/
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if(cmd == Setbuswidth)
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switch(arg){
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case 0:
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r[Control0] &= ~Dwidth4;
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break;
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case 2:
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r[Control0] |= Dwidth4;
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break;
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}
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return 0;
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}
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static void
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emmciosetup(int, void *buf, int bsize, int bcount)
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{
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u32int *r;
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uintptr pa;
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int len;
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len = bsize*bcount;
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if(len > (0x1000<<7))
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error(Etoobig);
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pa = PADDR(buf);
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cleandse((uchar*)buf, (uchar*)buf+len);
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clean2pa(pa, pa+len);
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r = emmc.regs;
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r[Sysaddr] = pa;
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r[Blksizecnt] = 7<<12 | bcount<<16 | bsize;
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r[Irpten] = Datadone|Err;
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}
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static void
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emmcio(int write, uchar *buf, int len)
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{
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u32int *r;
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int i;
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tsleep(&emmc.r, datadone, 0, 3000);
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i = emmc.datadone;
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emmc.datadone = 0;
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r = emmc.regs;
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r[Irpten] = 0;
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if((i & Datadone) == 0){
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print("emmcio: %d timeout intr %ux stat %ux\n",
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write, i, r[Status]);
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r[Interrupt] = i;
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error(Eio);
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}
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if(i & Err){
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print("emmcio: %d error intr %ux stat %ux\n",
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write, r[Interrupt], r[Status]);
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r[Interrupt] = i;
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error(Eio);
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}
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if(i)
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r[Interrupt] = i;
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if(!write){
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uintptr pa = PADDR(buf);
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invaldse((uchar*)buf, (uchar*)buf+len);
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inval2pa(pa, pa+len);
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}
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}
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SDio sdio = {
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"emmc",
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emmcinit,
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emmcenable,
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emmcinquiry,
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emmccmd,
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emmciosetup,
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emmcio,
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};
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