4f85115526
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
559 lines
9.1 KiB
C
559 lines
9.1 KiB
C
/*
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* pci mmc controller.
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*
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* initially written for X230 Ricoh MMC controller.
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* cmdinfo[] table stolen from bcm/emmc.c, thanks richard.
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*
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* for sdhc documentation see: https://www.sdcard.org/
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/pci.h"
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#include "../port/sd.h"
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/* registers */
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enum {
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Rsdma = 0x00,
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Rbsize = 0x04,
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Rbcount = 0x06,
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Rarg = 0x08,
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Rmode = 0x0C,
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Rcmd = 0x0E,
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Rresp0 = 0x10,
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Rresp1 = 0x14,
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Rresp2 = 0x18,
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Rresp3 = 0x1C,
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Rdat0 = 0x20,
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Rdat1 = 0x22,
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Rpres = 0x24,
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Rhc = 0x28,
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Rpwr = 0x29,
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Rbgc = 0x2A,
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Rwkc = 0x2B,
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Rclc = 0x2C,
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Rtmc = 0x2E,
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Rsrst = 0x2F,
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Rnis = 0x30,
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Reis = 0x32,
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Rnie = 0x34,
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Reie = 0x36,
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Rnise = 0x38,
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Reise = 0x3A,
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Ra12 = 0x3C,
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Rcap = 0x40,
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Rrcap = 0x44,
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Rxcap = 0x48,
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Rrxcap = 0x4C,
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Rfea12 = 0x50,
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Rfeei = 0x52,
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Radmasr = 0x54,
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Radmaba = 0x58,
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Rsists = 0xFC,
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Rhcver = 0xFE,
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};
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/* sts bits */
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enum {
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Seint = 1<<15,
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Snint = 1<<8,
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Srem = 1<<7,
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Sins = 1<<6,
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Srrdy = 1<<5,
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Swrdy = 1<<4,
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Sdint = 1<<3,
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Sbge = 1<<2,
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Strac = 1<<1,
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Scmdc = 1<<0,
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Smask = 0x81ff,
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};
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/* err bits */
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enum {
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Ea12 = 1<<8,
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Elimit = 1<<7,
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Edebit = 1<<6,
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Edcrc = 1<<5,
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Edtmo = 1<<4,
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Ecidx = 1<<3,
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Ecebit = 1<<2,
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Eccrc = 1<<1,
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Ectmo = 1<<0,
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Emask = 0x1ff,
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};
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/* present bits */
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enum {
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Plsig = 1<<24,
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Pldat3 = 1<<23,
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Pldat2 = 1<<22,
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Pldat1 = 1<<21,
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Pldat0 = 1<<20,
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Ppswit = 1<<19,
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Pcrddt = 1<<18,
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Pcrdst = 1<<17,
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Pcrdin = 1<<16,
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Pbufrd = 1<<11,
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Pbufwr = 1<<10,
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Ptrard = 1<<9,
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Ptrawr = 1<<8,
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Pdat = 1<<2,
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Pinhbc = 1<<1,
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Pinhbd = 1<<0,
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};
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/* Rmode bits */
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enum {
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Mblk = 1<<5,
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Mrd = 1<<4,
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Mwr = 0<<4,
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Ma12 = 1<<2,
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Mcnt = 1<<1,
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Mdma = 1<<0,
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};
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/* command bits */
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enum {
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Abort = 3<<6,
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Isdata = 1<<5,
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Ixchken = 1<<4,
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Crcchken = 1<<3,
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Respmask = 3,
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Respnone = 0,
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Resp48busy = 3,
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Resp48 = 2,
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Resp136 = 1,
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};
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/* fake for cmdinfo */
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enum {
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Blkcnten = Mblk << 8,
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Multiblock = Mcnt << 8,
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Card2host = Mrd << 8,
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Host2card = Mwr << 8,
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};
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static int cmdinfo[64] = {
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[0] Ixchken,
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[2] Resp136,
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[3] Resp48 | Ixchken | Crcchken,
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[6] Resp48 | Ixchken | Crcchken,
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[7] Resp48busy | Ixchken | Crcchken,
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[8] Resp48 | Ixchken | Crcchken,
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[9] Resp136,
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[12] Resp48busy | Ixchken | Crcchken,
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[13] Resp48 | Ixchken | Crcchken,
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[16] Resp48,
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[17] Resp48 | Isdata | Card2host | Ixchken | Crcchken,
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[18] Resp48 | Isdata | Card2host | Multiblock | Blkcnten | Ixchken | Crcchken,
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[24] Resp48 | Isdata | Host2card | Ixchken | Crcchken,
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[25] Resp48 | Isdata | Host2card | Multiblock | Blkcnten | Ixchken | Crcchken,
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[41] Resp48,
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[55] Resp48 | Ixchken | Crcchken,
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};
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typedef struct Ctlr Ctlr;
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struct Ctlr {
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Lock;
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Pcidev *pdev;
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u8int *mmio;
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int change;
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u32int waitsts;
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u32int waitmsk;
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Rendez r;
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struct {
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int bcount;
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int bsize;
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} io;
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};
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static Ctlr pmmc[1];
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#define CR8(c, off) *((u8int*)(c->mmio + off))
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#define CR16(c, off) *((u16int*)(c->mmio + off))
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#define CR32(c, off) *((u32int*)(c->mmio + off))
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static void
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mmcinterrupt(Ureg*, void *arg)
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{
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u16int nis, eis;
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Ctlr *c;
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c = arg;
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nis = CR16(c, Rnis);
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if((nis & Smask) == 0)
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return; /* not for us */
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CR16(c, Rnis) = nis; /* ack */
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ilock(c);
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eis = 0;
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if((nis & Seint) != 0){
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eis = CR16(c, Reis);
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CR16(c, Reis) = eis; /* ack */
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}
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if((nis & Snint) != 0)
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CR16(c, Rnie) |= Snint; /* ack */
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if((nis & (Srem|Sins)) != 0)
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c->change = 1;
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c->waitsts |= nis | (eis << 16);
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if((c->waitsts & c->waitmsk) != 0)
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wakeup(&c->r);
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iunlock(c);
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}
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static int
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pmmcinit(void)
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{
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Pcidev *p;
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p = nil;
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while((p = pcimatch(p, 0, 0)) != nil){
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if(p->ccrb == 8 && p->ccru == 5)
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break;
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if(p->vid == 0x1180){ /* Ricoh */
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if(p->did == 0xe822) /* 5U822 SD/MMC */
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break;
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if(p->did == 0xe823) /* 5U823 SD/MMC */
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break;
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}
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}
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if(p == nil || p->mem[0].size < 256 || (p->mem[0].bar & 1) != 0)
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return -1;
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pmmc->mmio = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
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if(pmmc->mmio == nil)
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return -1;
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pmmc->pdev = p;
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pcienable(p);
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if(p->did == 0x1180 && p->vid == 0xe823){ /* Ricoh */
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/* Enable SD2.0 mode. */
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pcicfgw8(p, 0xf9, 0xfc);
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pcicfgw8(p, 0x150, 0x10);
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pcicfgw8(p, 0xf9, 0x00);
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/*
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* Some SD/MMC cards don't work with the default base
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* clock frequency of 200MHz. Lower it to 50Hz.
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*/
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pcicfgw8(p, 0xfc, 0x01);
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pcicfgw8(p, 0xe1, 50);
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pcicfgw8(p, 0xfc, 0x00);
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}
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return 0;
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}
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static int
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pmmcinquiry(char *inquiry, int inqlen)
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{
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return snprint(inquiry, inqlen, "MMC Host Controller");
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}
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static void
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softreset(Ctlr *c, int all)
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{
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int i, m;
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m = all ? 1 : 6;
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CR8(c, Rsrst) = m;
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for(i=10; i>=0; i--){
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if((CR8(c, Rsrst) & m) == 0)
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break;
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delay(10);
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CR8(c, Rsrst) = 0;
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}
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if(i < 0) iprint("mmc: didnt reset\n");
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}
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static void
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setpower(Ctlr *c, int on)
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{
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enum {
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Vcap18 = 1<<26, Vset18 = 0x05,
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Vcap30 = 1<<25, Vset30 = 0x06,
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Vcap33 = 1<<24, Vset33 = 0x07,
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};
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u32int cap, v;
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cap = CR32(c, Rcap);
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v = Vset18;
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if(cap & Vcap30)
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v = Vset30;
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if(cap & Vcap33)
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v = Vset33;
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CR8(c, Rpwr) = on ? ((v<<1) | 1) : 0;
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}
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static void
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setclkfreq(Ctlr *c, int khz)
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{
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u32int caps, intfreq;
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int i, div;
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if(khz == 0){
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CR16(c, Rclc) |= ~4; /* sd clock disable */
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return;
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}
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caps = CR32(c, Rcap);
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intfreq = 1000*((caps >> 8) & 0x3f);
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for(div = 1; div <= 256; div <<= 1){
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if((intfreq / div) <= khz){
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div >>= 1;
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break;
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}
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}
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CR16(c, Rclc) = 0;
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CR16(c, Rclc) = div<<8;
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CR16(c, Rclc) |= 1; /* int clock enable */
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for(i=1000; i>=0; i--){
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if(CR16(c, Rclc) & 2) /* int clock stable */
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break;
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delay(10);
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}
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if(i < 0) iprint("mmc: clock didnt stabilize\n");
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CR16(c, Rclc) |= 4; /* sd clock enable */
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}
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static void
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resetctlr(Ctlr *c)
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{
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u32int m;
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ilock(c);
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CR16(c, Rnise) = 0; /* interrupts off */
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c->change = 0;
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c->waitmsk = c->waitsts = 0;
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softreset(c, 1);
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/* set timeout */
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CR8(c, Rtmc) = 0x0e;
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m = Srem | Sins | Srrdy | Swrdy | Sdint | Sbge | Strac | Scmdc;
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CR16(c, Rnie) = m;
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CR16(c, Reie) = Emask;
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CR16(c, Rnise) = m;
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CR16(c, Reise) = Emask;
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setpower(c, 1);
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setclkfreq(c, 400);
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iunlock(c);
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}
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static int
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waitcond(void *arg)
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{
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Ctlr *c;
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c = arg;
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return (c->waitsts & c->waitmsk) != 0;
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}
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static u32int
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intrwait(Ctlr *c, u32int mask, int tmo)
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{
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u32int status;
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ilock(c);
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c->waitmsk = Seint | mask;
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iunlock(c);
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do {
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if(!waserror()){
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tsleep(&c->r, waitcond, c, 100);
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poperror();
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}
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mmcinterrupt(nil, c);
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if(waitcond(c))
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break;
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tmo -= 100;
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} while(tmo > 0);
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ilock(c);
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c->waitmsk = 0;
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status = c->waitsts;
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c->waitsts &= ~(status & mask);
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if((status & mask) == 0 || (status & Seint) != 0){
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/* abort command on timeout/error interrupt */
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softreset(c, 0);
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c->waitsts = 0;
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status = 0;
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}
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iunlock(c);
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return status & mask;
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}
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static void
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pmmcenable(void)
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{
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Pcidev *p;
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Ctlr *c;
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c = pmmc;
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p = c->pdev;
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resetctlr(c);
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intrenable(p->intl, mmcinterrupt, c, p->tbdf, "mmc");
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}
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static int
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pmmccmd(u32int cmd, u32int arg, u32int *resp)
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{
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u32int status;
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int i, mode;
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Ctlr *c;
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if(cmd >= nelem(cmdinfo) || cmdinfo[cmd] == 0)
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error(Egreg);
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mode = cmdinfo[cmd] >> 8;
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cmd = (cmd << 8) | (cmdinfo[cmd] & 0xFF);
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c = pmmc;
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if(c->change)
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resetctlr(c);
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if((CR32(c, Rpres) & Pcrdin) == 0)
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error("no card");
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status = Pinhbc;
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if((cmd & Isdata) != 0 || (cmd & Respmask) == Resp48busy)
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status |= Pinhbd;
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for(i=1000; (CR32(c, Rpres) & status) != 0 && i>=0; i--)
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delay(1);
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if(i < 0)
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error(Eio);
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ilock(c);
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if((mode & (Mcnt|Mblk)) == (Mcnt|Mblk)){
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CR16(c, Rbsize) = c->io.bsize;
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CR16(c, Rbcount) = c->io.bcount;
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}
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CR32(c, Rarg) = arg;
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CR16(c, Rmode) = mode;
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CR16(c, Rcmd) = cmd;
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iunlock(c);
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if(!intrwait(c, Scmdc, 1000))
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error(Eio);
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switch(cmd & Respmask){
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case Resp48busy:
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resp[0] = CR32(c, Rresp0);
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if(!intrwait(c, Strac, 3000))
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error(Eio);
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break;
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case Resp48:
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resp[0] = CR32(c, Rresp0);
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break;
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case Resp136:
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resp[0] = CR32(c, Rresp0)<<8;
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resp[1] = CR32(c, Rresp0)>>24 | CR32(c, Rresp1)<<8;
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resp[2] = CR32(c, Rresp1)>>24 | CR32(c, Rresp2)<<8;
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resp[3] = CR32(c, Rresp2)>>24 | CR32(c, Rresp3)<<8;
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break;
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case Respnone:
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resp[0] = 0;
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break;
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}
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cmd >>= 8;
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if(cmd == 0x06){ /* buswidth */
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switch(arg){
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case 0:
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CR8(c, Rhc) &= ~2;
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break;
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case 2:
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CR8(c, Rhc) |= 2;
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break;
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}
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}
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return 0;
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}
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static void
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pmmciosetup(int write, void *buf, int bsize, int bcount)
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{
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Ctlr *c;
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USED(write);
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USED(buf);
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if(bsize == 0 || (bsize & 3) != 0)
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error(Egreg);
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c = pmmc;
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c->io.bsize = bsize;
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c->io.bcount = bcount;
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}
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static void
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readblock(Ctlr *c, uchar *buf, int len)
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{
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for(len >>= 2; len > 0; len--){
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*((u32int*)buf) = CR32(c, Rdat0);
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buf += 4;
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}
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}
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static void
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writeblock(Ctlr *c, uchar *buf, int len)
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{
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for(len >>= 2; len > 0; len--){
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CR32(c, Rdat0) = *((u32int*)buf);
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buf += 4;
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}
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}
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static void
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pmmcio(int write, uchar *buf, int len)
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{
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Ctlr *c;
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int n;
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c = pmmc;
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if(len != c->io.bsize*c->io.bcount)
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error(Egreg);
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while(len > 0){
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if(!intrwait(c, write ? Swrdy : Srrdy, 3000))
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error(Eio);
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n = len;
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if(n > c->io.bsize)
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n = c->io.bsize;
|
|
if(write)
|
|
writeblock(c, buf, n);
|
|
else
|
|
readblock(c, buf, n);
|
|
len -= n;
|
|
buf += n;
|
|
}
|
|
if(!intrwait(c, Strac, 1000))
|
|
error(Eio);
|
|
}
|
|
|
|
SDio sdio = {
|
|
"pmmc",
|
|
pmmcinit,
|
|
pmmcenable,
|
|
pmmcinquiry,
|
|
pmmccmd,
|
|
pmmciosetup,
|
|
pmmcio,
|
|
};
|