4f85115526
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
919 lines
17 KiB
C
919 lines
17 KiB
C
/*
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* intel 10GB ethernet pci-express driver
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* 6.0.0: net 02.00.00 8086/15c8 11 0:dfc0000c 2097152 4:dfe0400c 16384
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* Intel Corporation Ethernet Connection X553/X550-AT 10GBASE-T
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/pci.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "../port/etherif.h"
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enum {
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/* general */
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Ctrl = 0x00000/4, /* Device Control */
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Status = 0x00008/4, /* Device Status */
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Ctrlext = 0x00018/4, /* Extended Device Control */
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Tcptimer = 0x0004c/4, /* tcp timer */
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/* nvm */
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Eec = 0x10010/4, /* eeprom/flash control */
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Eemngctl = 0x10110/4, /* Manageability EEPROM-Mode Control */
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/* interrupt */
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Icr = 0x00800/4, /* interrupt cause read */
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Ics = 0x00808/4, /* " set */
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Ims = 0x00880/4, /* " mask read/set */
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Imc = 0x00888/4, /* " mask clear */
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Iac = 0x00810/4, /* " auto clear */
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Iam = 0x00890/4, /* " auto mask enable */
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Itr = 0x00820/4, /* " throttling rate (0-19) */
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Ivar = 0x00900/4, /* " vector allocation regs. */
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/* rx dma */
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Rdbal = 0x01000/4, /* rx desc base low (0-63) +0x40n */
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Rdbah = 0x01004/4, /* " high */
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Rdlen = 0x01008/4, /* " length */
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Rdh = 0x01010/4, /* " head */
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Rdt = 0x01018/4, /* " tail */
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Rxdctl = 0x01028/4, /* " control */
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Srrctl = 0x02100/4, /* split and replication rx ctl. */
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Rdrxctl = 0x02f00/4, /* rx dma control */
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Rxpbsize = 0x03c00/4, /* rx packet buffer size */
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Rxctrl = 0x03000/4, /* rx control */
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/* rx */
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Rxcsum = 0x05000/4, /* rx checksum control */
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Mcstctrl = 0x05090/4, /* multicast control register */
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Mta = 0x05200/4, /* multicast table array (0-127) */
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Ral = 0x05400/4, /* rx address low */
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Rah = 0x05404/4,
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Vfta = 0x0a000/4, /* vlan filter table array. */
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Fctrl = 0x05080/4, /* filter control */
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/* tx */
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Tdbal = 0x06000/4, /* tx desc base low +0x40n */
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Tdbah = 0x06004/4, /* " high */
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Tdlen = 0x06008/4, /* " len */
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Tdh = 0x06010/4, /* " head */
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Tdt = 0x06018/4, /* " tail */
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Txdctl = 0x06028/4, /* " control */
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Dmatxctl = 0x04a80/4,
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/* mac */
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Hlreg0 = 0x04240/4, /* highlander control reg 0 */
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Hlreg1 = 0x04244/4, /* highlander control reg 1 (ro) */
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Maxfrs = 0x04268/4, /* max frame size */
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Links = 0x042a4/4, /* link status */
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};
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enum {
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/* Ctrl */
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Rst = 1<<26, /* full nic reset */
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/* Ctrlext */
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Drvload = 1<<28, /* Driver Load */
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/* Eec */
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AutoRd = 1<<9, /* NVM auto read done */
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/* Eemngctl */
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CfgDone0 = 1<<18, /* Configuration Done Port 0 */
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CfgDone1 = 1<<19, /* Configuration Done Port 1 */
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/* Txdctl */
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Pthresh = 0, /* prefresh threshold shift in bits */
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Hthresh = 8, /* host buffer minimum threshold */
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Wthresh = 16, /* writeback threshold */
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Ten = 1<<25,
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/* Fctrl */
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Bam = 1<<10, /* broadcast accept mode */
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Upe = 1<<9, /* unicast promiscuous */
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Mpe = 1<<8, /* multicast promiscuous */
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/* Rxdctl */
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Renable = 1<<25,
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/* Dmatxctl */
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Txen = 1<<0,
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/* Rxctl */
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Rxen = 1<<0,
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/* Rdrxctl */
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Dmaidone = 1<<3,
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/* Rxcsum */
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Ippcse = 1<<12, /* ip payload checksum enable */
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/* Mcstctrl */
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Mo = 0, /* multicast offset 47:36 */
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Mfe = 1<<2, /* multicast filter enable */
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/* Rah */
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Av = 1<<31,
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/* interrupts */
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Irx0 = 1<<0, /* driver defined - rx interrupt */
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Itx0 = 1<<1, /* driver defined - tx interrupt */
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Lsc = 1<<20, /* link status change */
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/* Ivar Interrupt Vector Allocation Register */
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Intalloc0 = 0, /* Map the 0th queue Rx interrupt to the 0th bit of EICR register */
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Intallocval0 = 1<<7,
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intalloc1 = 1<<8, /* Map the 0th queue Tx interrupt to the 1st bit of EICR register */
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Intallocval1 = 1<<15,
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/* Links */
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Lnkup = 1<<30,
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Lnkspd = 1<<29,
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/* Hlreg0 */
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Jumboen = 1<<2,
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};
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typedef struct {
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uint reg;
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char *name;
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} Stat;
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static
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Stat stattab[] = {
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0x4000, "crc error",
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0x4004, "illegal byte",
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0x4008, "short packet",
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0x3fa0, "missed pkt0",
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0x4034, "mac local flt",
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0x4038, "mac rmt flt",
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0x4040, "rx length err",
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0x405c, "rx 040",
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0x4060, "rx 07f",
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0x4064, "rx 100",
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0x4068, "rx 200",
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0x406c, "rx 3ff",
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0x4070, "rx big",
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0x4074, "rx ok",
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0x4078, "rx bcast",
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0x407c, "rx mcast",
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0x4080, "tx ok",
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0x40a4, "rx runt",
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0x40a8, "rx frag",
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0x40ac, "rx ovrsz",
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0x40b0, "rx jab",
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0x40d0, "rx pkt",
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0x40d4, "tx pkt",
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0x40d8, "tx 040",
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0x40dc, "tx 07f",
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0x40e0, "tx 100",
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0x40e4, "tx 200",
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0x40e8, "tx 3ff",
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0x40ec, "tx big",
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0x40f0, "tx mcast",
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0x40f4, "tx bcast",
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0x4120, "xsum err",
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};
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/* status */
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enum {
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Pif = 1<<7, /* past exact filter (sic) */
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Ipcs = 1<<6, /* ip checksum calcuated */
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L4cs = 1<<5, /* layer 2 */
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Udpcs = 1<<4, /* udp checksum calcuated */
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Vp = 1<<3, /* 802.1q packet matched vet */
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Reop = 1<<1, /* end of packet */
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Rdd = 1<<0, /* descriptor done */
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};
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typedef struct {
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u32int addr[2];
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ushort length;
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ushort cksum;
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uchar status;
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uchar errors;
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ushort vlan;
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} Rd;
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enum {
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/* Td cmd */
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Rs = 1<<3,
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Ic = 1<<2,
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Ifcs = 1<<1,
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Teop = 1<<0,
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/* Td status */
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Tdd = 1<<0,
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};
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typedef struct {
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u32int addr[2];
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u16int length;
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uchar cso;
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uchar cmd;
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uchar status;
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uchar css;
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ushort vlan;
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} Td;
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enum {
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Factive = 1<<0,
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Fstarted = 1<<1,
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};
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typedef struct {
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Pcidev *p;
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Ether *edev;
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uintptr io;
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u32int *reg;
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u32int *regmsi;
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uchar flag;
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int nrd;
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int ntd;
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int rbsz;
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Lock slock;
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Lock alock;
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QLock tlock;
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Rendez lrendez;
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Rendez trendez;
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Rendez rrendez;
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uint im;
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uint lim;
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uint rim;
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uint tim;
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Lock imlock;
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char *alloc;
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Rd *rdba;
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Block **rb;
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uint rdt;
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uint rdfree;
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Td *tdba;
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uint tdh;
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uint tdt;
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Block **tb;
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uchar ra[Eaddrlen];
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u32int mta[128];
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ulong stats[nelem(stattab)];
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uint speeds[3];
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} Ctlr;
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/* tweakable paramaters */
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enum {
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Mtu = 12*1024,
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Nrd = 256,
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Ntd = 256,
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Nrb = 256,
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};
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static Ctlr *ctlrtab[4];
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static int nctlr;
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static void
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readstats(Ctlr *c)
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{
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int i;
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lock(&c->slock);
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for(i = 0; i < nelem(c->stats); i++)
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c->stats[i] += c->reg[stattab[i].reg >> 2];
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unlock(&c->slock);
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}
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static int speedtab[] = {
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0,
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1000,
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10000,
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};
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static long
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ifstat(Ether *e, void *a, long n, ulong offset)
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{
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uint i, *t;
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char *s, *p, *q;
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Ctlr *c;
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p = s = smalloc(READSTR);
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q = p + READSTR;
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c = e->ctlr;
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readstats(c);
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for(i = 0; i < nelem(stattab); i++)
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if(c->stats[i] > 0)
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p = seprint(p, q, "%.10s %uld\n", stattab[i].name,
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c->stats[i]);
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t = c->speeds;
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p = seprint(p, q, "speeds: 0:%d 1000:%d 10000:%d\n", t[0], t[1], t[2]);
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seprint(p, q, "rdfree %d rdh %d rdt %d\n", c->rdfree, c->reg[Rdt],
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c->reg[Rdh]);
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n = readstr(offset, a, n, s);
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free(s);
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return n;
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}
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static void
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im(Ctlr *c, int i)
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{
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ilock(&c->imlock);
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c->im |= i;
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c->reg[Ims] = c->im;
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iunlock(&c->imlock);
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}
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static int
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lim(void *v)
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{
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return ((Ctlr*)v)->lim != 0;
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}
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static void
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lproc(void *v)
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{
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int r, i;
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Ctlr *c;
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Ether *e;
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e = v;
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c = e->ctlr;
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while(waserror())
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;
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for (;;) {
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r = c->reg[Links];
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e->link = (r & Lnkup) != 0;
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i = 0;
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if(e->link)
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i = 1 + ((r & Lnkspd) != 0);
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c->speeds[i]++;
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e->mbps = speedtab[i];
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c->lim = 0;
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im(c, Lsc);
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sleep(&c->lrendez, lim, c);
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c->lim = 0;
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}
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}
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static long
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ctl(Ether *, void *, long)
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{
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error(Ebadarg);
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return -1;
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}
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#define Next(x, m) (((x)+1) & (m))
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static int
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cleanup(Ctlr *c, int tdh)
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{
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Block *b;
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uint m, n;
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m = c->ntd - 1;
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while(c->tdba[n = Next(tdh, m)].status & Tdd){
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tdh = n;
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b = c->tb[tdh];
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c->tb[tdh] = 0;
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freeb(b);
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c->tdba[tdh].status = 0;
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}
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return tdh;
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}
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static void
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transmit(Ether *e)
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{
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uint i, m, tdt, tdh;
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Ctlr *c;
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Block *b;
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Td *t;
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c = e->ctlr;
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if(!canqlock(&c->tlock)){
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im(c, Itx0);
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return;
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}
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tdh = c->tdh = cleanup(c, c->tdh);
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tdt = c->tdt;
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m = c->ntd - 1;
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for(i = 0; i < 8; i++){
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if(Next(tdt, m) == tdh){
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im(c, Itx0);
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break;
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}
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if(!(b = qget(e->oq)))
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break;
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t = c->tdba + tdt;
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t->addr[0] = PCIWADDR(b->rp);
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t->length = BLEN(b);
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t->cmd = Rs | Ifcs | Teop;
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c->tb[tdt] = b;
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tdt = Next(tdt, m);
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}
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if(i){
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c->tdt = tdt;
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c->reg[Tdt] = tdt;
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}
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qunlock(&c->tlock);
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}
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static int
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tim(void *c)
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{
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return ((Ctlr*)c)->tim != 0;
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}
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static void
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tproc(void *v)
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{
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Ctlr *c;
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Ether *e;
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e = v;
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c = e->ctlr;
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while(waserror())
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;
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for (;;) {
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sleep(&c->trendez, tim, c); /* transmit kicks us */
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c->tim = 0;
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transmit(e);
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}
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}
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static void
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rxinit(Ctlr *c)
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{
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int i;
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Block *b;
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c->reg[Rxctrl] &= ~Rxen;
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/* Pg 144 Step 2
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Receive buffers of appropriate size should be allocated
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and pointers to these buffers should be stored in the
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descriptor ring - replinish() does this? */
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for(i = 0; i < c->nrd; i++){
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b = c->rb[i];
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c->rb[i] = 0;
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if(b)
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freeb(b);
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}
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c->rdfree = 0;
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c->reg[Fctrl] |= Bam;
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c->reg[Rxcsum] |= Ippcse;
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c->reg[Srrctl] = c->rbsz / 1024;
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c->reg[Maxfrs] = c->rbsz << 16;
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c->reg[Hlreg0] |= Jumboen;
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c->reg[Rdbal] = PCIWADDR(c->rdba);
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c->reg[Rdbah] = 0;
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c->reg[Rdlen] = c->nrd*sizeof(Rd);
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c->reg[Rdh] = 0;
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c->reg[Rdt] = c->rdt = 0;
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c->reg[Rxdctl] = Renable;
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while((c->reg[Rxdctl] & Renable) == 0)
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;
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/* TODO? bump the tail pointer RDT to enable descriptors
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fetching by setting it to the ring length minus 1. Pg 145 */
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c->reg[Rxctrl] |= Rxen;
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}
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static void
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replenish(Ctlr *c, uint rdh)
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{
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int rdt, m, i;
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Block *b;
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Rd *r;
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m = c->nrd - 1;
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i = 0;
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for(rdt = c->rdt; Next(rdt, m) != rdh; rdt = Next(rdt, m)){
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b = allocb(c->rbsz+BY2PG);
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b->rp = (uchar*)PGROUND((uintptr)b->base);
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b->wp = b->rp;
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c->rb[rdt] = b;
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r = c->rdba + rdt;
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r->addr[0] = PCIWADDR(b->rp);
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r->status = 0;
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c->rdfree++;
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i++;
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}
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if(i)
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c->reg[Rdt] = c->rdt = rdt;
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}
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static int
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rim(void *v)
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{
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return ((Ctlr*)v)->rim != 0;
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}
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|
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static uchar zeroea[Eaddrlen];
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|
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static void
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rproc(void *v)
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{
|
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uint m, rdh;
|
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Block *b;
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Ctlr *c;
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Ether *e;
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Rd *r;
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e = v;
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c = e->ctlr;
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m = c->nrd - 1;
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rdh = 0;
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while(waserror())
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;
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loop:
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|
replenish(c, rdh);
|
|
im(c, Irx0);
|
|
sleep(&c->rrendez, rim, c);
|
|
loop1:
|
|
c->rim = 0;
|
|
if(c->nrd - c->rdfree >= 16)
|
|
replenish(c, rdh);
|
|
r = c->rdba + rdh;
|
|
if(!(r->status & Rdd))
|
|
goto loop; /* UGH */
|
|
b = c->rb[rdh];
|
|
c->rb[rdh] = 0;
|
|
b->wp += r->length;
|
|
if((r->status & 1)){
|
|
if(r->status & Ipcs)
|
|
b->flag |= Bipck;
|
|
b->checksum = r->cksum;
|
|
}
|
|
// r->status = 0;
|
|
etheriq(e, b);
|
|
c->rdfree--;
|
|
rdh = Next(rdh, m);
|
|
goto loop1; /* UGH */
|
|
}
|
|
|
|
static void
|
|
promiscuous(void *a, int on)
|
|
{
|
|
Ctlr *c;
|
|
Ether *e;
|
|
|
|
e = a;
|
|
c = e->ctlr;
|
|
if(on)
|
|
c->reg[Fctrl] |= Upe | Mpe;
|
|
else
|
|
c->reg[Fctrl] &= ~(Upe | Mpe);
|
|
}
|
|
|
|
static void
|
|
multicast(void *a, uchar *ea, int on)
|
|
{
|
|
int b, i;
|
|
Ctlr *c;
|
|
Ether *e;
|
|
|
|
e = a;
|
|
c = e->ctlr;
|
|
|
|
/*
|
|
* multiple ether addresses can hash to the same filter bit,
|
|
* so it's never safe to clear a filter bit.
|
|
* if we want to clear filter bits, we need to keep track of
|
|
* all the multicast addresses in use, clear all the filter bits,
|
|
* then set the ones corresponding to in-use addresses.
|
|
*
|
|
* Extracts the 12 bits, from a multicast address, to determine which
|
|
* bit-vector to set in the multicast table. The hardware uses 12 bits, from
|
|
* incoming rx multicast addresses, to determine the bit-vector to check in
|
|
* the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
|
|
* by the MO field of the MCSTCTRL. The MO field is set during initialization
|
|
* to mc_filter_type.
|
|
*
|
|
* The MTA is a register array of 128 32-bit registers. It is treated
|
|
* like an array of 4096 bits. We want to set bit
|
|
* BitArray[vector_value]. So we figure out what register the bit is
|
|
* in, read it, OR in the new bit, then write back the new value. The
|
|
* register is determined by the upper 7 bits of the vector value and
|
|
* the bit within that register are determined by the lower 5 bits of
|
|
* the value.
|
|
*
|
|
* when Mcstctrl.Mo == 0, use bits [47:36] of the address
|
|
* register index = bits [47:41]
|
|
* which bit in the above register = bits [40:36]
|
|
*/
|
|
i = ea[5] >> 1; /* register index = 47:41 (7 bits) */
|
|
b = (ea[5]&1)<<4 | ea[4]>>4; /* which bit in the above register = 40:36 (5 bits) */
|
|
b = 1 << b;
|
|
if(on)
|
|
c->mta[i] |= b;
|
|
// else
|
|
// c->mta[i] &= ~b;
|
|
c->reg[Mta+i] = c->mta[i];
|
|
c->reg[Mcstctrl] = Mfe;
|
|
/* for(i = 0; i < 128; i++) c->reg[Mta + i] = -1; brute force it to work for testing */
|
|
}
|
|
|
|
static int
|
|
detach(Ctlr *c)
|
|
{
|
|
int i;
|
|
u32int l, h;
|
|
|
|
l = c->reg[Ral];
|
|
h = c->reg[Rah];
|
|
if (h & Av) {
|
|
c->ra[0] = l & 0xFF;
|
|
c->ra[1] = l>>8 & 0xFF;
|
|
c->ra[2] = l>>16 & 0xFF;
|
|
c->ra[3] = l>>24 & 0xFF;
|
|
c->ra[4] = h & 0xFF;
|
|
c->ra[5] = h>>8 & 0xFF;
|
|
}
|
|
c->reg[Imc] = ~0;
|
|
c->reg[Ctrl] |= Rst;
|
|
for(i = 0; i < 100; i++){
|
|
delay(1);
|
|
if((c->reg[Ctrl] & Rst) == 0)
|
|
break;
|
|
}
|
|
if (i >= 100)
|
|
return -1;
|
|
delay(10);
|
|
|
|
/* not cleared by reset; kill it manually. */
|
|
for(i = 1; i < 16; i++)
|
|
c->reg[Rah + i] &= ~(1 << 31);
|
|
for(i = 0; i < 128; i++)
|
|
c->reg[Mta + i] = 0;
|
|
for(i = 1; i < 640; i++)
|
|
c->reg[Vfta + i] = 0;
|
|
c->reg[Ctrlext] &= ~Drvload; /* driver works without this */
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
shutdown(Ether *e)
|
|
{
|
|
detach(e->ctlr);
|
|
}
|
|
|
|
static int
|
|
reset(Ctlr *c)
|
|
{
|
|
int i;
|
|
|
|
while((c->reg[Eec] & AutoRd) == 0)
|
|
;
|
|
while((c->reg[Eemngctl] & CfgDone0) == 0)
|
|
;
|
|
while((c->reg[Eemngctl] & CfgDone1) == 0)
|
|
;
|
|
while((c->reg[Rdrxctl] & Dmaidone) == 0)
|
|
;
|
|
if(detach(c)){
|
|
print("iX550: reset timeout\n");
|
|
return -1;
|
|
}
|
|
while((c->reg[Eec] & AutoRd) == 0)
|
|
;
|
|
while((c->reg[Eemngctl] & CfgDone0) == 0)
|
|
;
|
|
while((c->reg[Eemngctl] & CfgDone1) == 0)
|
|
;
|
|
while((c->reg[Rdrxctl] & Dmaidone) == 0)
|
|
;
|
|
readstats(c);
|
|
for(i = 0; i<nelem(c->stats); i++)
|
|
c->stats[i] = 0;
|
|
|
|
/* configure interrupt mapping */
|
|
c->reg[Ivar] = Intalloc0 | Intallocval0 | intalloc1 | Intallocval1;
|
|
|
|
/* interrupt throttling goes here. */
|
|
for(i = Itr; i < Itr + 20; i++)
|
|
c->reg[i] = 1<<3; /* 1 interval */
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
txinit(Ctlr *c)
|
|
{
|
|
Block *b;
|
|
int i;
|
|
|
|
c->reg[Txdctl] = 16<<Wthresh | 16<<Pthresh;
|
|
for(i = 0; i < c->ntd; i++){
|
|
b = c->tb[i];
|
|
c->tb[i] = 0;
|
|
if(b)
|
|
freeb(b);
|
|
}
|
|
memset(c->tdba, 0, c->ntd * sizeof(Td));
|
|
c->reg[Tdbal] = PCIWADDR(c->tdba);
|
|
c->reg[Tdbah] = 0;
|
|
c->reg[Tdlen] = c->ntd*sizeof(Td);
|
|
c->reg[Tdh] = 0;
|
|
c->reg[Tdt] = 0;
|
|
c->tdh = c->ntd - 1;
|
|
c->tdt = 0;
|
|
|
|
c->reg[Txdctl] |= Ten;
|
|
c->reg[Dmatxctl] |= Txen;
|
|
|
|
}
|
|
|
|
static void
|
|
attach(Ether *e)
|
|
{
|
|
Ctlr *c;
|
|
int t;
|
|
char buf[KNAMELEN];
|
|
|
|
c = e->ctlr;
|
|
c->edev = e; /* point back to Ether* */
|
|
lock(&c->alock);
|
|
if(c->alloc){
|
|
unlock(&c->alock);
|
|
return;
|
|
}
|
|
|
|
c->nrd = Nrd;
|
|
c->ntd = Ntd;
|
|
t = c->nrd * sizeof *c->rdba + 255;
|
|
t += c->ntd * sizeof *c->tdba + 255;
|
|
t += (c->ntd + c->nrd) * sizeof(Block*);
|
|
c->alloc = malloc(t);
|
|
unlock(&c->alock);
|
|
if(c->alloc == nil)
|
|
error(Enomem);
|
|
|
|
c->rdba = (Rd*)ROUNDUP((uintptr)c->alloc, 256);
|
|
c->tdba = (Td*)ROUNDUP((uintptr)(c->rdba + c->nrd), 256);
|
|
c->rb = (Block**)(c->tdba + c->ntd);
|
|
c->tb = (Block**)(c->rb + c->nrd);
|
|
|
|
rxinit(c);
|
|
txinit(c);
|
|
|
|
c->reg[Ctrlext] |= Drvload; /* driver works without this */
|
|
snprint(buf, sizeof buf, "#l%dl", e->ctlrno);
|
|
kproc(buf, lproc, e);
|
|
snprint(buf, sizeof buf, "#l%dr", e->ctlrno);
|
|
kproc(buf, rproc, e);
|
|
snprint(buf, sizeof buf, "#l%dt", e->ctlrno);
|
|
kproc(buf, tproc, e);
|
|
}
|
|
|
|
static void
|
|
interrupt(Ureg*, void *v)
|
|
{
|
|
int icr, im;
|
|
Ctlr *c;
|
|
Ether *e;
|
|
|
|
e = v;
|
|
c = e->ctlr;
|
|
ilock(&c->imlock);
|
|
c->reg[Imc] = ~0;
|
|
im = c->im;
|
|
while((icr = c->reg[Icr] & c->im) != 0){
|
|
if(icr & Lsc){
|
|
im &= ~Lsc;
|
|
c->lim = icr & Lsc;
|
|
wakeup(&c->lrendez);
|
|
}
|
|
if(icr & Irx0){
|
|
im &= ~Irx0;
|
|
c->rim = icr & Irx0;
|
|
wakeup(&c->rrendez);
|
|
}
|
|
if(icr & Itx0){
|
|
im &= ~Itx0;
|
|
c->tim = icr & Itx0;
|
|
wakeup(&c->trendez);
|
|
}
|
|
}
|
|
c->reg[Ims] = c->im = im;
|
|
iunlock(&c->imlock);
|
|
}
|
|
|
|
static void
|
|
scan(void)
|
|
{
|
|
uvlong io, iomsi;
|
|
void *mem, *memmsi;
|
|
int pciregs, pcimsix;
|
|
Ctlr *c;
|
|
Pcidev *p;
|
|
|
|
p = 0;
|
|
while(p = pcimatch(p, 0x8086, 0x15c8)){ /* X553/X550-AT 10GBASE-T */
|
|
pcimsix = 4;
|
|
pciregs = 0;
|
|
if((p->mem[pciregs].bar & 1) != 0
|
|
|| (p->mem[pcimsix].bar & 1) != 0)
|
|
continue;
|
|
if(nctlr == nelem(ctlrtab)){
|
|
print("iX550: too many controllers\n");
|
|
return;
|
|
}
|
|
c = malloc(sizeof *c);
|
|
if(c == nil){
|
|
print("iX550: can't allocate memory\n");
|
|
continue;
|
|
}
|
|
io = p->mem[pciregs].bar & ~0xF;
|
|
mem = vmap(io, p->mem[pciregs].size);
|
|
if(mem == nil){
|
|
print("iX550: can't map regs %llux\n", io);
|
|
free(c);
|
|
continue;
|
|
}
|
|
iomsi = p->mem[pcimsix].bar & ~0xF;
|
|
memmsi = vmap(iomsi, p->mem[pcimsix].size);
|
|
if(memmsi == nil){
|
|
print("iX550: can't map msi-x regs %llux\n", iomsi);
|
|
vunmap(mem, p->mem[pciregs].size);
|
|
free(c);
|
|
continue;
|
|
}
|
|
pcienable(p);
|
|
c->p = p;
|
|
c->io = io;
|
|
c->reg = (u32int*)mem;
|
|
c->regmsi = (u32int*)memmsi;
|
|
c->rbsz = ROUND(Mtu, 1024);
|
|
if(reset(c)){
|
|
print("iX550: can't reset\n");
|
|
vunmap(mem, p->mem[pciregs].size);
|
|
vunmap(memmsi, p->mem[pcimsix].size);
|
|
free(c);
|
|
continue;
|
|
}
|
|
pcisetbme(p);
|
|
ctlrtab[nctlr++] = c;
|
|
}
|
|
}
|
|
|
|
static int
|
|
pnp(Ether *e)
|
|
{
|
|
static uchar zeros[Eaddrlen];
|
|
int i;
|
|
Ctlr *c = nil;
|
|
uchar *p;
|
|
|
|
if(nctlr == 0)
|
|
scan();
|
|
for(i = 0; i < nctlr; i++){
|
|
c = ctlrtab[i];
|
|
if(c == nil || c->flag & Factive)
|
|
continue;
|
|
if(e->port == 0 || e->port == c->io)
|
|
break;
|
|
}
|
|
if (i >= nctlr)
|
|
return -1;
|
|
|
|
if(memcmp(c->ra, zeros, Eaddrlen) != 0)
|
|
memmove(e->ea, c->ra, Eaddrlen);
|
|
|
|
p = e->ea;
|
|
c->reg[Ral] = p[3]<<24 | p[2]<<16 | p[1]<<8 | p[0];
|
|
c->reg[Rah] = p[5]<<8 | p[4] | 1<<31;
|
|
|
|
c->flag |= Factive;
|
|
e->ctlr = c;
|
|
e->port = (uintptr)c->reg;
|
|
e->irq = c->p->intl;
|
|
e->tbdf = c->p->tbdf;
|
|
e->mbps = 10000;
|
|
e->maxmtu = Mtu;
|
|
|
|
e->arg = e;
|
|
e->attach = attach;
|
|
e->ctl = ctl;
|
|
e->ifstat = ifstat;
|
|
e->multicast = multicast;
|
|
e->promiscuous = promiscuous;
|
|
e->shutdown = shutdown;
|
|
e->transmit = transmit;
|
|
|
|
intrenable(e->irq, interrupt, e, e->tbdf, e->name);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
etherx550link(void)
|
|
{
|
|
addethercard("iX550", pnp);
|
|
}
|