1385 lines
30 KiB
C
1385 lines
30 KiB
C
/*
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* omap3530 SoC (e.g. beagleboard) architecture-specific stuff
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*
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* errata: usb port 3 cannot operate in ulpi mode, only serial or
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* ulpi tll mode
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "../port/error.h"
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#include "io.h"
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#include "arm.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#include "../port/flashif.h"
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#include "../port/usb.h"
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#include "usbehci.h"
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#define FREQSEL(x) ((x) << 4)
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typedef struct Cm Cm;
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typedef struct Cntrl Cntrl;
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typedef struct Gen Gen;
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typedef struct Gpio Gpio;
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typedef struct L3agent L3agent;
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typedef struct L3protreg L3protreg;
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typedef struct L3regs L3regs;
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typedef struct Prm Prm;
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typedef struct Usbotg Usbotg;
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typedef struct Usbtll Usbtll;
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/* omap3 non-standard usb stuff */
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struct Usbotg {
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uchar faddr;
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uchar power;
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ushort intrtx;
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ushort intrrx;
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ushort intrtxe;
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ushort intrrxe;
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uchar intrusb;
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uchar intrusbe;
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ushort frame;
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uchar index;
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uchar testmode;
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/* indexed registers follow; ignore for now */
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uchar _pad0[0x400 - 0x10];
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ulong otgrev;
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ulong otgsyscfg;
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ulong otgsyssts;
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ulong otgifcsel; /* interface selection */
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uchar _pad1[0x414 - 0x410];
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ulong otgforcestdby;
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};
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enum {
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/* power bits */
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Hsen = 1<<5, /* high-speed enable */
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/* testmode bits */
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Forcehost = 1<<7, /* force host (vs peripheral) mode */
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Forcehs = 1<<4, /* force high-speed at reset */
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/* otgsyscfg bits */
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Midle = 1<<12, /* no standby mode */
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Sidle = 1<<3, /* no idle mode */
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// Softreset = 1<<1,
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/* otgsyssts bits, per sysstatus */
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};
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struct Usbtll {
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ulong revision; /* ro */
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uchar _pad0[0x10-0x4];
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ulong sysconfig;
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ulong sysstatus; /* ro */
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ulong irqstatus;
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ulong irqenable;
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};
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enum {
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/* sysconfig bits */
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Softreset = 1<<1,
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/* sysstatus bits */
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Resetdone = 1<<0,
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/* only in uhh->sysstatus */
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Ehci_resetdone = 1<<2,
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Ohci_resetdone = 1<<1,
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};
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/*
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* an array of these structs is preceded by error_log at 0x20, control,
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* error_clear_single, error_clear_multi. first struct is at offset 0x48.
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*/
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struct L3protreg { /* hw: an L3 protection region */
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uvlong req_info_perm;
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uvlong read_perm;
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uvlong write_perm;
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uvlong addr_match; /* ro? write this one last, then flush */
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};
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// TODO: set these permission bits (e.g., for usb)?
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enum {
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Permusbhost = 1<<9,
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Permusbotg = 1<<4,
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Permsysdma = 1<<3,
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Permmpu = 1<<1,
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};
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struct L3agent { /* hw registers */
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uchar _pad0[0x20];
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uvlong ctl;
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uvlong sts;
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uchar _pad1[0x58 - 0x30];
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uvlong errlog;
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uvlong errlogaddr;
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};
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struct L3regs {
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L3protreg *base; /* base of array */
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int upper; /* index maximum */
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char *name;
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};
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L3regs l3regs[] = {
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(L3protreg *)(PHYSL3GPMCPM+0x48), 7, "gpmc", /* known to be first */
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(L3protreg *)(PHYSL3PMRT+0x48), 1, "rt", /* l3 config */
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(L3protreg *)(PHYSL3OCTRAM+0x48), 7, "ocm ram",
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(L3protreg *)(PHYSL3OCTROM+0x48), 1, "ocm rom",
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(L3protreg *)(PHYSL3MAD2D+0x48), 7, "mad2d", /* die-to-die */
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(L3protreg *)(PHYSL3IVA+0x48), 3, "iva2.2", /* a/v */
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};
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/*
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* PRM_CLKSEL (0x48306d40) low 3 bits are system clock speed, assuming
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* units of MHz: 0 = 12, 1 = 13, 2 = 19.2, 3 = 26, 4 = 38.4, 5 = 16.8
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*/
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struct Cm { /* clock management */
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ulong fclken; /* ``functional'' clock enable */
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ulong fclken2;
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ulong fclken3;
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uchar _pad0[0x10 - 0xc];
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ulong iclken; /* ``interface'' clock enable */
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ulong iclken2;
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ulong iclken3;
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uchar _pad1[0x20 - 0x1c];
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ulong idlest; /* idle status */
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ulong idlest2;
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ulong idlest3;
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uchar _pad2[0x30 - 0x2c];
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ulong autoidle;
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ulong autoidle2;
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ulong autoidle3;
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uchar _pad3[0x40 - 0x3c];
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union {
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ulong clksel[5];
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struct unused {
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ulong sleepdep;
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ulong clkstctrl;
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ulong clkstst;
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};
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uchar _pad4[0x70 - 0x40];
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};
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ulong clkoutctrl;
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};
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struct Prm { /* power & reset management */
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uchar _pad[0x50];
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ulong rstctrl;
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};
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struct Gpio {
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ulong _pad0[4];
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ulong sysconfig;
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ulong sysstatus;
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ulong irqsts1; /* for mpu */
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ulong irqen1;
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ulong wkupen;
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ulong _pad1;
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ulong irqsts2; /* for iva */
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ulong irqen2;
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ulong ctrl;
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ulong oe;
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ulong datain;
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ulong dataout;
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ulong lvldet0;
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ulong lvldet1;
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ulong risingdet;
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ulong fallingdet;
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/* rest are uninteresting */
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ulong deben; /* debouncing enable */
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ulong debtime;
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ulong _pad2[2];
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ulong clrirqen1;
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ulong setirqen1;
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ulong _pad3[2];
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ulong clrirqen2;
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ulong setirqen2;
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ulong _pad4[2];
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ulong clrwkupen;
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ulong setwkupen;
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ulong _pad5[2];
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ulong clrdataout;
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ulong setdataout;
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};
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enum {
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/* clock enable & idle status bits */
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Wkusimocp = 1 << 9, /* SIM card: uses 120MHz clock */
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Wkwdt2 = 1 << 5, /* wdt2 clock enable bit for wakeup */
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Wkgpio1 = 1 << 3, /* gpio1 " */
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Wkgpt1 = 1 << 0, /* gpt1 " */
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Dssl3l4 = 1 << 0, /* dss l3, l4 i clks */
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Dsstv = 1 << 2, /* dss tv f clock */
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Dss2 = 1 << 1, /* dss clock 2 */
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Dss1 = 1 << 0, /* dss clock 1 */
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Pergpio6 = 1 << 17,
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Pergpio5 = 1 << 16,
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Pergpio4 = 1 << 15,
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Pergpio3 = 1 << 14,
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Pergpio2 = 1 << 13,
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Perwdt3 = 1 << 12, /* wdt3 clock enable bit for periphs */
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Peruart3 = 1 << 11, /* console uart */
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Pergpt9 = 1 << 10,
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Pergpt8 = 1 << 9,
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Pergpt7 = 1 << 8,
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Pergpt6 = 1 << 7,
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Pergpt5 = 1 << 6,
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Pergpt4 = 1 << 5,
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Pergpt3 = 1 << 4,
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Pergpt2 = 1 << 3, /* gpt2 clock enable bit for periphs */
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Perenable = Pergpio6 | Pergpio5 | Perwdt3 | Pergpt2 | Peruart3,
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Usbhost2 = 1 << 1, /* 120MHz clock enable */
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Usbhost1 = 1 << 0, /* 48MHz clock enable */
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Usbhost = Usbhost1, /* iclock enable */
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Usbhostidle = 1 << 1,
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Usbhoststdby = 1 << 0,
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Coreusbhsotg = 1 << 4, /* usb hs otg enable bit */
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Core3usbtll = 1 << 2, /* usb tll enable bit */
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/* core->idlest bits */
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Coreusbhsotgidle = 1 << 5,
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Coreusbhsotgstdby= 1 << 4,
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Dplllock = 7,
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/* mpu->idlest2 bits */
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Dplllocked = 1,
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Dpllbypassed = 0,
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/* wkup->idlest bits */
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Gpio1idle = 1 << 3,
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/* dss->idlest bits */
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Dssidle = 1 << 1,
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Gpio1vidmagic = 1<<24 | 1<<8 | 1<<5, /* gpio 1 pins for video */
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};
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enum {
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Rstgs = 1 << 1, /* global sw. reset */
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/* fp control regs. most are read-only */
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Fpsid = 0,
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Fpscr, /* rw */
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Mvfr1 = 6,
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Mvfr0,
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Fpexc, /* rw */
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};
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/* see ether9221.c for explanation */
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enum {
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Ethergpio = 176,
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Etherchanbit = 1 << (Ethergpio % 32),
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};
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/*
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* these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
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* the Cortex-A8 L2 cache (A=3, L=6).
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* A = log2(# of ways), L = log2(bytes per cache line).
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* see armv7 arch ref p. 1403.
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*
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* #define L1WAYSH 30
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* #define L1SETSH 6
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* #define L2WAYSH 29
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* #define L2SETSH 6
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*/
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enum {
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/*
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* cache capabilities. write-back vs write-through is controlled
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* by the Buffered bit in PTEs.
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*/
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Cawt = 1 << 31,
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Cawb = 1 << 30,
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Cara = 1 << 29,
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Cawa = 1 << 28,
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};
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struct Gen {
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ulong padconf_off;
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ulong devconf0;
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uchar _pad0[0x68 - 8];
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ulong devconf1;
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};
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struct Cntrl {
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ulong _pad0;
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ulong id;
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ulong _pad1;
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ulong skuid;
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};
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static char *
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devidstr(ulong)
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{
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return "ARM Cortex-A8";
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}
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void
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archomaplink(void)
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{
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}
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int
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ispow2(uvlong ul)
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{
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/* see Hacker's Delight if this isn't obvious */
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return (ul & (ul - 1)) == 0;
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}
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/*
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* return exponent of smallest power of 2 ≥ n
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*/
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int
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log2(ulong n)
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{
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int i;
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i = 31 - clz(n);
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if (n == 0 || !ispow2(n))
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i++;
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return i;
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}
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void
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archconfinit(void)
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{
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char *p;
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ulong mhz;
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assert(m != nil);
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m->cpuhz = 500 * Mhz; /* beagle speed */
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p = getconf("*cpumhz");
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if (p) {
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mhz = atoi(p) * Mhz;
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if (mhz >= 100*Mhz && mhz <= 3000UL*Mhz)
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m->cpuhz = mhz;
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}
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m->delayloop = m->cpuhz/2000; /* initial estimate */
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}
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static void
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prperm(uvlong perm)
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{
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if (perm == MASK(16))
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print("all");
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else
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print("%#llux", perm);
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}
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static void
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prl3region(L3protreg *pr, int r)
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{
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int level, size, addrspace;
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uvlong am, base;
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if (r == 0)
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am = 0;
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else
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am = pr->addr_match;
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size = (am >> 3) & MASK(5);
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if (r > 0 && size == 0) /* disabled? */
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return;
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print(" %d: perms req ", r);
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prperm(pr->req_info_perm);
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if (pr->read_perm == pr->write_perm && pr->read_perm == MASK(16))
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print(" rw all");
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else {
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print(" read ");
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prperm(pr->read_perm);
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print(" write ");
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prperm(pr->write_perm);
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}
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if (r == 0)
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print(", all addrs level 0");
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else {
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size = 1 << size; /* 2^size */
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level = (am >> 9) & 1;
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if (r == 1)
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level = 3;
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else
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level++;
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addrspace = am & 7;
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base = am & ~MASK(10);
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print(", base %#llux size %dKB level %d addrspace %d",
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base, size, level, addrspace);
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}
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print("\n");
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delay(100);
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}
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/*
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* dump the l3 interconnect firewall settings by protection region.
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* mpu, sys dma and both usbs (0x21a) should be set in all read & write
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* permission registers.
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*/
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static void
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dumpl3pr(void)
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{
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int r;
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L3regs *reg;
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L3protreg *pr;
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for (reg = l3regs; reg < l3regs + nelem(l3regs); reg++) {
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print("%#p (%s) enabled l3 regions:\n", reg->base, reg->name);
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for (r = 0; r <= reg->upper; r++)
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prl3region(reg->base + r, r);
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}
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if (0) { // TODO
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/* touch up gpmc perms */
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reg = l3regs; /* first entry is gpmc */
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for (r = 0; r <= reg->upper; r++) {
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pr = reg->base + r;
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// TODO
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}
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print("%#p (%s) modified l3 regions:\n", reg->base, reg->name);
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for (r = 0; r <= reg->upper; r++)
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prl3region(reg->base + r, r);
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}
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}
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static void
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p16(uchar *p, ulong v)
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{
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*p++ = v>>8;
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*p = v;
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}
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static void
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p32(uchar *p, ulong v)
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{
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*p++ = v>>24;
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*p++ = v>>16;
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*p++ = v>>8;
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*p = v;
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}
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int
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archether(unsigned ctlrno, Ether *ether)
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{
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switch(ctlrno) {
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case 0:
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/* there's no built-in ether on the beagle but igepv2 has 1 */
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ether->type = "9221";
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ether->ctlrno = ctlrno;
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ether->irq = 34;
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ether->nopt = 0;
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ether->mbps = 100;
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return 1;
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}
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return -1;
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}
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/*
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* turn on all the necessary clocks on the SoC.
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*
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* a ``functional'' clock drives a device; an ``interface'' clock drives
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* its communication with the rest of the system. so the interface
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* clock must be enabled to reach the device's registers.
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*
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* dplls: 1 mpu, 2 iva2, 3 core, 4 per, 5 per2.
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*/
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static void
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configmpu(void)
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{
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ulong clk, mhz, nmhz, maxmhz;
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Cm *mpu = (Cm *)PHYSSCMMPU;
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Cntrl *id = (Cntrl *)PHYSCNTRL;
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if ((id->skuid & MASK(4)) == 8)
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maxmhz = 720;
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else
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maxmhz = 600;
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iprint("cpu capable of %ldMHz operation", maxmhz);
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clk = mpu->clksel[0];
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mhz = (clk >> 8) & MASK(11); /* configured speed */
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// iprint("\tfclk src %ld; dpll1 mult %ld (MHz) div %ld",
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// (clk >> 19) & MASK(3), mhz, clk & MASK(7));
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iprint("; at %ldMHz", mhz);
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nmhz = m->cpuhz / Mhz; /* nominal speed */
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if (mhz == nmhz) {
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iprint("\n");
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return;
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}
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mhz = nmhz;
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if (mhz > maxmhz) {
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mhz = maxmhz;
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iprint("; limiting operation to %ldMHz", mhz);
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}
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/* disable dpll1 lock mode; put into low-power bypass mode */
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mpu->fclken2 = mpu->fclken2 & ~MASK(3) | 5;
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coherence();
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while (mpu->idlest2 != Dpllbypassed)
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;
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/*
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* there's a dance to change processor speed,
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* prescribed in spruf98d §4.7.6.9.
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*/
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/* just change multiplier; leave divider alone at 12 (meaning 13?) */
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mpu->clksel[0] = clk & ~(MASK(11) << 8) | mhz << 8;
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coherence();
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|
|
|
/* set output divider (M2) in clksel[1]: leave at 1 */
|
|
|
|
/*
|
|
* u-boot calls us with just freqsel 3 (~1MHz) & dpll1 lock mode.
|
|
*/
|
|
/* set FREQSEL */
|
|
mpu->fclken2 = mpu->fclken2 & ~FREQSEL(MASK(4)) | FREQSEL(3);
|
|
coherence();
|
|
|
|
/* set ramp-up delay to `fast' */
|
|
mpu->fclken2 = mpu->fclken2 & ~(MASK(2) << 8) | 3 << 8;
|
|
coherence();
|
|
|
|
/* set auto-recalibration (off) */
|
|
mpu->fclken2 &= ~(1 << 3);
|
|
coherence();
|
|
|
|
/* disable auto-idle: ? */
|
|
/* unmask clock intr: later */
|
|
|
|
/* enable dpll lock mode */
|
|
mpu->fclken2 |= Dplllock;
|
|
coherence();
|
|
while (mpu->idlest2 != Dplllocked)
|
|
;
|
|
delay(200); /* allow time for speed to ramp up */
|
|
|
|
if (((mpu->clksel[0] >> 8) & MASK(11)) != mhz)
|
|
panic("mpu clock speed change didn't stick");
|
|
iprint("; now at %ldMHz\n", mhz);
|
|
}
|
|
|
|
static void
|
|
configpll(void)
|
|
{
|
|
int i;
|
|
Cm *pll = (Cm *)PHYSSCMPLL;
|
|
|
|
pll->clkoutctrl |= 1 << 7; /* enable sys_clkout2 */
|
|
coherence();
|
|
delay(10);
|
|
|
|
/*
|
|
* u-boot calls us with just freqsel 3 (~1MHz) & lock mode
|
|
* for both dplls (3 & 4). ensure that.
|
|
*/
|
|
if ((pll->idlest & 3) != 3) {
|
|
/* put dpll[34] into low-power bypass mode */
|
|
pll->fclken = pll->fclken & ~(MASK(3) << 16 | MASK(3)) |
|
|
1 << 16 | 5;
|
|
coherence();
|
|
while (pll->idlest & 3) /* wait for both to bypass or stop */
|
|
;
|
|
|
|
pll->fclken = (FREQSEL(3) | Dplllock) << 16 |
|
|
FREQSEL(3) | Dplllock;
|
|
coherence();
|
|
while ((pll->idlest & 3) != 3) /* wait for both to lock */
|
|
;
|
|
}
|
|
|
|
/*
|
|
* u-boot calls us with just freqsel 1 (default but undefined)
|
|
* & stop mode for dpll5. try to lock it at 120MHz.
|
|
*/
|
|
if (!(pll->idlest2 & Dplllocked)) {
|
|
/* force dpll5 into low-power bypass mode */
|
|
pll->fclken2 = 3 << 8 | FREQSEL(1) | 1;
|
|
coherence();
|
|
for (i = 0; pll->idlest2 & Dplllocked && i < 20; i++)
|
|
delay(50);
|
|
if (i >= 20)
|
|
iprint(" [dpll5 failed to stop]");
|
|
|
|
/*
|
|
* CORE_CLK is 26MHz.
|
|
*/
|
|
pll->clksel[4-1] = 120 << 8 | 12; /* M=120, N=12+1 */
|
|
/* M2 divisor: 120MHz clock is exactly the DPLL5 clock */
|
|
pll->clksel[5-1] = 1;
|
|
coherence();
|
|
|
|
pll->fclken2 = 3 << 8 | FREQSEL(1) | Dplllock; /* def. freq */
|
|
coherence();
|
|
|
|
for (i = 0; !(pll->idlest2 & Dplllocked) && i < 20; i++)
|
|
delay(50);
|
|
if (i >= 20)
|
|
iprint(" [dpll5 failed to lock]");
|
|
}
|
|
if (!(pll->idlest2 & (1<<1)))
|
|
iprint(" [no 120MHz clock]");
|
|
if (!(pll->idlest2 & (1<<3)))
|
|
iprint(" [no dpll5 120MHz clock output]");
|
|
}
|
|
|
|
static void
|
|
configper(void)
|
|
{
|
|
Cm *per = (Cm *)PHYSSCMPER;
|
|
|
|
per->clksel[0] &= ~MASK(8); /* select 32kHz clock for GPTIMER2-9 */
|
|
|
|
per->iclken |= Perenable;
|
|
coherence();
|
|
per->fclken |= Perenable;
|
|
coherence();
|
|
while (per->idlest & Perenable)
|
|
;
|
|
|
|
per->autoidle = 0;
|
|
coherence();
|
|
}
|
|
|
|
static void
|
|
configwkup(void)
|
|
{
|
|
Cm *wkup = (Cm *)PHYSSCMWKUP;
|
|
|
|
/* select 32kHz clock (not system clock) for GPTIMER1 */
|
|
wkup->clksel[0] &= ~1;
|
|
|
|
wkup->iclken |= Wkusimocp | Wkwdt2 | Wkgpt1;
|
|
coherence();
|
|
wkup->fclken |= Wkusimocp | Wkwdt2 | Wkgpt1;
|
|
coherence();
|
|
while (wkup->idlest & (Wkusimocp | Wkwdt2 | Wkgpt1))
|
|
;
|
|
}
|
|
|
|
static void
|
|
configusb(void)
|
|
{
|
|
int i;
|
|
Cm *usb = (Cm *)PHYSSCMUSB;
|
|
|
|
/*
|
|
* make the usb registers accessible without address faults,
|
|
* notably uhh, ochi & ehci. tll seems to be separate & otg is okay.
|
|
*/
|
|
usb->iclken |= Usbhost;
|
|
coherence();
|
|
usb->fclken |= Usbhost1 | Usbhost2; /* includes 120MHz clock */
|
|
coherence();
|
|
for (i = 0; usb->idlest & Usbhostidle && i < 20; i++)
|
|
delay(50);
|
|
if (i >= 20)
|
|
iprint(" [usb inaccessible]");
|
|
}
|
|
|
|
static void
|
|
configcore(void)
|
|
{
|
|
Cm *core = (Cm *)PHYSSCMCORE;
|
|
|
|
/*
|
|
* make the usb tll registers accessible.
|
|
*/
|
|
core->iclken |= Coreusbhsotg;
|
|
core->iclken3 |= Core3usbtll;
|
|
coherence();
|
|
core->fclken3 |= Core3usbtll;
|
|
coherence();
|
|
delay(100);
|
|
while (core->idlest & Coreusbhsotgidle)
|
|
;
|
|
if (core->idlest3 & Core3usbtll)
|
|
iprint(" [no usb tll]");
|
|
}
|
|
|
|
static void
|
|
configclks(void)
|
|
{
|
|
int s;
|
|
Gen *gen = (Gen *)PHYSSCMPCONF;
|
|
|
|
delay(20);
|
|
s = splhi();
|
|
configmpu(); /* sets cpu clock rate, turns on dplls 1 & 2 */
|
|
|
|
/*
|
|
* the main goal is to get enough clocks running, in the right order,
|
|
* so that usb has all the necessary clock signals.
|
|
*/
|
|
iprint("clocks:");
|
|
iprint(" usb");
|
|
configusb(); /* starts usb clocks & 120MHz clock */
|
|
iprint(", pll");
|
|
configpll(); /* starts dplls 3, 4 & 5 & 120MHz clock */
|
|
iprint(", wakeup");
|
|
configwkup(); /* starts timer clocks and usim clock */
|
|
iprint(", per");
|
|
configper(); /* starts timer & gpio (ether) clocks */
|
|
iprint(", core");
|
|
configcore(); /* starts usb tll */
|
|
iprint("\n");
|
|
|
|
gen->devconf0 |= 1 << 1 | 1 << 0; /* dmareq[01] edge sensitive */
|
|
/* make dmareq[2-6] edge sensitive */
|
|
gen->devconf1 |= 1 << 23 | 1 << 22 | 1 << 21 | 1 << 8 | 1 << 7;
|
|
coherence();
|
|
splx(s);
|
|
delay(20);
|
|
}
|
|
|
|
static void
|
|
resetwait(ulong *reg)
|
|
{
|
|
long bound;
|
|
|
|
for (bound = 400*Mhz; !(*reg & Resetdone) && bound > 0; bound--)
|
|
;
|
|
if (bound <= 0)
|
|
iprint("archomap: Resetdone didn't come ready\n");
|
|
}
|
|
|
|
/*
|
|
* gpio irq 1 goes to the mpu intr ctlr; irq 2 goes to the iva's.
|
|
* this stuff is magic and without it, we won't get irq 34 interrupts
|
|
* from the 9221 ethernet controller.
|
|
*/
|
|
static void
|
|
configgpio(void)
|
|
{
|
|
Gpio *gpio = (Gpio *)PHYSGPIO6;
|
|
|
|
gpio->sysconfig = Softreset;
|
|
coherence();
|
|
resetwait(&gpio->sysstatus);
|
|
|
|
gpio->ctrl = 1<<1 | 0; /* enable this gpio module, gating ratio 1 */
|
|
gpio->oe |= Etherchanbit; /* cfg ether pin as input */
|
|
coherence();
|
|
|
|
gpio->irqen1 = Etherchanbit; /* channel # == pin # */
|
|
gpio->irqen2 = 0;
|
|
|
|
gpio->lvldet0 = Etherchanbit; /* enable irq ass'n on low det'n */
|
|
gpio->lvldet1 = 0; /* disable irq ass'n on high det'n */
|
|
gpio->risingdet = 0; /* enable irq rising edge det'n */
|
|
gpio->fallingdet = 0; /* disable irq falling edge det'n */
|
|
|
|
gpio->wkupen = 0;
|
|
|
|
gpio->deben = 0; /* no de-bouncing */
|
|
gpio->debtime = 0;
|
|
coherence();
|
|
|
|
gpio->irqsts1 = ~0; /* dismiss all outstanding intrs */
|
|
gpio->irqsts2 = ~0;
|
|
coherence();
|
|
}
|
|
|
|
void
|
|
configscreengpio(void)
|
|
{
|
|
Cm *wkup = (Cm *)PHYSSCMWKUP;
|
|
Gpio *gpio = (Gpio *)PHYSGPIO1;
|
|
|
|
/* no clocksel needed */
|
|
wkup->iclken |= Wkgpio1;
|
|
coherence();
|
|
wkup->fclken |= Wkgpio1; /* turn gpio clock on */
|
|
coherence();
|
|
// wkup->autoidle |= Wkgpio1; /* set gpio clock on auto */
|
|
wkup->autoidle = 0;
|
|
coherence();
|
|
while (wkup->idlest & Gpio1idle)
|
|
;
|
|
|
|
/*
|
|
* 0 bits in oe are output signals.
|
|
* enable output for gpio 1 (first gpio) video magic pins.
|
|
*/
|
|
gpio->oe &= ~Gpio1vidmagic;
|
|
coherence();
|
|
gpio->dataout |= Gpio1vidmagic; /* set output pins to 1 */
|
|
coherence();
|
|
delay(50);
|
|
}
|
|
|
|
void
|
|
screenclockson(void)
|
|
{
|
|
Cm *dss = (Cm *)PHYSSCMDSS;
|
|
|
|
dss->iclken |= Dssl3l4;
|
|
coherence();
|
|
dss->fclken = Dsstv | Dss2 | Dss1;
|
|
coherence();
|
|
/* tv fclk is dpll4 clk; dpll4 m4 divide factor for dss1 fclk is 2 */
|
|
dss->clksel[0] = 1<<12 | 2;
|
|
coherence();
|
|
delay(50);
|
|
while (dss->idlest & Dssidle)
|
|
;
|
|
}
|
|
|
|
void
|
|
gpioirqclr(void)
|
|
{
|
|
Gpio *gpio = (Gpio *)PHYSGPIO6;
|
|
|
|
gpio->irqsts1 = gpio->irqsts1;
|
|
coherence();
|
|
}
|
|
|
|
static char *
|
|
l1iptype(uint type)
|
|
{
|
|
static char *types[] = {
|
|
"reserved",
|
|
"asid-tagged VIVT",
|
|
"VIPT",
|
|
"PIPT",
|
|
};
|
|
|
|
if (type >= nelem(types) || types[type] == nil)
|
|
return "GOK";
|
|
return types[type];
|
|
}
|
|
|
|
void
|
|
cacheinfo(int level, Memcache *cp)
|
|
{
|
|
ulong setsways;
|
|
|
|
/* select cache level */
|
|
cpwrsc(CpIDcssel, CpID, CpIDid, 0, (level - 1) << 1);
|
|
|
|
setsways = cprdsc(CpIDcsize, CpID, CpIDid, 0);
|
|
cp->l1ip = cprdsc(0, CpID, CpIDidct, CpIDct);
|
|
cp->level = level;
|
|
cp->nways = ((setsways >> 3) & MASK(10)) + 1;
|
|
cp->nsets = ((setsways >> 13) & MASK(15)) + 1;
|
|
cp->log2linelen = (setsways & MASK(2)) + 2 + 2;
|
|
cp->linelen = 1 << cp->log2linelen;
|
|
cp->setsways = setsways;
|
|
|
|
cp->setsh = cp->log2linelen;
|
|
cp->waysh = 32 - log2(cp->nways);
|
|
}
|
|
|
|
static void
|
|
prcachecfg(void)
|
|
{
|
|
int cache;
|
|
Memcache mc;
|
|
|
|
for (cache = 1; cache <= 2; cache++) {
|
|
cacheinfo(cache, &mc);
|
|
iprint("l%d: %d ways %d sets %d bytes/line",
|
|
mc.level, mc.nways, mc.nsets, mc.linelen);
|
|
if (mc.linelen != CACHELINESZ)
|
|
iprint(" *should* be %d", CACHELINESZ);
|
|
if (mc.setsways & Cawt)
|
|
iprint("; can WT");
|
|
if (mc.setsways & Cawb)
|
|
iprint("; can WB");
|
|
#ifdef COMPULSIVE /* both caches can do this */
|
|
if (mc.setsways & Cara)
|
|
iprint("; can read-allocate");
|
|
#endif
|
|
if (mc.setsways & Cawa)
|
|
iprint("; can write-allocate");
|
|
if (cache == 1)
|
|
iprint("; l1 I policy %s",
|
|
l1iptype((mc.l1ip >> 14) & MASK(2)));
|
|
iprint("\n");
|
|
}
|
|
}
|
|
|
|
static char *
|
|
subarch(int impl, uint sa)
|
|
{
|
|
static char *armarchs[] = {
|
|
"VFPv1 (pre-armv7)",
|
|
"VFPv2 (pre-armv7)",
|
|
"VFPv3+ with common VFP subarch v2",
|
|
"VFPv3+ with null subarch",
|
|
"VFPv3+ with common VFP subarch v3",
|
|
};
|
|
|
|
if (impl != 'A' || sa >= nelem(armarchs))
|
|
return "GOK";
|
|
else
|
|
return armarchs[sa];
|
|
}
|
|
|
|
/*
|
|
* padconf bits in a short, 2 per long register
|
|
* 15 wakeupevent
|
|
* 14 wakeupenable
|
|
* 13 offpulltypeselect
|
|
* 12 offpulludenable
|
|
* 11 offoutvalue
|
|
* 10 offoutenable
|
|
* 9 offenable
|
|
* 8 inputenable
|
|
* 4 pulltypeselect
|
|
* 3 pulludenable
|
|
* 2-0 muxmode
|
|
*
|
|
* see table 7-5 in §7.4.4.3 of spruf98d
|
|
*/
|
|
|
|
enum {
|
|
/* pad config register bits */
|
|
Inena = 1 << 8, /* input enable */
|
|
Indis = 0 << 8, /* input disable */
|
|
Ptup = 1 << 4, /* pull type up */
|
|
Ptdown = 0 << 4, /* pull type down */
|
|
Ptena = 1 << 3, /* pull type selection is active */
|
|
Ptdis = 0 << 3, /* pull type selection is inactive */
|
|
Muxmode = MASK(3),
|
|
|
|
/* pad config registers relevant to flash */
|
|
GpmcA1 = 0x4800207A,
|
|
GpmcA2 = 0x4800207C,
|
|
GpmcA3 = 0x4800207E,
|
|
GpmcA4 = 0x48002080,
|
|
GpmcA5 = 0x48002082,
|
|
GpmcA6 = 0x48002084,
|
|
GpmcA7 = 0x48002086,
|
|
GpmcA8 = 0x48002088,
|
|
GpmcA9 = 0x4800208A,
|
|
GpmcA10 = 0x4800208C,
|
|
GpmcD0 = 0x4800208E,
|
|
GpmcD1 = 0x48002090,
|
|
GpmcD2 = 0x48002092,
|
|
GpmcD3 = 0x48002094,
|
|
GpmcD4 = 0x48002096,
|
|
GpmcD5 = 0x48002098,
|
|
GpmcD6 = 0x4800209A,
|
|
GpmcD7 = 0x4800209C,
|
|
GpmcD8 = 0x4800209E,
|
|
GpmcD9 = 0x480020A0,
|
|
GpmcD10 = 0x480020A2,
|
|
GpmcD11 = 0x480020A4,
|
|
GpmcD12 = 0x480020A6,
|
|
GpmcD13 = 0x480020A8,
|
|
GpmcD14 = 0x480020AA,
|
|
GpmcD15 = 0x480020AC,
|
|
GpmcNCS0 = 0x480020AE,
|
|
GpmcNCS1 = 0x480020B0,
|
|
GpmcNCS2 = 0x480020B2,
|
|
GpmcNCS3 = 0x480020B4,
|
|
GpmcNCS4 = 0x480020B6,
|
|
GpmcNCS5 = 0x480020B8,
|
|
GpmcNCS6 = 0x480020BA,
|
|
GpmcNCS7 = 0x480020BC,
|
|
GpmcCLK = 0x480020BE,
|
|
GpmcNADV_ALE = 0x480020C0,
|
|
GpmcNOE = 0x480020C2,
|
|
GpmcNWE = 0x480020C4,
|
|
GpmcNBE0_CLE = 0x480020C6,
|
|
GpmcNBE1 = 0x480020C8,
|
|
GpmcNWP = 0x480020CA,
|
|
GpmcWAIT0 = 0x480020CC,
|
|
GpmcWAIT1 = 0x480020CE,
|
|
GpmcWAIT2 = 0x480020D0,
|
|
GpmcWAIT3 = 0x480020D2,
|
|
};
|
|
|
|
/* set SCM pad config mux mode */
|
|
void
|
|
setmuxmode(ulong addr, int shorts, int mode)
|
|
{
|
|
int omode;
|
|
ushort *ptr;
|
|
|
|
mode &= Muxmode;
|
|
for (ptr = (ushort *)addr; shorts-- > 0; ptr++) {
|
|
omode = *ptr & Muxmode;
|
|
if (omode != mode)
|
|
*ptr = *ptr & ~Muxmode | mode;
|
|
}
|
|
coherence();
|
|
}
|
|
|
|
static void
|
|
setpadmodes(void)
|
|
{
|
|
int off;
|
|
|
|
/* set scm pad modes for usb; hasn't made any difference yet */
|
|
setmuxmode(0x48002166, 7, 5); /* hsusb3_tll* in mode 5; is mode 4 */
|
|
setmuxmode(0x48002180, 1, 5); /* hsusb3_tll_clk; is mode 4 */
|
|
setmuxmode(0x48002184, 4, 5); /* hsusb3_tll_data?; is mode 1 */
|
|
setmuxmode(0x480021a2, 12, 0); /* hsusb0 (console) in mode 0 */
|
|
setmuxmode(0x480021d4, 6, 2); /* hsusb2_tll* (ehci port 2) in mode 2 */
|
|
/* mode 3 is hsusb2_data* */
|
|
setmuxmode(0x480025d8, 18, 6); /* hsusb[12]_tll*; mode 3 is */
|
|
/* hsusb1_data*, hsusb2* */
|
|
|
|
setmuxmode(0x480020e4, 2, 5); /* uart3_rx_* in mode 5 */
|
|
setmuxmode(0x4800219a, 4, 0); /* uart3_* in mode 0 */
|
|
/* uart3_* in mode 2; TODO: conflicts with hsusb0 */
|
|
setmuxmode(0x480021aa, 4, 2);
|
|
setmuxmode(0x48002240, 2, 3); /* uart3_* in mode 3 */
|
|
|
|
/*
|
|
* igep/gumstix only: mode 4 of 21d2 is gpio_176 (smsc9221 ether irq).
|
|
* see ether9221.c for more.
|
|
*/
|
|
*(ushort *)0x480021d2 = Inena | Ptup | Ptena | 4;
|
|
|
|
/* magic from u-boot for flash */
|
|
*(ushort *)GpmcA1 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA2 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA3 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA4 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA5 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA6 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA7 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA8 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA9 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcA10 = Indis | Ptup | Ptena | 0;
|
|
|
|
*(ushort *)GpmcD0 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD1 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD2 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD3 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD4 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD5 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD6 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD7 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD8 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD9 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD10 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD11 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD12 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD13 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD14 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcD15 = Inena | Ptup | Ptena | 0;
|
|
|
|
*(ushort *)GpmcNCS0 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcNCS1 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcNCS2 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcNCS3 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcNCS4 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcNCS5 = Indis | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcNCS6 = Indis | Ptup | Ptena | 0;
|
|
|
|
*(ushort *)GpmcNOE = Indis | Ptdown | Ptdis | 0;
|
|
*(ushort *)GpmcNWE = Indis | Ptdown | Ptdis | 0;
|
|
|
|
*(ushort *)GpmcWAIT2 = Inena | Ptup | Ptena | 4; /* GPIO_64 -ETH_NRESET */
|
|
*(ushort *)GpmcNCS7 = Inena | Ptup | Ptena | 1; /* SYS_nDMA_REQ3 */
|
|
|
|
*(ushort *)GpmcCLK = Indis | Ptdown | Ptdis | 0;
|
|
|
|
*(ushort *)GpmcNBE1 = Inena | Ptdown | Ptdis | 0;
|
|
|
|
*(ushort *)GpmcNADV_ALE = Indis | Ptdown | Ptdis | 0;
|
|
*(ushort *)GpmcNBE0_CLE = Indis | Ptdown | Ptdis | 0;
|
|
|
|
*(ushort *)GpmcNWP = Inena | Ptdown | Ptdis | 0;
|
|
|
|
*(ushort *)GpmcWAIT0 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcWAIT1 = Inena | Ptup | Ptena | 0;
|
|
*(ushort *)GpmcWAIT3 = Inena | Ptup | Ptena | 0;
|
|
|
|
/*
|
|
* magic from u-boot: set 0xe00 bits in gpmc_(nwe|noe|nadv_ale)
|
|
* to enable `off' mode for each.
|
|
*/
|
|
for (off = 0xc0; off <= 0xc4; off += sizeof(short))
|
|
*((ushort *)(PHYSSCM + off)) |= 0xe00;
|
|
coherence();
|
|
}
|
|
|
|
static char *
|
|
implement(uchar impl)
|
|
{
|
|
if (impl == 'A')
|
|
return "arm";
|
|
else
|
|
return "unknown";
|
|
}
|
|
|
|
static void
|
|
fpon(void)
|
|
{
|
|
int gotfp, impl;
|
|
ulong acc, scr;
|
|
|
|
gotfp = 1 << CpFP | 1 << CpDFP;
|
|
cpwrsc(0, CpCONTROL, 0, CpCPaccess, MASK(28));
|
|
acc = cprdsc(0, CpCONTROL, 0, CpCPaccess);
|
|
if ((acc & (MASK(2) << (2*CpFP))) == 0) {
|
|
gotfp &= ~(1 << CpFP);
|
|
print("fpon: no single FP coprocessor\n");
|
|
}
|
|
if ((acc & (MASK(2) << (2*CpDFP))) == 0) {
|
|
gotfp &= ~(1 << CpDFP);
|
|
print("fpon: no double FP coprocessor\n");
|
|
}
|
|
if (!gotfp) {
|
|
print("fpon: no FP coprocessors\n");
|
|
return;
|
|
}
|
|
|
|
/* enable fp. must be first operation on the FPUs. */
|
|
fpwr(Fpexc, fprd(Fpexc) | 1 << 30);
|
|
|
|
scr = fprd(Fpsid);
|
|
impl = scr >> 24;
|
|
print("fp: %s arch %s", implement(impl),
|
|
subarch(impl, (scr >> 16) & MASK(7)));
|
|
|
|
scr = fprd(Fpscr);
|
|
// TODO configure Fpscr further
|
|
scr |= 1 << 9; /* div-by-0 exception */
|
|
scr &= ~(MASK(2) << 20 | MASK(3) << 16); /* all ops are scalar */
|
|
fpwr(Fpscr, scr);
|
|
print("\n");
|
|
/* we should now be able to execute VFP-style FP instr'ns natively */
|
|
}
|
|
|
|
static void
|
|
resetusb(void)
|
|
{
|
|
int bound;
|
|
Uhh *uhh;
|
|
Usbotg *otg;
|
|
Usbtll *tll;
|
|
|
|
iprint("resetting usb: otg...");
|
|
otg = (Usbotg *)PHYSUSBOTG;
|
|
otg->otgsyscfg = Softreset; /* see omap35x errata 3.1.1.144 */
|
|
coherence();
|
|
resetwait(&otg->otgsyssts);
|
|
otg->otgsyscfg |= Sidle | Midle;
|
|
coherence();
|
|
|
|
iprint("uhh...");
|
|
uhh = (Uhh *)PHYSUHH;
|
|
uhh->sysconfig |= Softreset;
|
|
coherence();
|
|
resetwait(&uhh->sysstatus);
|
|
for (bound = 400*Mhz; !(uhh->sysstatus & Resetdone) && bound > 0;
|
|
bound--)
|
|
;
|
|
uhh->sysconfig |= Sidle | Midle;
|
|
|
|
/*
|
|
* using the TLL seems to be an optimisation when talking
|
|
* to another identical SoC, thus not very useful, so
|
|
* force PHY (ULPI) mode.
|
|
*/
|
|
/* this bit is normally off when we get here */
|
|
uhh->hostconfig &= ~P1ulpi_bypass;
|
|
coherence();
|
|
if (uhh->hostconfig & P1ulpi_bypass)
|
|
iprint("utmi (tll) mode..."); /* via tll */
|
|
else
|
|
/* external transceiver (phy), no tll */
|
|
iprint("ulpi (phy) mode...");
|
|
|
|
tll = (Usbtll *)PHYSUSBTLL;
|
|
if (probeaddr(PHYSUSBTLL) >= 0) {
|
|
iprint("tll...");
|
|
tll->sysconfig |= Softreset;
|
|
coherence();
|
|
resetwait(&tll->sysstatus);
|
|
tll->sysconfig |= Sidle;
|
|
coherence();
|
|
} else
|
|
iprint("no tll...");
|
|
iprint("\n");
|
|
}
|
|
|
|
/*
|
|
* there are secure sdrc registers at 0x48002460
|
|
* sdrc regs at PHYSSDRC; see spruf98c §1.2.8.2.
|
|
* set or dump l4 prot regs at PHYSL4?
|
|
*/
|
|
void
|
|
archreset(void)
|
|
{
|
|
static int beenhere;
|
|
|
|
if (beenhere)
|
|
return;
|
|
beenhere = 1;
|
|
|
|
/* conservative temporary values until archconfinit runs */
|
|
m->cpuhz = 500 * Mhz; /* beagle speed */
|
|
m->delayloop = m->cpuhz/2000; /* initial estimate */
|
|
|
|
// dumpl3pr();
|
|
prcachecfg();
|
|
/* fight omap35x errata 2.0.1.104 */
|
|
memset((void *)PHYSSWBOOTCFG, 0, 240);
|
|
coherence();
|
|
|
|
setpadmodes();
|
|
configclks(); /* may change cpu speed */
|
|
configgpio();
|
|
|
|
archconfinit();
|
|
|
|
resetusb();
|
|
fpon();
|
|
}
|
|
|
|
void
|
|
archreboot(void)
|
|
{
|
|
Prm *prm = (Prm *)PHYSPRMGLBL;
|
|
|
|
iprint("archreboot: reset!\n");
|
|
delay(20);
|
|
|
|
prm->rstctrl |= Rstgs;
|
|
coherence();
|
|
delay(500);
|
|
|
|
/* shouldn't get here */
|
|
splhi();
|
|
iprint("awaiting reset");
|
|
for(;;) {
|
|
delay(1000);
|
|
print(".");
|
|
}
|
|
}
|
|
|
|
void
|
|
lastresortprint(char *buf, long bp)
|
|
{
|
|
iprint("%.*s", (int)bp, buf); /* nothing else seems to work */
|
|
}
|
|
|
|
static void
|
|
scmdump(ulong addr, int shorts)
|
|
{
|
|
ushort reg;
|
|
ushort *ptr;
|
|
|
|
ptr = (ushort *)addr;
|
|
print("scm regs:\n");
|
|
while (shorts-- > 0) {
|
|
reg = *ptr++;
|
|
print("%#p: %#ux\tinputenable %d pulltypeselect %d "
|
|
"pulludenable %d muxmode %d\n",
|
|
ptr, reg, (reg>>8) & 1, (reg>>4) & 1, (reg>>3) & 1,
|
|
reg & 7);
|
|
}
|
|
}
|
|
|
|
char *cputype2name(char *buf, int size);
|
|
|
|
void
|
|
cpuidprint(void)
|
|
{
|
|
char name[64];
|
|
|
|
cputype2name(name, sizeof name);
|
|
delay(250); /* let uart catch up */
|
|
iprint("cpu%d: %lldMHz ARM %s\n", m->machno, m->cpuhz / Mhz, name);
|
|
}
|
|
|
|
static void
|
|
missing(ulong addr, char *name)
|
|
{
|
|
static int firstmiss = 1;
|
|
|
|
if (probeaddr(addr) >= 0)
|
|
return;
|
|
if (firstmiss) {
|
|
iprint("missing:");
|
|
firstmiss = 0;
|
|
} else
|
|
iprint(",\n\t");
|
|
iprint(" %s at %#lux", name, addr);
|
|
}
|
|
|
|
/* verify that all the necessary device registers are accessible */
|
|
void
|
|
chkmissing(void)
|
|
{
|
|
delay(20);
|
|
missing(PHYSSCM, "scm");
|
|
missing(KZERO, "dram");
|
|
missing(PHYSL3, "l3 config");
|
|
missing(PHYSINTC, "intr ctlr");
|
|
missing(PHYSTIMER1, "timer1");
|
|
missing(PHYSCONS, "console uart2");
|
|
missing(PHYSUART0, "uart0");
|
|
missing(PHYSUART1, "uart1");
|
|
missing(PHYSETHER, "smc9221"); /* not on beagle */
|
|
missing(PHYSUSBOTG, "usb otg");
|
|
missing(PHYSUHH, "usb uhh");
|
|
missing(PHYSOHCI, "usb ohci");
|
|
missing(PHYSEHCI, "usb ehci");
|
|
missing(PHYSSDMA, "dma");
|
|
missing(PHYSWDOG, "watchdog timer");
|
|
missing(PHYSUSBTLL, "usb tll");
|
|
iprint("\n");
|
|
delay(20);
|
|
}
|
|
|
|
void
|
|
archflashwp(Flash*, int)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* for ../port/devflash.c:/^flashreset
|
|
* retrieve flash type, virtual base and length and return 0;
|
|
* return -1 on error (no flash)
|
|
*/
|
|
int
|
|
archflashreset(int bank, Flash *f)
|
|
{
|
|
if(bank != 0)
|
|
return -1;
|
|
/*
|
|
* this is set up for the igepv2 board.
|
|
* if the beagleboard ever works, we'll have to sort this out.
|
|
*/
|
|
f->type = "onenand";
|
|
f->addr = (void*)PHYSNAND; /* mapped here by archreset */
|
|
f->size = 0; /* done by probe */
|
|
f->width = 1;
|
|
f->interleave = 0;
|
|
return 0;
|
|
}
|