425 lines
10 KiB
C
425 lines
10 KiB
C
enum {
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BusCBUS = 0, /* Corollary CBUS */
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BusCBUSII, /* Corollary CBUS II */
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BusEISA, /* Extended ISA */
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BusFUTURE, /* IEEE Futurebus */
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BusINTERN, /* Internal bus */
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BusISA, /* Industry Standard Architecture */
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BusMBI, /* Multibus I */
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BusMBII, /* Multibus II */
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BusMCA, /* Micro Channel Architecture */
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BusMPI, /* MPI */
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BusMPSA, /* MPSA */
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BusNUBUS, /* Apple Macintosh NuBus */
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BusPCI, /* Peripheral Component Interconnect */
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BusPCMCIA, /* PC Memory Card International Association */
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BusTC, /* DEC TurboChannel */
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BusVL, /* VESA Local bus */
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BusVME, /* VMEbus */
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BusXPRESS, /* Express System Bus */
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BUSUNKNOWN = -1
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};
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#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
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#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
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#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
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#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
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#define BUSTYPE(tbdf) ((tbdf)>>24)
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#define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
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/*
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* PCI support code.
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*/
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enum { /* type 0 & type 1 pre-defined header */
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PciVID = 0x00, /* vendor ID */
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PciDID = 0x02, /* device ID */
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PciPCR = 0x04, /* command */
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PciPSR = 0x06, /* status */
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PciRID = 0x08, /* revision ID */
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PciCCRp = 0x09, /* programming interface class code */
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PciCCRu = 0x0A, /* sub-class code */
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PciCCRb = 0x0B, /* base class code */
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PciCLS = 0x0C, /* cache line size */
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PciLTR = 0x0D, /* latency timer */
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PciHDT = 0x0E, /* header type */
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PciBST = 0x0F, /* BIST */
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};
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/* ccrb (base class code) values; controller types */
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enum {
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Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
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Pcibcstore = 1, /* mass storage */
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Pcibcnet = 2, /* network */
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Pcibcdisp = 3, /* display */
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Pcibcmmedia = 4, /* multimedia */
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Pcibcmem = 5, /* memory */
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Pcibcbridge = 6, /* bridge */
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Pcibccomm = 7, /* simple comms (e.g., serial) */
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Pcibcbasesys = 8, /* base system */
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Pcibcinput = 9, /* input */
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Pcibcdock = 0xa, /* docking stations */
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Pcibcproc = 0xb, /* processors */
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Pcibcserial = 0xc, /* serial bus (e.g., USB) */
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Pcibcwireless = 0xd, /* wireless */
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Pcibcintell = 0xe, /* intelligent i/o */
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Pcibcsatcom = 0xf, /* satellite comms */
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Pcibccrypto = 0x10, /* encryption/decryption */
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Pcibcdacq = 0x11, /* data acquisition & signal proc. */
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};
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/* ccru (sub-class code) values; common cases only */
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enum {
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/* mass storage */
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Pciscscsi = 0, /* SCSI */
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Pciscide = 1, /* IDE (ATA) */
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/* network */
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Pciscether = 0, /* Ethernet */
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/* display */
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Pciscvga = 0, /* VGA */
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Pciscxga = 1, /* XGA */
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Pcisc3d = 2, /* 3D */
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/* bridges */
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Pcischostpci = 0, /* host/pci */
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Pciscpcicpci = 1, /* pci/pci */
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/* simple comms */
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Pciscserial = 0, /* 16450, etc. */
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Pciscmultiser = 1, /* multiport serial */
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/* serial bus */
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Pciscusb = 3, /* USB */
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};
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enum { /* type 0 pre-defined header */
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PciCIS = 0x28, /* cardbus CIS pointer */
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PciSVID = 0x2C, /* subsystem vendor ID */
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PciSID = 0x2E, /* subsystem ID */
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PciEBAR0 = 0x30, /* expansion ROM base address */
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PciMGNT = 0x3E, /* burst period length */
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PciMLT = 0x3F, /* maximum latency between bursts */
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};
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enum { /* type 1 pre-defined header */
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PciPBN = 0x18, /* primary bus number */
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PciSBN = 0x19, /* secondary bus number */
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PciUBN = 0x1A, /* subordinate bus number */
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PciSLTR = 0x1B, /* secondary latency timer */
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PciIBR = 0x1C, /* I/O base */
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PciILR = 0x1D, /* I/O limit */
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PciSPSR = 0x1E, /* secondary status */
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PciMBR = 0x20, /* memory base */
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PciMLR = 0x22, /* memory limit */
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PciPMBR = 0x24, /* prefetchable memory base */
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PciPMLR = 0x26, /* prefetchable memory limit */
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PciPUBR = 0x28, /* prefetchable base upper 32 bits */
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PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
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PciIUBR = 0x30, /* I/O base upper 16 bits */
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PciIULR = 0x32, /* I/O limit upper 16 bits */
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PciEBAR1 = 0x28, /* expansion ROM base address */
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PciBCR = 0x3E, /* bridge control register */
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};
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enum { /* type 2 pre-defined header */
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PciCBExCA = 0x10,
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PciCBSPSR = 0x16,
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PciCBPBN = 0x18, /* primary bus number */
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PciCBSBN = 0x19, /* secondary bus number */
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PciCBUBN = 0x1A, /* subordinate bus number */
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PciCBSLTR = 0x1B, /* secondary latency timer */
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PciCBMBR0 = 0x1C,
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PciCBMLR0 = 0x20,
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PciCBMBR1 = 0x24,
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PciCBMLR1 = 0x28,
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PciCBIBR0 = 0x2C, /* I/O base */
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PciCBILR0 = 0x30, /* I/O limit */
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PciCBIBR1 = 0x34, /* I/O base */
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PciCBILR1 = 0x38, /* I/O limit */
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PciCBSVID = 0x40, /* subsystem vendor ID */
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PciCBSID = 0x42, /* subsystem ID */
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PciCBLMBAR = 0x44, /* legacy mode base address */
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};
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typedef struct Pcisiz Pcisiz;
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struct Pcisiz
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{
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Pcidev* dev;
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int siz;
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int bar;
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};
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typedef struct Pcidev Pcidev;
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struct Pcidev
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{
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int tbdf; /* type+bus+device+function */
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ushort vid; /* vendor ID */
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ushort did; /* device ID */
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ushort pcr;
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uchar rid;
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uchar ccrp;
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uchar ccru;
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uchar ccrb;
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uchar cls;
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uchar ltr;
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struct {
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ulong bar; /* base address */
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int size;
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} mem[6];
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struct {
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ulong bar;
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int size;
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} rom;
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uchar intl; /* interrupt line */
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Pcidev* list;
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Pcidev* link; /* next device on this bno */
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Pcidev* bridge; /* down a bus */
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struct {
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ulong bar;
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int size;
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} ioa, mema;
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int pmrb; /* power management register block */
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};
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#define PCIWINDOW 0
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#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
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/*
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* Kirkwood stuff
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*/
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enum {
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AddrEfuse = PHYSIO+0x1008c,
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Addrpci = PHYSIO+0x40000, /* for registers below */
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Addrpcibase = PHYSIO+0x41800, /* for registers below */
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AddrMpp = PHYSIO+0x10000,
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AddrSdio = PHYSIO+0x90000,
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};
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enum {
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Socrevz0,
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Socreva0 = 2,
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Socreva1,
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};
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enum {
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/* registers; if we actually use these, change to soc.pci(base)->reg */
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PciBAR0 = Addrpcibase + 4, /* base address */
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PciBAR1 = Addrpcibase + 8,
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PciCP = Addrpci + 0x64, /* capabilities pointer */
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PciINTL = Addrpci + 0x3c, /* interrupt line */
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PciINTP = PciINTL + 1, /* interrupt pin */
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};
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/*
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* interrupt stuff
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*/
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enum {
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Irqlo, Irqhi, Irqbridge,
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};
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enum {
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/* main interrupt cause low register bit #s (LE) */
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IRQ0hisum, /* summary of main intr high cause reg */
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IRQ0bridge,
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IRQ0h2cdoorbell,
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IRQ0c2hdoorbell,
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_IRQ0reserved0,
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IRQ0xor0chan0,
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IRQ0xor0chan1,
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IRQ0xor1chan0,
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IRQ0xor1chan1,
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IRQ0pex0int, /* pex = pci-express */
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_IRQ0reserved1,
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IRQ0gbe0sum,
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IRQ0gbe0rx,
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IRQ0gbe0tx,
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IRQ0gbe0misc,
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IRQ0gbe1sum,
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IRQ0gbe1rx,
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IRQ0gbe1tx,
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IRQ0gbe1misc,
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IRQ0usb0,
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_IRQ0reserved2,
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IRQ0sata,
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IRQ0crypto,
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IRQ0spi,
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IRQ0audio,
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_IRQ0reserved3,
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IRQ0ts0,
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_IRQ0reserved4,
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IRQ0sdio,
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IRQ0twsi,
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IRQ0avb,
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IRQ0tdm,
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/* main interrupt cause high register bit #s (LE) */
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_IRQ1reserved0 = 0,
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IRQ1uart0,
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IRQ1uart1,
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IRQ1gpiolo0,
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IRQ1gpiolo1,
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IRQ1gpiolo2,
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IRQ1gpiolo3,
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IRQ1gpiohi0,
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IRQ1gpiohi1,
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IRQ1gpiohi2,
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IRQ1gpiohi3,
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IRQ1xor0err,
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IRQ1xor1err,
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IRQ1pex0err,
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_IRQ1reserved1,
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IRQ1gbe0err,
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IRQ1gbe1err,
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IRQ1usberr,
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IRQ1cryptoerr,
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IRQ1audioerr,
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_IRQ1reserved2,
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_IRQ1reserved3,
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IRQ1rtc,
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/* bridged-interrupt causes */
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IRQcpuself = 0,
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IRQcputimer0,
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IRQcputimer1,
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IRQcputimerwd,
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IRQaccesserr,
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};
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/*
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* interrupt controller
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*/
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typedef struct IntrReg IntrReg;
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struct IntrReg
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{
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struct {
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ulong irq; /* main intr cause reg (ro) */
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ulong irqmask;
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ulong fiqmask;
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ulong epmask;
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} lo, hi;
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};
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/*
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* CPU control & status (archkw.c and trap.c)
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*/
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typedef struct CpucsReg CpucsReg;
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struct CpucsReg
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{
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ulong cpucfg;
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ulong cpucsr;
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ulong rstout;
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ulong softreset;
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ulong irq; /* mbus(-l) bridge interrupt cause */
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ulong irqmask; /* ⋯ mask */
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ulong mempm; /* memory power mgmt. control */
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ulong clockgate; /* clock enable bits */
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ulong biu;
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ulong pad0;
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ulong l2cfg; /* turn l2 cache on or off, set coherency */
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ulong pad1[2];
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ulong l2tm0;
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ulong l2tm1;
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ulong pad2[2];
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ulong l2pm;
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ulong ram0;
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ulong ram1;
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ulong ram2;
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ulong ram3;
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};
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enum {
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/* cpucfg bits */
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Cfgvecinithi = 1<<1, /* boot at 0xffff0000, not 0; default 1 */
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Cfgbigendreset = 3<<1, /* init. as big-endian at reset; default 0 */
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Cfgiprefetch = 1<<16, /* instruction prefetch enable */
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Cfgdprefetch = 1<<17, /* data prefetch enable */
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/* cpucsr bits */
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Reset = 1<<1, /* reset cpu core */
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/* rstout bits */
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RstoutPex = 1<<0, /* assert RSTOUTn at pci-e reset */
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RstoutWatchdog = 1<<1, /* assert RSTOUTn at watchdog timeout */
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RstoutSoft = 1<<2, /* assert RSTOUTn at sw reset */
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/* softreset bits */
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ResetSystem = 1<<0, /* assert RSTOUTn pin on SoftRstOutEn */
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/* l2cfg bits */
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L2ecc = 1<<2,
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L2exists = 1<<3, /* l2 cache doesn't ignore cpu */
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L2writethru = 1<<4, /* always WT, else see PTE C & B */
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};
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enum {
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/* from 88f6281 func'l specs (MV-S104860-00), tables 2 & 3, chapter 2 */
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Targdram = 0, /* ddr sdram */
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Targflash = 1,
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Targcesasram = 3, /* security accelerator sram */
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/* attributes */
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Attrcs0 = 0xe, /* chip select 0 (low dram) */
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Attrcs1 = 0xd, /* chip select 1 (high dram) */
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Attrbootrom = 0x1d,
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Attrspi = 0x1e,
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Attrnand = 0x2f,
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Winenable = 1<<0,
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};
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typedef struct Pciex Pciex;
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struct Pciex {
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ushort venid; /* 0x11ab means Marvell */
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ushort devid; /* 0x6281 means 6281 */
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ulong csr;
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ulong revid;
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ulong bistcache; /* bist hdr type & cache-line size */
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ulong bar0;
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ulong bar0hi;
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ulong bar1;
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ulong bar1hi;
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ulong bar2;
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ulong bar2hi;
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ulong _pad0;
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ushort ssvenid; /* 0x11ab means Marvell */
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ushort ssdevid; /* 0x11ab means Marvell */
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ulong rombar;
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ulong caplist;
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ulong _pad1;
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ulong intrpinline; /* interrupt pin & line */
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ulong pmcap; /* power mgmt. capability header */
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ulong pmcsr; /* power mgmt. control & status */
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ulong _pad2[2];
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ulong msictl; /* msi message control */
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ulong msiaddr;
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ulong msiaddrhi;
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ulong msidata;
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ulong cap;
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ulong devcap;
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ulong devcsr;
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ulong linkcap;
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ulong linkcsr;
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uchar _pad[0x40100-0x40074];
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ulong errrep; /* advanced error report header */
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ulong uncorrerr; /* uncorrectable error status */
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ulong uncorrerrmask; /* uncorrectable error mask */
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ulong uncorrerrsev; /* uncorrectable error severity */
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ulong correrr; /* correctable error status */
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ulong correrrmask; /* correctable error mask */
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ulong errcap; /* advanced error capability & ctl. */
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ulong hdrlog[4]; /* header log */
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/* continues with more rubbish at 0x41a00. some day... */
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};
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