d6e0e9c402
the only architecture dependence of devether was enabling interrupts, which is now done at the end of the driver's reset() function now. the wifi stack and dummy ethersink also go to port/. do the IRQ2->IRQ9 hack for pc kernels in intrenabale(), so not every caller of intrenable() has to be aware of it.
208 lines
6.8 KiB
C
208 lines
6.8 KiB
C
/*
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* Memory and machine-specific definitions. Used in C and assembler.
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*/
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#define KiB 1024u /* Kibi 0x0000000000000400 */
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#define MiB 1048576u /* Mebi 0x0000000000100000 */
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#define GiB 1073741824u /* Gibi 000000000040000000 */
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#define MIN(a, b) ((a) < (b)? (a): (b))
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#define MAX(a, b) ((a) > (b)? (a): (b))
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/*
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* Not sure where these macros should go.
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* This probably isn't right but will do for now.
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* The macro names are problematic too.
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*/
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/*
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* In B(o), 'o' is the bit offset in the register.
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* For multi-bit fields use F(v, o, w) where 'v' is the value
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* of the bit-field of width 'w' with LSb at bit offset 'o'.
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*/
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#define B(o) (1<<(o))
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#define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
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#define FCLR(d, o, w) ((d) & ~(((1<<(w))-1)<<(o)))
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#define FEXT(d, o, w) (((d)>>(o)) & ((1<<(w))-1))
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#define FINS(d, o, w, v) (FCLR((d), (o), (w))|F((v), (o), (w)))
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#define FSET(d, o, w) ((d)|(((1<<(w))-1)<<(o)))
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#define FMASK(o, w) (((1<<(w))-1)<<(o))
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/*
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* Sizes
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*/
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#define BY2PG (4*KiB) /* bytes per page */
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#define PGSHIFT 12 /* log(BY2PG) */
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#define PGROUND(s) ROUND(s, BY2PG)
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#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
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#define MAXMACH 1 /* max # cpus system can run */
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#define MACHSIZE BY2PG
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#define KSTKSIZE (16*KiB) /* was 8K */
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#define STACKALIGN(sp) ((sp) & ~3) /* bug: assure with alloc */
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/*
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* Address spaces.
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* KTZERO is used by kprof and dumpstack (if any).
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*
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* KZERO (0xc0000000) is mapped to physical 0x80000000 (start of dram).
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* u-boot claims to occupy the first 3 MB of dram, but we're willing to
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* step on it once we're loaded. Expect plan9.ini in the first 64K past 3MB.
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*
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* L2 PTEs are stored in 1K before Mach (11K to 12K above KZERO).
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* cpu0's Mach struct is at L1 - MACHSIZE(4K) to L1 (12K to 16K above KZERO).
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* L1 PTEs are stored from L1 to L1+32K (16K to 48K above KZERO).
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* KTZERO may be anywhere after that (but probably shouldn't collide with
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* u-boot).
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* This should leave over 8K from KZERO to L2 PTEs.
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*/
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#define KSEG0 0xC0000000 /* kernel segment */
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/* mask to check segment; good for 512MB dram */
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#define KSEGM 0xE0000000
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#define KZERO KSEG0 /* kernel address space */
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#define L1 (KZERO+16*KiB) /* tt ptes: 16KiB aligned */
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#define CONFADDR (KZERO+0x300000) /* unparsed plan9.ini */
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/* KTZERO must match loadaddr in mkfile */
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#define KTZERO (KZERO+0x310000) /* kernel text start */
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#define UZERO 0 /* user segment */
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#define UTZERO (UZERO+BY2PG) /* user text start */
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/* moved USTKTOP down to 512MB to keep MMIO space out of user space. */
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#define USTKTOP 0x20000000 /* user segment end +1 */
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#define USTKSIZE (8*1024*1024) /* user stack size */
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/* address at which to copy and execute rebootcode */
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#define REBOOTADDR KADDR(0x100)
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/*
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* Legacy...
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*/
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#define BLOCKALIGN 32 /* only used in allocb.c */
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#define KSTACK KSTKSIZE
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/*
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* Sizes
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*/
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#define BI2BY 8 /* bits per byte */
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#define BY2SE 4
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#define BY2WD 4
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#define BY2V 8 /* only used in xalloc.c */
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#define CACHELINESZ 64 /* bytes per cache line */
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#define PTEMAPMEM (1024*1024)
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#define PTEPERTAB (PTEMAPMEM/BY2PG)
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#define SEGMAPSIZE 1984 /* magic 16*124 */
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#define SSEGMAPSIZE 16 /* magic */
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#define PPN(x) ((x)&~(BY2PG-1)) /* pure page number? */
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/*
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* With a little work these move to port.
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*/
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#define PTEVALID (1<<0)
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#define PTERONLY 0
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#define PTEWRITE (1<<1)
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#define PTEUNCACHED (1<<2)
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#define PTEKERNEL (1<<3)
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/*
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* Physical machine information from here on.
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*/
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/* gpmc-controlled address space 0—1G */
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#define PHYSNAND 1 /* cs0 is onenand flash */
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#define PHYSETHER 0x2c000000
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#define PHYSIO 0x48000000 /* L4 ctl */
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#define PHYSSCM 0x48002000 /* system control module */
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/* core control pad cfg 0x48002030—0x480021e4, */
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/* core control d2d pad cfg 0x480021e4—0x48002264 */
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#define PHYSSCMPCONF 0x48002270 /* general device config */
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#define PHYSOMAPSTS 0x4800244c /* standalone short: has l2 size */
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/* core control pad cfg (2) 0x480025d8—0x480025fc */
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#define PHYSSWBOOTCFG 0x48002910 /* sw booting config */
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/* wakeup control pad cfg 0x48002a00—0x48002a54 */
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#define PHYSSCMMPU 0x48004900 /* actually CPU */
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#define PHYSSCMCORE 0x48004a00
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#define PHYSSCMWKUP 0x48004c00
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#define PHYSSCMPLL 0x48004d00 /* clock ctl for dpll[3-5] */
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#define PHYSSCMDSS 0x48004e00
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#define PHYSSCMPER 0x48005000
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#define PHYSSCMUSB 0x48005400
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#define PHYSL4CORE 0x48040100 /* l4 ap */
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#define PHYSDSS 0x48050000 /* start of dss registers */
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#define PHYSDISPC 0x48050400
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#define PHYSGFX 0x48050480 /* part of dispc */
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#define PHYSSDMA 0x48056000 /* system dma */
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#define PHYSDMA 0x48060000
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#define PHYSUSBTLL 0x48062000 /* usb: transceiver-less link */
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#define PHYSUHH 0x48064000 /* usb: `high-speed usb host' ctlr or subsys */
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#define PHYSOHCI 0x48064400 /* usb 1.0: slow */
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#define PHYSEHCI 0x48064800 /* usb 2.0: medium */
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#define PHYSUART0 0x4806a000
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#define PHYSUART1 0x4806c000
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#define PHYSMMCHS1 0x4809c000 /* mmc/sdio */
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#define PHYSUSBOTG 0x480ab000 /* on-the-go usb */
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#define PHYSMMCHS3 0x480ad000
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#define PHYSMMCHS2 0x480b4000
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#define PHYSINTC 0x48200000 /* interrupt controller */
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#define PHYSPRMIVA2 0x48206000 /* prm iva2 regs */
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/* 48306d40 sys_clkin_sel */
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#define PHYSPRMGLBL 0x48307200 /* prm global regs */
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#define PHYSPRMWKUSB 0x48307400
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#define PHYSCNTRL 0x4830a200 /* SoC id, etc. */
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#define PHYSWDT1 0x4830c000 /* wdt1, not on GP omaps */
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#define PHYSGPIO1 0x48310000 /* contains dss gpio */
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#define PHYSWDOG 0x48314000 /* watchdog timer, wdt2 */
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#define PHYSWDT2 0x48314000 /* watchdog timer, wdt2 */
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#define PHYSTIMER1 0x48318000
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#define PHYSL4WKUP 0x48328100 /* l4 wkup */
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#define PHYSL4PER 0x49000100 /* l4 per */
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#define PHYSCONS 0x49020000 /* uart console (third one) */
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#define PHYSWDT3 0x49030000 /* wdt3 */
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#define PHYSTIMER2 0x49032000
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#define PHYSTIMER3 0x49034000
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#define PHYSGPIO5 0x49056000
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#define PHYSGPIO6 0x49058000 /* contains igep ether gpio */
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#define PHYSIOEND 0x49100000 /* end of PHYSIO identity map */
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#define PHYSL4EMU 0x54006100 /* l4 emu */
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#define PHYSL4PROT 0x54728000 /* l4 protection regs */
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#define PHYSL3 0x68000000 /* l3 interconnect control */
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#define PHYSL3GPMCCFG 0x68002000 /* l3 gpmc target port agent cfg */
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#define PHYSL3USB 0x68004000 /* l3 regs for usb */
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#define PHYSL3USBOTG 0x68004400 /* l3 regs for usb otg */
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/* (target port) protection registers */
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#define PHYSL3PMRT 0x68010000 /* l3 PM register target prot. */
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#define PHYSL3GPMCPM 0x68012400 /* l3 gpmc target port protection */
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#define PHYSL3OCTRAM 0x68012800 /* l3 ocm ram */
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#define PHYSL3OCTROM 0x68012c00 /* l3 ocm rom */
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#define PHYSL3MAD2D 0x68013000 /* l3 die-to-die */
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#define PHYSL3IVA 0x68014000 /* l3 die-to-die */
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#define PHYSSMS 0x6c000000 /* cfg regs: sms addr space 2 */
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#define PHYSDRC 0x6d000000 /* sdram ctlr, addr space 3 */
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#define PHYSGPMC 0x6e000000 /* flash, non-dram memory ctlr */
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#define PHYSDRAM 0x80000000
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#define VIRTNAND 0x20000000 /* fixed by u-boot */
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#define VIRTIO PHYSIO
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