931ae0cfeb
supports the lcd panel and adds alot of infrastructure like for the ccm clock module and the i2c controllers.
405 lines
9.2 KiB
C
405 lines
9.2 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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enum {
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URXD = 0x00/4, /* UART Receiver Register */
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RX_CHARRDY = 1<<15,
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RX_ERR = 1<<14,
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RX_OVRRUN = 1<<13,
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RX_FRMERR = 1<<12,
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RX_BRK = 1<<11,
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RX_PRERR = 1<<10,
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RX_DATA = 0xFF,
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UTXD = 0x40/4, /* UART Transmitter Register */
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TX_DATA = 0xFF,
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UCR1 = 0x80/4, /* UART Control Register 1 */
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CR1_ADEN = 1<<15, /* Automatic Baud Rate Detection Interrupt Enable */
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CR1_ADNR = 1<<14, /* Automatic Detection of Baud Rate */
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CR1_TRDYEN = 1<<13, /* Transmitter Ready Interrupt Enable */
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CR1_IDEN = 1<<12, /* Idle Condition Detected Interrupt Enable */
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CR1_ICD_SHIFT = 10, /* Idle Condition Detect Mask */
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CR1_ICD_MASK = 3<<CR1_ICD_SHIFT,
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CR1_RRDYEN = 1<<9, /* Receiver Ready Interrupt Enable */
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CR1_RXDMAEN = 1<<8, /* Receive Ready DMA Enable */
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CR1_IREN = 1<<7, /* Infrared Interface Enable */
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CR1_TXMPTYEN = 1<<6, /* Transmitter Empty Interrupt Enable */
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CR1_RTSDEN = 1<<5, /* RTS Delta Interrupt Enable */
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CR1_SNDBRK = 1<<4, /* Send BREAK */
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CR1_TXDMAEN = 1<<3, /* Transmitter Ready DMA Enable */
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CR1_ATDMAEN = 1<<2, /* Aging DMA Timer Enable */
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CR1_DOZE = 1<<1, /* DOZE */
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CR1_UARTEN = 1<<0, /* Uart Enable */
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UCR2 = 0x84/4, /* UART Control Register 2 */
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CR2_ESCI = 1<<15, /* Escape Sequence Interrupt Enable */
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CR2_IRTS = 1<<14, /* Ignore RTS Pin */
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CR2_CTSC = 1<<13, /* CTS Pin Control */
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CR2_CTS = 1<<12, /* Clear to Send */
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CR2_ESCEN = 1<<11, /* Escape Enable */
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CR2_RTEC_RAISING= 0<<9,
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CR2_RTEC_FALLING= 1<<9,
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CR2_RTEC_ANY = 2<<9,
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CR2_RTEC_MASK = 3<<9,
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CR2_PREN = 1<<8, /* Parity Enable */
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CR2_PREVEN = 0<<7, /* Parity Even */
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CR2_PRODD = 1<<7, /* Parity Odd */
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CR2_STPB = 1<<6, /* Stop */
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CR2_WS8 = 1<<5, /* Word Size */
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CR2_WS7 = 0<<5,
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CR2_RTSEN = 1<<4, /* Request to Send Interrupt Enable */
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CR2_ATEN = 1<<3, /* Aging Timer Enable */
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CR2_TXEN = 1<<2, /* Transmitter Enable */
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CR2_RXEN = 1<<1, /* Receiver Enable */
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CR2_SRST = 1<<0, /* Software Reset */
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UCR3 = 0x88/4, /* UART Control Register 3 */
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CR3_PARERREN = 1<<12, /* Parity Error Interrupt Enable */
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CR3_FRAERREN = 1<<11, /* Frame Error Interrupt Enable */
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CR3_ADNIMP = 1<<7, /* Autobaud Detection Not Improved */
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CR3_RXDSEN = 1<<6, /* Receive Status Interrupt Enable */
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CR3_AIRINTEN = 1<<5, /* Asynchronous IR WAKE Interrupt Enable */
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CR3_AWAKEN = 1<<4, /* Asynchronous WAKE Interrupt Enable */
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CR3_RXDMUXSEL = 1<<2, /* RXD Muxed Input Selected */
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CR3_INVT = 1<<1, /* Invert TXD output in RS-232/RS-485 mode */
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CR3_ACIEN = 1<<0, /* Autobaud Counter Interrupt Enable */
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UCR4 = 0x8C/4, /* UART Control Register 4 */
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CR4_CTSTL_SHIFT = 10, /* CTS Trigger Level */
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CR4_CTSTL_MASK = 0x3F<<CR4_CTSTL_SHIFT,
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CR4_INVR = 1<<9, /* Invert RXD Input in RS-232/RS-485 Mode */
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CR4_ENIRI = 1<<8, /* Serial Infrared Interrupt Enable */
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CR4_WKEN = 1<<7, /* WAKE Interrupt Enable */
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CR4_IDDMAEN = 1<<6, /* DMA IDLE Condition Detected Interrupt Enable */
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CR4_IRSC = 1<<5, /* IR Special Case */
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CR4_LPBYP = 1<<4, /* Low Power Bypass */
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CR4_TCEN = 1<<3, /* Transmit Complete Interrupt Enable */
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CR4_BKEN = 1<<2, /* BREAK Condition Detected Interrupt Enable */
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CR4_OREN = 1<<1, /* Receiver Overrun Interrupt Enable */
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CR4_DREN = 1<<0, /* Receive Data Interrupt Enable */
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UFCR = 0x90/4, /* UART FIFO Control Register */
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FCR_TXTL_SHIFT = 10, /* Transmitter Trigger Level */
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FCR_TXTL_MASK = 0x3F<<FCR_TXTL_SHIFT,
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FCR_RFDIV_SHIFT = 7, /* Reference Frequency Divider */
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FCR_RFDIV_MASK = 0x7<<FCR_RFDIV_SHIFT,
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FCR_DCE = 0<<6, /* DCE/DTE mode select */
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FCR_DTE = 1<<6,
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FCR_RXTL_SHIFT = 0, /* Receive Trigger Level */
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FCR_RXTL_MASK = 0x3F<<FCR_RXTL_SHIFT,
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USR1 = 0x94/4, /* UART Status Register 1 */
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SR1_PARITYERR = 1<<15, /* Parity Error Interrupt Flag */
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SR1_RTSS = 1<<14, /* RTS_B Pin Status */
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SR1_TRDY = 1<<13, /* Transmitter Ready Interrupt / DMA Flag */
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SR1_RTSD = 1<<12, /* RTS Delta */
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SR1_ESCF = 1<<11, /* Escape Sequence Interrupt Flag */
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SR1_FRAMEERR = 1<<10, /* Frame Error Interrupt Flag */
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SR1_RRDY = 1<<9, /* Receiver Ready Interrupt / DMA Flag */
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SR1_AGTIM = 1<<8, /* Aging Timer Interrupt Flag */
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SR1_DTRD = 1<<7,
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SR1_RXDS = 1<<6, /* Receiver IDLE Interrupt Flag */
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SR1_AIRINT = 1<<5, /* Asynchronous IR WAKE Interrupt Flag */
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SR1_AWAKE = 1<<4, /* Asynchronous WAKE Interrupt Flag */
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SR1_SAD = 1<<3, /* RS-485 Slave Address Detected Interrupt Flag */
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USR2 = 0x98/4, /* UART Status Register 2 */
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SR2_ADET = 1<<15, /* Automatic Baud Rate Detected Complete */
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SR2_TXFE = 1<<14, /* Transmit Buffer FIFO Empty */
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SR2_DTRF = 1<<13,
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SR2_IDLE = 1<<12, /* Idle Condition */
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SR2_ACST = 1<<11, /* Autobaud Counter Stopped */
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SR2_RIDELT = 1<<10,
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SR2_RIIN = 1<<9,
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SR2_IRINT = 1<<8, /* Serial Infrared Interrupt Flag */
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SR2_WAKE = 1<<7, /* Wake */
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SR2_DCDDELT = 1<<6,
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SR2_DCDIN = 1<<5,
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SR2_RTSF = 1<<4, /* RTS Edge Triggered Interrupt Flag */
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SR2_TXDC = 1<<3, /* Transmitter Complete */
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SR2_BRCD = 1<<2, /* BREAK Condition Detected */
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SR2_ORE = 1<<1, /* Overrun Error */
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SR2_RDR = 1<<0, /* Receive Data Ready */
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UESC = 0x9C/4, /* UART Escape Character Register */
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UTIM = 0xA0/4, /* UART Escape Timer Register */
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UBIR = 0xA4/4, /* UART BRM Incremental Modulator Register */
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UBMR = 0xA8/4, /* UART BRM Modulator Register */
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UBRC = 0xAC/4, /* UART Baud Rate Count Register */
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ONEMS = 0xB0/4, /* UART One-Millisecond Register */
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UTS = 0xB5/4, /* UART Test Register */
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UMCR = 0xB8/4, /* UART RS-485 Mode Control Register */
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};
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extern PhysUart imxphysuart;
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static Uart uart1 = {
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.regs = (u32int*)(VIRTIO + 0x860000ULL),
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.name = "uart1",
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.baud = 115200,
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.freq = 25*Mhz,
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.phys = &imxphysuart,
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};
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static Uart*
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pnp(void)
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{
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return &uart1;
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}
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static void
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kick(Uart *u)
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{
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u32int *regs = (u32int*)u->regs;
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while(u->op < u->oe || uartstageoutput(u)){
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if(u->blocked)
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break;
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if((regs[USR1] & SR1_TRDY) == 0){
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regs[UCR1] |= CR1_TRDYEN;
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return;
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}
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regs[UTXD] = *(u->op++) & TX_DATA;
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}
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regs[UCR1] &= ~CR1_TRDYEN;
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}
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static void
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config(Uart *u)
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{
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u32int cr2, *regs = u->regs;
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/* enable uart */
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regs[UCR1] = CR1_UARTEN;
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cr2 = CR2_SRST | CR2_IRTS | CR2_RXEN | CR2_TXEN;
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switch(u->parity){
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case 'e': cr2 |= CR2_PREN | CR2_PREVEN; break;
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case 'o': cr2 |= CR2_PREN | CR2_PRODD; break;
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}
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cr2 |= u->bits == 7 ? CR2_WS7 : CR2_WS8;
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if(u->stop == 2) cr2 |= CR2_STPB;
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regs[UCR2] = cr2;
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regs[UCR3] = 0x7<<8 | CR3_RXDMUXSEL;
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regs[UCR4] = 31<<CR4_CTSTL_SHIFT;
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/* baud = clock / (16 * (ubmr+1)/(ubir+1)) */
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regs[UFCR] = (6 - 1)<<FCR_RFDIV_SHIFT | 16<<FCR_TXTL_SHIFT | 1<<FCR_RXTL_SHIFT;
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regs[UBIR] = ((16*u->baud) / 1600)-1;
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regs[UBMR] = (u->freq / 1600)-1;
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regs[UCR1] = CR1_UARTEN | CR1_RRDYEN;
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}
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static int
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bits(Uart *u, int n)
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{
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switch(n){
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case 8:
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break;
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case 7:
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break;
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default:
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return -1;
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}
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u->bits = n;
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config(u);
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return 0;
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}
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static int
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stop(Uart *u, int n)
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{
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switch(n){
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case 1:
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break;
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case 2:
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break;
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default:
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return -1;
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}
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u->stop = n;
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config(u);
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return 0;
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}
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static int
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parity(Uart *u, int n)
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{
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switch(n){
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case 'n':
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break;
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case 'e':
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break;
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case 'o':
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break;
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default:
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return -1;
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}
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u->parity = n;
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config(u);
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return 0;
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}
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static int
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baud(Uart *u, int n)
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{
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if(u->freq == 0 || n <= 0)
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return -1;
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u->baud = n;
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config(u);
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return 0;
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}
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static void
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rts(Uart*, int)
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{
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}
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static void
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dobreak(Uart*, int)
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{
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}
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static long
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status(Uart *uart, void *buf, long n, long offset)
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{
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char *p;
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p = malloc(READSTR);
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if(p == nil)
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error(Enomem);
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snprint(p, READSTR,
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"b%d\n"
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"dev(%d) type(%d) framing(%d) overruns(%d) "
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"berr(%d) serr(%d)\n",
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uart->baud,
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uart->dev,
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uart->type,
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uart->ferr,
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uart->oerr,
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uart->berr,
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uart->serr
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);
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n = readstr(offset, buf, n, p);
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free(p);
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return n;
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}
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static void
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interrupt(Ureg*, void *arg)
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{
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Uart *uart = arg;
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u32int v, *regs = (u32int*)uart->regs;
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while((v = regs[URXD]) & RX_CHARRDY)
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uartrecv(uart, v & RX_DATA);
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uartkick(uart);
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}
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static void
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clkenable(Uart *u, int on)
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{
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char clk[32];
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snprint(clk, sizeof(clk), "%s.ipg_perclk", u->name);
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if(on) setclkrate(clk, "osc_25m_ref_clk", u->freq);
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setclkgate(clk, on);
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}
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static void
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disable(Uart *u)
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{
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u32int *regs = u->regs;
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if(u->console)
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return; /* avoid glitch */
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regs[UCR1] = 0;
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clkenable(u, 0);
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}
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static void
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enable(Uart *u, int ie)
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{
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disable(u);
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clkenable(u, 1);
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if(ie) intrenable(IRQuart1, interrupt, u, BUSUNKNOWN, u->name);
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config(u);
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}
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static void
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donothing(Uart*, int)
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{
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}
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static void
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putc(Uart *u, int c)
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{
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u32int *regs = u->regs;
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while((regs[USR1] & SR1_TRDY) == 0)
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;
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regs[UTXD] = c & TX_DATA;
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}
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static int
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getc(Uart *u)
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{
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u32int c, *regs = (u32int*)u->regs;
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do
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c = regs[URXD];
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while((c & RX_CHARRDY) == 0);
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return c & RX_DATA;
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}
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void
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uartconsinit(void)
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{
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consuart = &uart1;
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consuart->console = 1;
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uartctl(consuart, "l8 pn s1");
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uartputs(kmesg.buf, kmesg.n);
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}
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PhysUart imxphysuart = {
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.name = "imx",
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.pnp = pnp,
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.enable = enable,
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.disable = disable,
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.kick = kick,
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.dobreak = dobreak,
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.baud = baud,
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.bits = bits,
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.stop = stop,
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.parity = parity,
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.modemctl = donothing,
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.rts = rts,
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.dtr = donothing,
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.status = status,
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.fifo = donothing,
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.getc = getc,
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.putc = putc,
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};
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