fff070f2cb
This is a work in progress port to the mntreform2 laptop. Working so far: - mmu (same as raspberry pi 3b+) - arm generic timer - gicv3 - uart1 - enet With access to the uart, one can netboot this kernel in u-boot using the following commands: > dhcp > bootm
213 lines
3.1 KiB
ArmAsm
213 lines
3.1 KiB
ArmAsm
#include "sysreg.h"
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#undef SYSREG
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#define SYSREG(op0,op1,Cn,Cm,op2) SPR(((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5))
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/*
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* instruction cache operations
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*/
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TEXT cacheiinvse(SB), 1, $-4
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MOVWU len+8(FP), R2
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ADD R0, R2
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MRS DAIF, R11
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MSR $0x2, DAIFSet
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MOVWU $1, R10
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MSR R10, CSSELR_EL1
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ISB $SY
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MRS CCSIDR_EL1, R4
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ANDW $7, R4
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ADDW $4, R4 // log2(linelen)
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LSL R4, R10
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LSR R4, R0
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LSL R4, R0
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_iinvse:
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IC R0, 3,7,5,1 // IVAU
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ADD R10, R0
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CMP R0, R2
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BGT _iinvse
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DSB $NSH
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ISB $SY
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MSR R11, DAIF
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RETURN
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TEXT cacheiinv(SB), 1, $-4
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IC R0, 0,7,5,0 // IALLU
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DSB $NSH
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ISB $SY
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RETURN
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TEXT cacheuwbinv(SB), 1, $0
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BL cachedwbinv(SB)
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BL cacheiinv(SB)
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RETURN
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/*
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* data cache operations
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*/
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TEXT cachedwbse(SB), 1, $-4
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MOV LR, R29
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BL cachedva<>(SB)
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TEXT dccvac(SB), 1, $-4
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DC R0, 3,7,10,1 // CVAC
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RETURN
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TEXT cacheduwbse(SB), 1, $-4
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MOV LR, R29
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BL cachedva<>(SB)
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TEXT dccvau(SB), 1, $-4
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DC R0, 3,7,11,1 // CVAU
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RETURN
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TEXT cachedinvse(SB), 1, $-4
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MOV LR, R29
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BL cachedva<>(SB)
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TEXT dcivac(SB), 1, $-4
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DC R0, 0,7,6,1 // IVAC
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RETURN
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TEXT cachedwbinvse(SB), 1, $-4
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MOV LR, R29
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BL cachedva<>(SB)
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TEXT dccivac(SB), 1, $-4
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DC R0, 3,7,14,1 // CIVAC
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RETURN
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TEXT cachedva<>(SB), 1, $-4
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MOV LR, R1
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MOVWU len+8(FP), R2
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ADD R0, R2
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MRS DAIF, R11
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MSR $0x2, DAIFSet
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MOVWU $0, R10
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MSR R10, CSSELR_EL1
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ISB $SY
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MRS CCSIDR_EL1, R4
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ANDW $7, R4
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ADDW $4, R4 // log2(linelen)
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MOVWU $1, R10
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LSL R4, R10
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LSR R4, R0
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LSL R4, R0
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DSB $SY
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ISB $SY
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_cachedva:
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BL (R1)
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ADD R10, R0
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CMP R0, R2
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BGT _cachedva
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DSB $SY
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ISB $SY
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MSR R11, DAIF
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RET R29
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/*
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* l1 cache operations
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*/
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TEXT cachedwb(SB), 1, $-4
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MOVWU $0, R0
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_cachedwb:
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MOV LR, R29
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BL cachedsw<>(SB)
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TEXT dccsw(SB), 1, $-4
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DC R0, 0,7,10,2 // CSW
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RETURN
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TEXT cachedinv(SB), 1, $-4
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MOVWU $0, R0
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_cachedinv:
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MOV LR, R29
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BL cachedsw<>(SB)
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TEXT dcisw(SB), 1, $-4
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DC R0, 0,7,6,2 // ISW
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RETURN
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TEXT cachedwbinv(SB), 1, $-4
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MOVWU $0, R0
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_cachedwbinv:
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MOV LR, R29
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BL cachedsw<>(SB)
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TEXT dccisw(SB), 1, $-4
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DC R0, 0,7,14,2 // CISW
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RETURN
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/*
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* l2 cache operations
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*/
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TEXT l2cacheuwb(SB), 1, $-4
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MOVWU $1, R0
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B _cachedwb
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TEXT l2cacheuinv(SB), 1, $-4
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MOVWU $1, R0
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B _cachedinv
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TEXT l2cacheuwbinv(SB), 1, $-4
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MOVWU $1, R0
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B _cachedwbinv
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TEXT cachesize(SB), 1, $-4
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MRS DAIF, R11
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MSR $0x2, DAIFSet
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MSR R0, CSSELR_EL1
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ISB $SY
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MRS CCSIDR_EL1, R0
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MSR R11, DAIF
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RETURN
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TEXT cachedsw<>(SB), 1, $-4
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MOV LR, R1
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MRS DAIF, R11
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MSR $0x2, DAIFSet
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ADDW R0, R0, R8
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MSR R8, CSSELR_EL1
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ISB $SY
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MRS CCSIDR_EL1, R4
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LSR $3, R4, R7
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ANDW $1023, R7 // lastway
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ADDW $1, R7, R5 // #ways
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LSR $13, R4, R2
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ANDW $32767, R2 // lastset
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ADDW $1, R2 // #sets
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ANDW $7, R4
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ADDW $4, R4 // log2(linelen)
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MOVWU $32, R3 // wayshift = 32 - log2(#ways)
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_countlog2ways:
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CBZ R7, _loop // lastway == 0?
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LSR $1, R7 // lastway >>= 1
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SUB $1, R3 // wayshift--
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B _countlog2ways
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_loop:
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DSB $SY
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ISB $SY
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_nextway:
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MOVWU $0, R6 // set
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_nextset:
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LSL R3, R7, R0 // way<<wayshift
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LSL R4, R6, R9 // set<<log2(linelen)
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ORRW R8, R0 // level
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ORRW R9, R0 // setway
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BL (R1) // op(setway)
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ADDW $1, R6 // set++
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CMPW R2, R6
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BLT _nextset
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ADDW $1, R7 // way++
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CMPW R5, R7
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BLT _nextway
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DSB $SY
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ISB $SY
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MSR R11, DAIF
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RET R29
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