1135 lines
22 KiB
C
1135 lines
22 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/error.h"
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typedef struct IOMap IOMap;
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struct IOMap
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{
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IOMap *next;
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int reserved;
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char tag[13];
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ulong start;
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ulong end;
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};
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static struct
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{
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Lock;
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IOMap *m;
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IOMap *free;
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IOMap maps[32]; /* some initial free maps */
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QLock ql; /* lock for reading map */
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} iomap;
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enum {
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Qdir = 0,
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Qioalloc = 1,
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Qiob,
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Qiow,
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Qiol,
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Qmsr,
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Qbase,
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Qmax = 16,
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};
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enum {
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CR4Osfxsr = 1 << 9,
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};
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enum { /* cpuid standard function codes */
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Highstdfunc = 0, /* also returns vendor string */
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Procsig,
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Proctlbcache,
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Procserial,
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};
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typedef long Rdwrfn(Chan*, void*, long, vlong);
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static Rdwrfn *readfn[Qmax];
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static Rdwrfn *writefn[Qmax];
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static Dirtab archdir[Qmax] = {
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".", { Qdir, 0, QTDIR }, 0, 0555,
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"ioalloc", { Qioalloc, 0 }, 0, 0444,
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"iob", { Qiob, 0 }, 0, 0660,
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"iow", { Qiow, 0 }, 0, 0660,
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"iol", { Qiol, 0 }, 0, 0660,
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"msr", { Qmsr, 0}, 0, 0660,
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};
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Lock archwlock; /* the lock is only for changing archdir */
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int narchdir = Qbase;
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int (*_pcmspecial)(char*, ISAConf*);
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void (*_pcmspecialclose)(int);
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static int doi8253set = 1;
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/*
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* Add a file to the #P listing. Once added, you can't delete it.
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* You can't add a file with the same name as one already there,
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* and you get a pointer to the Dirtab entry so you can do things
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* like change the Qid version. Changing the Qid path is disallowed.
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*/
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Dirtab*
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addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
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{
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int i;
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Dirtab d;
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Dirtab *dp;
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memset(&d, 0, sizeof d);
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strcpy(d.name, name);
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d.perm = perm;
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lock(&archwlock);
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if(narchdir >= Qmax){
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unlock(&archwlock);
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return nil;
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}
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for(i=0; i<narchdir; i++)
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if(strcmp(archdir[i].name, name) == 0){
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unlock(&archwlock);
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return nil;
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}
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d.qid.path = narchdir;
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archdir[narchdir] = d;
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readfn[narchdir] = rdfn;
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writefn[narchdir] = wrfn;
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dp = &archdir[narchdir++];
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unlock(&archwlock);
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return dp;
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}
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void
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ioinit(void)
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{
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char *excluded;
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int i;
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for(i = 0; i < nelem(iomap.maps)-1; i++)
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iomap.maps[i].next = &iomap.maps[i+1];
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iomap.maps[i].next = nil;
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iomap.free = iomap.maps;
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/*
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* This is necessary to make the IBM X20 boot.
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* Have not tracked down the reason.
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* i82557 is at 0x1000, the dummy entry is needed for swappable devs.
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*/
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ioalloc(0x0fff, 1, 0, "dummy");
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if ((excluded = getconf("ioexclude")) != nil) {
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char *s;
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s = excluded;
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while (s && *s != '\0' && *s != '\n') {
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char *ends;
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int io_s, io_e;
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io_s = (int)strtol(s, &ends, 0);
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if (ends == nil || ends == s || *ends != '-') {
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print("ioinit: cannot parse option string\n");
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break;
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}
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s = ++ends;
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io_e = (int)strtol(s, &ends, 0);
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if (ends && *ends == ',')
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*ends++ = '\0';
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s = ends;
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ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
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}
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}
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}
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/*
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* Reserve a range to be ioalloced later.
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* This is in particular useful for exchangable cards, such
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* as pcmcia and cardbus cards.
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*/
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int
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ioreserve(int, int size, int align, char *tag)
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{
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IOMap *m, **l;
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int i, port;
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lock(&iomap);
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/* find a free port above 0x400 and below 0x1000 */
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port = 0x400;
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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if (m->start < 0x400) continue;
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i = m->start - port;
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if(i > size)
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break;
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if(align > 0)
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port = ((port+align-1)/align)*align;
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else
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port = m->end;
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}
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if(*l == nil){
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unlock(&iomap);
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return -1;
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}
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m = iomap.free;
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if(m == nil){
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print("ioalloc: out of maps");
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unlock(&iomap);
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return port;
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}
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iomap.free = m->next;
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m->next = *l;
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m->start = port;
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m->end = port + size;
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m->reserved = 1;
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strncpy(m->tag, tag, sizeof(m->tag)-1);
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m->tag[sizeof(m->tag)-1] = 0;
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*l = m;
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archdir[0].qid.vers++;
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unlock(&iomap);
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return m->start;
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}
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/*
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* alloc some io port space and remember who it was
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* alloced to. if port < 0, find a free region.
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*/
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int
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ioalloc(int port, int size, int align, char *tag)
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{
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IOMap *m, **l;
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int i;
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lock(&iomap);
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if(port < 0){
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/* find a free port above 0x400 and below 0x1000 */
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port = 0x400;
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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if (m->start < 0x400) continue;
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i = m->start - port;
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if(i > size)
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break;
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if(align > 0)
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port = ((port+align-1)/align)*align;
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else
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port = m->end;
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}
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if(*l == nil){
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unlock(&iomap);
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return -1;
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}
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} else {
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/* Only 64KB I/O space on the x86. */
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if((port+size) > 0x10000){
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unlock(&iomap);
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return -1;
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}
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/* see if the space clashes with previously allocated ports */
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for(l = &iomap.m; *l; l = &(*l)->next){
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m = *l;
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if(m->end <= port)
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continue;
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if(m->reserved && m->start == port && m->end >= port + size) {
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m->reserved = 0;
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unlock(&iomap);
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return m->start;
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}
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if(m->start >= port+size)
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break;
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unlock(&iomap);
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return -1;
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}
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}
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m = iomap.free;
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if(m == nil){
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print("ioalloc: out of maps");
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unlock(&iomap);
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return port;
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}
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iomap.free = m->next;
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m->next = *l;
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m->start = port;
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m->end = port + size;
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strncpy(m->tag, tag, sizeof(m->tag)-1);
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m->tag[sizeof(m->tag)-1] = 0;
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*l = m;
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archdir[0].qid.vers++;
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unlock(&iomap);
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return m->start;
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}
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void
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iofree(int port)
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{
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IOMap *m, **l;
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lock(&iomap);
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for(l = &iomap.m; *l; l = &(*l)->next){
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if((*l)->start == port){
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m = *l;
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*l = m->next;
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m->next = iomap.free;
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iomap.free = m;
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break;
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}
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if((*l)->start > port)
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break;
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}
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archdir[0].qid.vers++;
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unlock(&iomap);
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}
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int
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iounused(int start, int end)
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{
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IOMap *m;
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for(m = iomap.m; m; m = m->next){
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if(start >= m->start && start < m->end
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|| start <= m->start && end > m->start)
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return 0;
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}
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return 1;
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}
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static void
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checkport(int start, int end)
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{
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/* standard vga regs are OK */
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if(start >= 0x2b0 && end <= 0x2df+1)
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return;
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if(start >= 0x3c0 && end <= 0x3da+1)
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return;
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if(iounused(start, end))
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return;
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error(Eperm);
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}
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static Chan*
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archattach(char* spec)
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{
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return devattach('P', spec);
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}
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Walkqid*
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archwalk(Chan* c, Chan *nc, char** name, int nname)
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{
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return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
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}
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static int
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archstat(Chan* c, uchar* dp, int n)
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{
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return devstat(c, dp, n, archdir, narchdir, devgen);
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}
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static Chan*
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archopen(Chan* c, int omode)
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{
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return devopen(c, omode, archdir, narchdir, devgen);
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}
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static void
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archclose(Chan*)
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{
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}
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enum
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{
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Linelen= 31,
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};
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static long
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archread(Chan *c, void *a, long n, vlong offset)
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{
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char *buf, *p;
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int port;
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ushort *sp;
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ulong *lp;
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vlong *vp;
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IOMap *m;
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Rdwrfn *fn;
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switch((ulong)c->qid.path){
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case Qdir:
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return devdirread(c, a, n, archdir, narchdir, devgen);
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case Qiob:
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port = offset;
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checkport(offset, offset+n);
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for(p = a; port < offset+n; port++)
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*p++ = inb(port);
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return n;
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case Qiow:
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if(n & 1)
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error(Ebadarg);
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checkport(offset, offset+n);
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sp = a;
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for(port = offset; port < offset+n; port += 2)
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*sp++ = ins(port);
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return n;
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case Qiol:
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if(n & 3)
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error(Ebadarg);
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checkport(offset, offset+n);
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lp = a;
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for(port = offset; port < offset+n; port += 4)
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*lp++ = inl(port);
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return n;
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case Qmsr:
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if(n & 7)
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error(Ebadarg);
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vp = a;
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for(port = offset; port < offset+n; port += 8)
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if(rdmsr(port, vp++) < 0)
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error(Ebadarg);
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return n;
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case Qioalloc:
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break;
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default:
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if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
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return fn(c, a, n, offset);
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error(Eperm);
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break;
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}
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if((buf = malloc(n)) == nil)
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error(Enomem);
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p = buf;
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n = n/Linelen;
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offset = offset/Linelen;
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lock(&iomap);
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for(m = iomap.m; n > 0 && m != nil; m = m->next){
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if(offset-- > 0)
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continue;
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sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
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p += Linelen;
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n--;
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}
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unlock(&iomap);
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n = p - buf;
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memmove(a, buf, n);
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free(buf);
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return n;
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}
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static long
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archwrite(Chan *c, void *a, long n, vlong offset)
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{
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char *p;
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int port;
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ushort *sp;
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ulong *lp;
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vlong *vp;
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Rdwrfn *fn;
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switch((ulong)c->qid.path){
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case Qiob:
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p = a;
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checkport(offset, offset+n);
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for(port = offset; port < offset+n; port++)
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outb(port, *p++);
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return n;
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case Qiow:
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if(n & 1)
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error(Ebadarg);
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checkport(offset, offset+n);
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sp = a;
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for(port = offset; port < offset+n; port += 2)
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outs(port, *sp++);
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return n;
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case Qiol:
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if(n & 3)
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error(Ebadarg);
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checkport(offset, offset+n);
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lp = a;
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for(port = offset; port < offset+n; port += 4)
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outl(port, *lp++);
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return n;
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case Qmsr:
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if(n & 7)
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error(Ebadarg);
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vp = a;
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for(port = offset; port < offset+n; port += 8)
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if(wrmsr(port, *vp++) < 0)
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error(Ebadarg);
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return n;
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default:
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if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
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return fn(c, a, n, offset);
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error(Eperm);
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break;
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}
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return 0;
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}
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|
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Dev archdevtab = {
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'P',
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"arch",
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devreset,
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devinit,
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devshutdown,
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archattach,
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archwalk,
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archstat,
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archopen,
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devcreate,
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archclose,
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archread,
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devbread,
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archwrite,
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devbwrite,
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devremove,
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devwstat,
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};
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|
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/*
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* the following is a generic version of the
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* architecture specific stuff
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*/
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|
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static int
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unimplemented(int)
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{
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return 0;
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}
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|
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static void
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nop(void)
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{
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}
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|
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static void
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archreset(void)
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{
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i8042reset();
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|
|
/*
|
|
* Often the BIOS hangs during restart if a conventional 8042
|
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* warm-boot sequence is tried. The following is Intel specific and
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* seems to perform a cold-boot, but at least it comes back.
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* And sometimes there is no keyboard...
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*
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* The reset register (0xcf9) is usually in one of the bridge
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* chips. The actual location and sequence could be extracted from
|
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* ACPI but why bother, this is the end of the line anyway.
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*/
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print("Takes a licking and keeps on ticking...\n");
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*(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
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outb(0xcf9, 0x02);
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outb(0xcf9, 0x06);
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|
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for(;;)
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idle();
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}
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|
|
/*
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* 386 has no compare-and-swap instruction.
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* Run it with interrupts turned off instead.
|
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*/
|
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static int
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cmpswap386(long *addr, long old, long new)
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{
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int r, s;
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|
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s = splhi();
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if(r = (*addr == old))
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*addr = new;
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splx(s);
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return r;
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}
|
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|
|
/*
|
|
* On a uniprocessor, you'd think that coherence could be nop,
|
|
* but it can't. We still need a barrier when using coherence() in
|
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* device drivers.
|
|
*
|
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* On VMware, it's safe (and a huge win) to set this to nop.
|
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* Aux/vmware does this via the #P/archctl file.
|
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*/
|
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void (*coherence)(void) = nop;
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|
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int (*cmpswap)(long*, long, long) = cmpswap386;
|
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|
|
PCArch* arch;
|
|
extern PCArch* knownarch[];
|
|
|
|
PCArch archgeneric = {
|
|
.id= "generic",
|
|
.ident= 0,
|
|
.reset= archreset,
|
|
.serialpower= unimplemented,
|
|
.modempower= unimplemented,
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|
|
.intrinit= i8259init,
|
|
.intrenable= i8259enable,
|
|
.intrvecno= i8259vecno,
|
|
.intrdisable= i8259disable,
|
|
.intron= i8259on,
|
|
.introff= i8259off,
|
|
|
|
.clockenable= i8253enable,
|
|
.fastclock= i8253read,
|
|
.timerset= i8253timerset,
|
|
};
|
|
|
|
typedef struct X86type X86type;
|
|
struct X86type {
|
|
int family;
|
|
int model;
|
|
int aalcycles;
|
|
char* name;
|
|
};
|
|
|
|
static X86type x86intel[] =
|
|
{
|
|
{ 4, 0, 22, "486DX", }, /* known chips */
|
|
{ 4, 1, 22, "486DX50", },
|
|
{ 4, 2, 22, "486SX", },
|
|
{ 4, 3, 22, "486DX2", },
|
|
{ 4, 4, 22, "486SL", },
|
|
{ 4, 5, 22, "486SX2", },
|
|
{ 4, 7, 22, "DX2WB", }, /* P24D */
|
|
{ 4, 8, 22, "DX4", }, /* P24C */
|
|
{ 4, 9, 22, "DX4WB", }, /* P24CT */
|
|
{ 5, 0, 23, "P5", },
|
|
{ 5, 1, 23, "P5", },
|
|
{ 5, 2, 23, "P54C", },
|
|
{ 5, 3, 23, "P24T", },
|
|
{ 5, 4, 23, "P55C MMX", },
|
|
{ 5, 7, 23, "P54C VRT", },
|
|
{ 6, 1, 16, "PentiumPro", },/* trial and error */
|
|
{ 6, 3, 16, "PentiumII", },
|
|
{ 6, 5, 16, "PentiumII/Xeon", },
|
|
{ 6, 6, 16, "Celeron", },
|
|
{ 6, 7, 16, "PentiumIII/Xeon", },
|
|
{ 6, 8, 16, "PentiumIII/Xeon", },
|
|
{ 6, 0xB, 16, "PentiumIII/Xeon", },
|
|
{ 6, 0xF, 16, "Xeon5000-series", },
|
|
{ 6, 0x16, 16, "Celeron", },
|
|
{ 6, 0x17, 16, "Core 2/Xeon", },
|
|
{ 6, 0x1A, 16, "Core i7/Xeon", },
|
|
{ 6, 0x1C, 16, "Atom", },
|
|
{ 6, 0x1D, 16, "Xeon MP", },
|
|
{ 0xF, 1, 16, "P4", }, /* P4 */
|
|
{ 0xF, 2, 16, "PentiumIV/Xeon", },
|
|
{ 0xF, 6, 16, "PentiumIV/Xeon", },
|
|
|
|
{ 3, -1, 32, "386", }, /* family defaults */
|
|
{ 4, -1, 22, "486", },
|
|
{ 5, -1, 23, "P5", },
|
|
{ 6, -1, 16, "P6", },
|
|
{ 0xF, -1, 16, "P4", }, /* P4 */
|
|
|
|
{ -1, -1, 16, "unknown", }, /* total default */
|
|
};
|
|
|
|
/*
|
|
* The AMD processors all implement the CPUID instruction.
|
|
* The later ones also return the processor name via functions
|
|
* 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
|
|
* and DX:
|
|
* K5 "AMD-K5(tm) Processor"
|
|
* K6 "AMD-K6tm w/ multimedia extensions"
|
|
* K6 3D "AMD-K6(tm) 3D processor"
|
|
* K6 3D+ ?
|
|
*/
|
|
static X86type x86amd[] =
|
|
{
|
|
{ 5, 0, 23, "AMD-K5", }, /* guesswork */
|
|
{ 5, 1, 23, "AMD-K5", }, /* guesswork */
|
|
{ 5, 2, 23, "AMD-K5", }, /* guesswork */
|
|
{ 5, 3, 23, "AMD-K5", }, /* guesswork */
|
|
{ 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
|
|
{ 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
|
|
{ 5, 6, 11, "AMD-K6", }, /* trial and error */
|
|
{ 5, 7, 11, "AMD-K6", }, /* trial and error */
|
|
{ 5, 8, 11, "AMD-K6-2", }, /* trial and error */
|
|
{ 5, 9, 11, "AMD-K6-III", },/* trial and error */
|
|
{ 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
|
|
|
|
{ 6, 1, 11, "AMD-Athlon", },/* trial and error */
|
|
{ 6, 2, 11, "AMD-Athlon", },/* trial and error */
|
|
|
|
{ 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
|
|
|
|
{ 4, -1, 22, "Am486", }, /* guesswork */
|
|
{ 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
|
|
{ 6, -1, 11, "AMD-Athlon", },/* guesswork */
|
|
{ 0xF, -1, 11, "AMD-K8", }, /* guesswork */
|
|
{ 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
|
|
|
|
{ -1, -1, 11, "unknown", }, /* total default */
|
|
};
|
|
|
|
/*
|
|
* WinChip 240MHz
|
|
*/
|
|
static X86type x86winchip[] =
|
|
{
|
|
{5, 4, 23, "Winchip",}, /* guesswork */
|
|
{6, 7, 23, "Via C3 Samuel 2 or Ezra",},
|
|
{6, 8, 23, "Via C3 Ezra-T",},
|
|
{6, 9, 23, "Via C3 Eden-N",},
|
|
{ -1, -1, 23, "unknown", }, /* total default */
|
|
};
|
|
|
|
/*
|
|
* SiS 55x
|
|
*/
|
|
static X86type x86sis[] =
|
|
{
|
|
{5, 0, 23, "SiS 55x",}, /* guesswork */
|
|
{ -1, -1, 23, "unknown", }, /* total default */
|
|
};
|
|
|
|
static X86type *cputype;
|
|
|
|
static void simplecycles(uvlong*);
|
|
void (*cycles)(uvlong*) = simplecycles;
|
|
void _cycles(uvlong*); /* in l.s */
|
|
|
|
static void
|
|
simplecycles(uvlong*x)
|
|
{
|
|
*x = m->ticks;
|
|
}
|
|
|
|
void
|
|
cpuidprint(void)
|
|
{
|
|
int i;
|
|
char buf[128];
|
|
|
|
i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
|
|
if(m->cpuidid[0])
|
|
i += sprint(buf+i, "%12.12s ", m->cpuidid);
|
|
seprint(buf+i, buf + sizeof buf - 1,
|
|
"%s (cpuid: AX 0x%4.4uX CX 0x%4.4uX DX 0x%4.4uX)\n",
|
|
m->cpuidtype, m->cpuidax, m->cpuidcx, m->cpuiddx);
|
|
print(buf);
|
|
}
|
|
|
|
/*
|
|
* figure out:
|
|
* - cpu type
|
|
* - whether or not we have a TSC (cycle counter)
|
|
* - whether or not it supports page size extensions
|
|
* (if so turn it on)
|
|
* - whether or not it supports machine check exceptions
|
|
* (if so turn it on)
|
|
* - whether or not it supports the page global flag
|
|
* (if so turn it on)
|
|
*/
|
|
int
|
|
cpuidentify(void)
|
|
{
|
|
char *p;
|
|
int family, model, nomce;
|
|
X86type *t, *tab;
|
|
uintptr cr4;
|
|
ulong regs[4];
|
|
vlong mca, mct;
|
|
|
|
cpuid(Highstdfunc, regs);
|
|
memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
|
|
memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
|
|
memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
|
|
m->cpuidid[12] = '\0';
|
|
|
|
cpuid(Procsig, regs);
|
|
m->cpuidax = regs[0];
|
|
m->cpuidcx = regs[2];
|
|
m->cpuiddx = regs[3];
|
|
|
|
if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
|
|
strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
|
|
tab = x86amd;
|
|
else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
|
|
tab = x86winchip;
|
|
else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
|
|
tab = x86sis;
|
|
else
|
|
tab = x86intel;
|
|
|
|
family = X86FAMILY(m->cpuidax);
|
|
model = X86MODEL(m->cpuidax);
|
|
for(t=tab; t->name; t++)
|
|
if((t->family == family && t->model == model)
|
|
|| (t->family == family && t->model == -1)
|
|
|| (t->family == -1))
|
|
break;
|
|
|
|
m->cpuidtype = t->name;
|
|
|
|
/*
|
|
* if there is one, set tsc to a known value
|
|
*/
|
|
if(m->cpuiddx & Tsc){
|
|
m->havetsc = 1;
|
|
cycles = _cycles;
|
|
if(m->cpuiddx & Cpumsr)
|
|
wrmsr(0x10, 0);
|
|
}
|
|
|
|
|
|
/*
|
|
* use i8253 to guess our cpu speed
|
|
*/
|
|
guesscpuhz(t->aalcycles);
|
|
|
|
/*
|
|
* If machine check exception, page size extensions or page global bit
|
|
* are supported enable them in CR4 and clear any other set extensions.
|
|
* If machine check was enabled clear out any lingering status.
|
|
*/
|
|
if(m->cpuiddx & (Pge|Mce|Pse)){
|
|
cr4 = getcr4();
|
|
if(m->cpuiddx & Pse)
|
|
cr4 |= 0x10; /* page size extensions */
|
|
if(p = getconf("*nomce"))
|
|
nomce = strtoul(p, 0, 0);
|
|
else
|
|
nomce = 0;
|
|
if((m->cpuiddx & Mce) && !nomce){
|
|
cr4 |= 0x40; /* machine check enable */
|
|
if(family == 5){
|
|
rdmsr(0x00, &mca);
|
|
rdmsr(0x01, &mct);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Detect whether the chip supports the global bit
|
|
* in page directory and page table entries. When set
|
|
* in a particular entry, it means ``don't bother removing
|
|
* this from the TLB when CR3 changes.''
|
|
*
|
|
* We flag all kernel pages with this bit. Doing so lessens the
|
|
* overhead of switching processes on bare hardware,
|
|
* even more so on VMware. See mmu.c:/^memglobal.
|
|
*
|
|
* For future reference, should we ever need to do a
|
|
* full TLB flush, it can be accomplished by clearing
|
|
* the PGE bit in CR4, writing to CR3, and then
|
|
* restoring the PGE bit.
|
|
*/
|
|
if(m->cpuiddx & Pge){
|
|
cr4 |= 0x80; /* page global enable bit */
|
|
m->havepge = 1;
|
|
}
|
|
|
|
putcr4(cr4);
|
|
|
|
if(m->cpuiddx & Mce)
|
|
rdmsr(0x01, &mct);
|
|
}
|
|
|
|
if(m->cpuiddx & Fxsr){ /* have sse fp? */
|
|
fpsave = fpssesave;
|
|
fprestore = fpsserestore;
|
|
putcr4(getcr4() | CR4Osfxsr);
|
|
} else {
|
|
fpsave = fpx87save;
|
|
fprestore = fpx87restore;
|
|
}
|
|
|
|
cputype = t;
|
|
return t->family;
|
|
}
|
|
|
|
static long
|
|
cputyperead(Chan*, void *a, long n, vlong offset)
|
|
{
|
|
char str[32];
|
|
ulong mhz;
|
|
|
|
mhz = (m->cpuhz+999999)/1000000;
|
|
|
|
snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
|
|
return readstr(offset, a, n, str);
|
|
}
|
|
|
|
static long
|
|
archctlread(Chan*, void *a, long nn, vlong offset)
|
|
{
|
|
int n;
|
|
char *buf, *p, *ep;
|
|
|
|
p = buf = smalloc(READSTR);
|
|
ep = p + READSTR;
|
|
p = seprint(p, ep, "cpu %s %lud%s\n",
|
|
cputype->name, (ulong)(m->cpuhz+999999)/1000000,
|
|
m->havepge ? " pge" : "");
|
|
p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
|
|
p = seprint(p, ep, "coherence ");
|
|
if(coherence == mb386)
|
|
p = seprint(p, ep, "mb386\n");
|
|
else if(coherence == mb586)
|
|
p = seprint(p, ep, "mb586\n");
|
|
else if(coherence == mfence)
|
|
p = seprint(p, ep, "mfence\n");
|
|
else if(coherence == nop)
|
|
p = seprint(p, ep, "nop\n");
|
|
else
|
|
p = seprint(p, ep, "0x%p\n", coherence);
|
|
p = seprint(p, ep, "cmpswap ");
|
|
if(cmpswap == cmpswap386)
|
|
p = seprint(p, ep, "cmpswap386\n");
|
|
else if(cmpswap == cmpswap486)
|
|
p = seprint(p, ep, "cmpswap486\n");
|
|
else
|
|
p = seprint(p, ep, "0x%p\n", cmpswap);
|
|
p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
|
|
n = p - buf;
|
|
n += mtrrprint(p, ep - p);
|
|
buf[n] = '\0';
|
|
|
|
n = readstr(offset, a, nn, buf);
|
|
free(buf);
|
|
return n;
|
|
}
|
|
|
|
enum
|
|
{
|
|
CMpge,
|
|
CMcoherence,
|
|
CMi8253set,
|
|
CMcache,
|
|
};
|
|
|
|
static Cmdtab archctlmsg[] =
|
|
{
|
|
CMpge, "pge", 2,
|
|
CMcoherence, "coherence", 2,
|
|
CMi8253set, "i8253set", 2,
|
|
CMcache, "cache", 4,
|
|
};
|
|
|
|
static long
|
|
archctlwrite(Chan*, void *a, long n, vlong)
|
|
{
|
|
uvlong base, size;
|
|
Cmdbuf *cb;
|
|
Cmdtab *ct;
|
|
char *ep;
|
|
|
|
cb = parsecmd(a, n);
|
|
if(waserror()){
|
|
free(cb);
|
|
nexterror();
|
|
}
|
|
ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
|
|
switch(ct->index){
|
|
case CMpge:
|
|
if(!m->havepge)
|
|
error("processor does not support pge");
|
|
if(strcmp(cb->f[1], "on") == 0)
|
|
putcr4(getcr4() | 0x80);
|
|
else if(strcmp(cb->f[1], "off") == 0)
|
|
putcr4(getcr4() & ~0x80);
|
|
else
|
|
cmderror(cb, "invalid pge ctl");
|
|
break;
|
|
case CMcoherence:
|
|
if(strcmp(cb->f[1], "mb386") == 0)
|
|
coherence = mb386;
|
|
else if(strcmp(cb->f[1], "mb586") == 0){
|
|
if(X86FAMILY(m->cpuidax) < 5)
|
|
error("invalid coherence ctl on this cpu family");
|
|
coherence = mb586;
|
|
}else if(strcmp(cb->f[1], "mfence") == 0){
|
|
if((m->cpuiddx & Sse2) == 0)
|
|
error("invalid coherence ctl on this cpu family");
|
|
coherence = mfence;
|
|
}else if(strcmp(cb->f[1], "nop") == 0){
|
|
/* only safe on vmware */
|
|
if(conf.nmach > 1)
|
|
error("cannot disable coherence on a multiprocessor");
|
|
coherence = nop;
|
|
}else
|
|
cmderror(cb, "invalid coherence ctl");
|
|
break;
|
|
case CMi8253set:
|
|
if(strcmp(cb->f[1], "on") == 0)
|
|
doi8253set = 1;
|
|
else if(strcmp(cb->f[1], "off") == 0){
|
|
doi8253set = 0;
|
|
(*arch->timerset)(0);
|
|
}else
|
|
cmderror(cb, "invalid i2853set ctl");
|
|
break;
|
|
case CMcache:
|
|
base = strtoull(cb->f[1], &ep, 0);
|
|
if(*ep)
|
|
error("cache: parse error: base not a number?");
|
|
size = strtoull(cb->f[2], &ep, 0);
|
|
if(*ep)
|
|
error("cache: parse error: size not a number?");
|
|
mtrr(base, size, cb->f[3]);
|
|
break;
|
|
}
|
|
free(cb);
|
|
poperror();
|
|
return n;
|
|
}
|
|
|
|
static long
|
|
rmemrw(int isr, void *a, long n, vlong off)
|
|
{
|
|
if(off < 0 || n < 0)
|
|
error("bad offset/count");
|
|
if(isr){
|
|
if(off >= MB)
|
|
return 0;
|
|
if(off+n >= MB)
|
|
n = MB - off;
|
|
memmove(a, KADDR((ulong)off), n);
|
|
}else{
|
|
/* allow vga framebuf's access */
|
|
if(off >= MB || off+n > MB ||
|
|
(off < 0xA0000 || off+n > 0xB0000+0x10000))
|
|
error("bad offset/count in write");
|
|
memmove(KADDR((ulong)off), a, n);
|
|
}
|
|
return n;
|
|
}
|
|
|
|
static long
|
|
rmemread(Chan*, void *a, long n, vlong off)
|
|
{
|
|
return rmemrw(1, a, n, off);
|
|
}
|
|
|
|
static long
|
|
rmemwrite(Chan*, void *a, long n, vlong off)
|
|
{
|
|
return rmemrw(0, a, n, off);
|
|
}
|
|
|
|
void
|
|
archinit(void)
|
|
{
|
|
PCArch **p;
|
|
|
|
arch = 0;
|
|
for(p = knownarch; *p; p++){
|
|
if((*p)->ident && (*p)->ident() == 0){
|
|
arch = *p;
|
|
break;
|
|
}
|
|
}
|
|
if(arch == 0)
|
|
arch = &archgeneric;
|
|
else{
|
|
if(arch->id == 0)
|
|
arch->id = archgeneric.id;
|
|
if(arch->reset == 0)
|
|
arch->reset = archgeneric.reset;
|
|
if(arch->serialpower == 0)
|
|
arch->serialpower = archgeneric.serialpower;
|
|
if(arch->modempower == 0)
|
|
arch->modempower = archgeneric.modempower;
|
|
if(arch->intrinit == 0)
|
|
arch->intrinit = archgeneric.intrinit;
|
|
if(arch->intrenable == 0)
|
|
arch->intrenable = archgeneric.intrenable;
|
|
}
|
|
|
|
/*
|
|
* Decide whether to use copy-on-reference (386 and mp).
|
|
* We get another chance to set it in mpinit() for a
|
|
* multiprocessor.
|
|
*/
|
|
if(X86FAMILY(m->cpuidax) == 3)
|
|
conf.copymode = 1;
|
|
|
|
if(X86FAMILY(m->cpuidax) >= 4)
|
|
cmpswap = cmpswap486;
|
|
|
|
if(X86FAMILY(m->cpuidax) >= 5)
|
|
coherence = mb586;
|
|
|
|
if(m->cpuiddx & Sse2)
|
|
coherence = mfence;
|
|
|
|
addarchfile("cputype", 0444, cputyperead, nil);
|
|
addarchfile("archctl", 0664, archctlread, archctlwrite);
|
|
addarchfile("realmodemem", 0660, rmemread, rmemwrite);
|
|
}
|
|
|
|
/*
|
|
* call either the pcmcia or pccard device setup
|
|
*/
|
|
int
|
|
pcmspecial(char *idstr, ISAConf *isa)
|
|
{
|
|
return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
|
|
}
|
|
|
|
/*
|
|
* call either the pcmcia or pccard device teardown
|
|
*/
|
|
void
|
|
pcmspecialclose(int a)
|
|
{
|
|
if (_pcmspecialclose != nil)
|
|
_pcmspecialclose(a);
|
|
}
|
|
|
|
/*
|
|
* return value and speed of timer set in arch->clockenable
|
|
*/
|
|
uvlong
|
|
fastticks(uvlong *hz)
|
|
{
|
|
return (*arch->fastclock)(hz);
|
|
}
|
|
|
|
ulong
|
|
µs(void)
|
|
{
|
|
return fastticks2us((*arch->fastclock)(nil));
|
|
}
|
|
|
|
/*
|
|
* set next timer interrupt
|
|
*/
|
|
void
|
|
timerset(Tval x)
|
|
{
|
|
if(doi8253set)
|
|
(*arch->timerset)(x);
|
|
}
|