28 lines
641 B
Plaintext
28 lines
641 B
Plaintext
units
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branch
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integer
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floating point
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on 601
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issue at most one per unit per cycle
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eight entry instruction queue
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can fill queue from cache in one clock cycle
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loads from requested address to end of cache block
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pipeline
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prefetch
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includes ins. cache access cycles
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decode
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execute
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writeback
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fpu
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IQ[3210] → fpu buffer/decode [≥1 cycle] → execute 1 → execute 2 → writeback
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iu
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IQ0/decode → buffer [if exec busy] → execute [hold for dependency] →
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circulate in load/store
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writeback
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bpu
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IQ[3210] → decode/execute → writeback
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notes
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address calculation must complete before stored value enters write buffer
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