2030 lines
32 KiB
C
2030 lines
32 KiB
C
#include <u.h>
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#include <libc.h>
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#include <bio.h>
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#include <mach.h>
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#define Extern extern
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#include "power.h"
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void add(ulong);
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void addc(ulong);
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void adde(ulong);
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void addme(ulong);
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void addze(ulong);
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void and(ulong);
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void andc(ulong);
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void cmp(ulong);
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void cmpl(ulong);
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void cntlzw(ulong);
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void dcbf(ulong);
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void dcbi(ulong);
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void dcbst(ulong);
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void dcbt(ulong);
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void dcbtst(ulong);
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void dcbz(ulong);
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void divw(ulong);
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void divwu(ulong);
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void eciwx(ulong);
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void ecowx(ulong);
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void eieio(ulong);
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void eqv(ulong);
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void extsb(ulong);
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void extsh(ulong);
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void icbi(ulong);
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void lbzx(ulong);
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void lfdx(ulong);
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void lfsx(ulong);
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void lhax(ulong);
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void lhbrx(ulong);
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void lhzx(ulong);
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void lswi(ulong);
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void lswx(ulong);
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void lwarx(ulong);
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void lwbrx(ulong);
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void lwzx(ulong);
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void mcrxr(ulong);
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void mfcr(ulong);
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void mfmsr(ulong);
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void mfpmr(ulong);
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void mfspr(ulong);
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void mfsr(ulong);
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void mfsrin(ulong);
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void mftb(ulong);
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void mftbu(ulong);
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void mspr(ulong);
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void mtcrf(ulong);
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void mtmsr(ulong);
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void mtpmr(ulong);
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void mtspr(ulong);
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void mtsr(ulong);
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void mtsrin(ulong);
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void mttb(ulong);
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void mttbu(ulong);
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void mulhw(ulong);
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void mulhwu(ulong);
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void mullw(ulong);
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void nand(ulong);
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void neg(ulong);
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void nor(ulong);
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void or(ulong);
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void orc(ulong);
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void slbia(ulong);
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void slbia(ulong);
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void slw(ulong);
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void sraw(ulong);
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void srawi(ulong);
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void srw(ulong);
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void stbx(ulong);
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void stfdx(ulong);
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void stfiwx(ulong);
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void stfsx(ulong);
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void sthbrx(ulong);
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void sthx(ulong);
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void stswi(ulong);
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void stswx(ulong);
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void stwbrx(ulong);
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void stwcx(ulong);
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void stwx(ulong);
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void subf(ulong);
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void subfc(ulong);
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void subfe(ulong);
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void subfme(ulong);
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void subfze(ulong);
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void sync(ulong);
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void tlbie(ulong);
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void tw(ulong);
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void xor(ulong);
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Inst op31[] = {
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[0] {cmp, "cmp", Iarith},
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[4] {tw, "tw", Iarith},
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[8] {subfc, "subfc", Iarith},
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[10] {addc, "addc", Iarith},
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[11] {mulhwu, "mulhwu", Iarith},
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[19] {mfcr, "mfcr", Iarith},
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[20] {lwarx, "lwarx", Iload},
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[23] {lwzx, "lwzx", Iload},
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[24] {slw, "slw", Ilog},
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[26] {cntlzw, "cntlzw", Ilog},
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[28] {and, "and", Ilog},
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[32] {cmpl, "cmpl", Iarith},
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[40] {subf, "subf", Iarith},
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[54] {dcbst, "dcbst", Icontrol},
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[55] {lwzx, "lwzux", Iload},
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[60] {andc, "andc", Ilog},
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[75] {mulhw, "mulhw", Iarith},
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[83] {0, "mfmsr", Icontrol},
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[86] {dcbf, "dcbf", Icontrol},
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[87] {lbzx, "lbzx", Iload},
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[104] {neg, "neg", Iarith},
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[115] {0, "mfpmr", Iarith},
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[119] {lbzx, "lbzux", Iload},
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[124] {nor, "nor", Iarith},
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[136] {subfe, "subfe", Iarith},
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[138] {adde, "adde", Iarith},
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[144] {mtcrf, "mtcrf", Ireg},
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[146] {0, "mtmsr", Icontrol},
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[150] {stwcx, "stwcx.", Istore},
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[151] {stwx, "stwx", Istore},
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[178] {0, "mtpmr", Icontrol},
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[183] {stwx, "stwux", Istore},
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[200] {subfze, "subfze", Iarith},
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[202] {addze, "addze", Iarith},
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[210] {0, "mtsr", Ireg},
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[215] {stbx, "stbx", Istore},
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[232] {subfme, "subfme", Iarith},
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[234] {addme, "addme", Iarith},
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[235] {mullw, "mullw", Iarith},
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[242] {0, "mtsrin", Ireg},
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[246] {dcbtst, "dcbtst", Icontrol},
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[247] {stbx, "stbux", Istore},
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[266] {add, "add", Iarith},
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[275] {0, "mftb", Icontrol},
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[278] {dcbt, "dcbt", Icontrol},
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[279] {lhzx, "lhzx", Iload},
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[284] {eqv, "eqv", Ilog},
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[306] {0, "tlbie", Icontrol},
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[307] {0, "mftbu", Icontrol},
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[310] {0, "eciwx", Icontrol},
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[311] {lhzx, "lhzux", Iload},
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[316] {xor, "xor", Ilog},
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[339] {mspr, "mfspr", Ireg},
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[343] {lhax, "lhax", Iload},
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[375] {lhax, "lhaux", Iload},
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[403] {0, "mttb", Icontrol},
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[407] {sthx, "sthx", Istore},
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[412] {orc, "orc", Ilog},
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[434] {0, "slbia", Iarith},
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[435] {0, "mttbu", Icontrol},
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[438] {0, "ecowx", Icontrol},
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[439] {sthx, "sthux", Istore},
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[444] {or, "or", Ilog},
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[459] {divwu, "divwu", Iarith},
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[467] {mspr, "mtspr", Ireg},
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[470] {0, "dcbi", Icontrol},
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[476] {nand, "nand", Ilog},
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[491] {divw, "divw", Iarith},
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[498] {0, "slbia", Icontrol},
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[512] {mcrxr, "mcrxr", Ireg},
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[533] {lswx, "lswx", Iload},
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[534] {lwbrx, "lwbrx", Iload},
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[535] {lfsx, "lfsx", Ifloat},
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[536] {srw, "srw", Ilog},
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[567] {lfsx, "lfsux", Ifloat},
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[595] {0, "mfsr", Iarith},
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[597] {lswi, "lswi", Iarith},
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[598] {sync, "sync", Iarith},
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[599] {lfdx, "lfdx", Ifloat},
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[631] {lfdx, "lfdux", Ifloat},
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[659] {0, "mfsrin", Ireg},
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[661] {stswx, "stswx", Istore},
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[662] {stwbrx, "stwbrx", Istore},
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[663] {stfsx, "stfsx", Istore},
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[695] {stfsx, "stfsux", Istore},
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[725] {stswi, "stswi", Istore},
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[727] {stfdx, "stfdx", Istore},
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[759] {stfdx, "stfdux", Istore},
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[790] {lhbrx, "lhbrx", Iload},
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[792] {sraw, "sraw", Ilog},
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[824] {srawi, "srawi", Ilog},
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[854] {0, "eieio", Icontrol},
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[918] {sthbrx, "sthbrx", Istore},
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[922] {extsh, "extsh", Iarith},
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[954] {extsb, "extsb", Iarith},
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[982] {icbi, "icbi", Icontrol},
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[983] {unimp, "stfiwx", Istore},
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[1014] {dcbz, "dcbz", Icontrol},
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};
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Inset ops31 = {op31, nelem(op31)};
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void
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mspr(ulong ir)
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{
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int rd, ra, rb;
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ulong *d;
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char *n;
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char buf[20];
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getarrr(ir);
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switch((rb<<5) | ra) {
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case 0:
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undef(ir); /* was mq */
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return;
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case 1:
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d = ®.xer; n = "xer";
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break;
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case 268:
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case 284:
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d = ®.tbl; n = "tbl";
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break;
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case 269:
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case 285:
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d = ®.tbu; n = "tbu";
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break;
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case 22:
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d = ®.dec; n = "dec";
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break;
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case 8:
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d = ®.lr; n = "lr";
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break;
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case 9:
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d = ®.ctr; n = "ctr";
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break;
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default:
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d = 0; sprint(n = buf, "spr%d", rd);
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break;
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}
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if(getxo(ir) == 339) {
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if(trace)
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itrace("%s\tr%d,%s", ci->name, rd, n);
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if(d != nil)
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reg.r[rd] = *d;
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} else {
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if(trace)
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itrace("%s\t%s,r%d", ci->name, n, rd);
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if(d != nil)
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*d = reg.r[rd];
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}
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}
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static void
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setcr(int d, long r)
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{
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int c;
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c = 0;
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if(reg.xer & XER_SO)
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c |= 1;
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if(r == 0)
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c |= 2;
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else if(r > 0)
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c |= 4;
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else
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c |= 8;
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reg.cr = (reg.cr & ~mkCR(d, 0xF)) | mkCR(d, c);
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}
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void
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addi(ulong ir)
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{
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int rd, ra;
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long imm;
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getairr(ir);
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if(trace) {
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if(ra)
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itrace("%s\tr%d,r%d,$0x%lux", ci->name, rd, ra, imm);
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else
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itrace("li\tr%d,$0x%lux", rd, imm);
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}
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if(ra)
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imm += reg.r[ra];
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reg.r[rd] = imm;
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}
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void
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addis(ulong ir)
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{
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int rd, ra;
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long imm;
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getairr(ir);
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if(trace) {
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if(ra)
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itrace("%s\tr%d,r%d,$0x%lux", ci->name, rd, ra, imm);
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else
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itrace("lis\tr%d,$0x%lux", rd, imm);
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}
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imm <<= 16;
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if(ra)
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imm += reg.r[ra];
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reg.r[rd] = imm;
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}
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void
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and(ulong ir)
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{
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int rs, ra, rb;
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getlrrr(ir);
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reg.r[ra] = reg.r[rs] & reg.r[rb];
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if(trace)
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itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
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if(ir & 1)
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setcr(0, reg.r[ra]);
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}
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void
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andc(ulong ir)
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{
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int rs, ra, rb;
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getlrrr(ir);
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reg.r[ra] = reg.r[rs] & ~reg.r[rb];
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if(trace)
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itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
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if(ir & 1)
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setcr(0, reg.r[ra]);
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}
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void
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andicc(ulong ir)
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{
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int rs, ra;
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ulong imm;
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getlirr(ir);
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reg.r[ra] = reg.r[rs] & imm;
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if(trace)
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itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
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setcr(0, reg.r[ra]);
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}
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void
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andiscc(ulong ir)
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{
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int rs, ra;
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ulong imm;
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getlirr(ir);
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reg.r[ra] = reg.r[rs] & (imm<<16);
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if(trace)
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itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
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setcr(0, reg.r[ra]);
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}
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void
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cmpli(ulong ir)
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{
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int rd, ra;
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ulong c;
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ulong imm, v;
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getairr(ir);
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imm &= 0xFFFF;
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if(rd & 3)
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undef(ir);
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rd >>= 2;
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v = reg.r[ra];
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c = 0;
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if(reg.xer & XER_SO)
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c |= CRSO;
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if(v < imm)
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c |= CRLT;
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else if(v == imm)
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c |= CREQ;
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else
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c |= CRGT;
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c >>= 28;
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reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
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if(trace)
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itrace("%s\tcrf%d,r%d,0x%lux [cr=#%x]", ci->name, rd, ra, imm, c);
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}
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void
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cmp(ulong ir)
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{
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int rd, ra, rb;
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ulong c;
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long va, vb;
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getarrr(ir);
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if(rd & 3)
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undef(ir);
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rd >>= 2;
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c = 0;
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if(reg.xer & XER_SO)
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c |= CRSO;
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va = reg.r[ra];
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vb = reg.r[rb];
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if(va < vb)
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c |= CRLT;
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else if(va == vb)
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c |= CREQ;
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else
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c |= CRGT;
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c >>= 28;
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reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
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if(trace)
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itrace("%s\tcrf%d,r%d,r%d [cr=#%x]", ci->name, rd, ra, rb, c);
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}
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void
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cmpi(ulong ir)
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{
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int rd, ra;
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ulong c;
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long imm, v;
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getairr(ir);
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if(rd & 3)
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undef(ir);
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rd >>= 2;
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v = reg.r[ra];
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c = 0;
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if(reg.xer & XER_SO)
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c |= CRSO;
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if(v < imm)
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c |= CRLT;
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else if(v == imm)
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c |= CREQ;
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else
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c |= CRGT;
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c >>= 28;
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reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
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if(trace)
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itrace("%s\tcrf%d,r%d,0x%lux [cr=#%x]", ci->name, rd, ra, imm, c);
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}
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void
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cmpl(ulong ir)
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{
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int rd, ra, rb;
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ulong c;
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ulong va, vb;
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getarrr(ir);
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if(rd & 3)
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undef(ir);
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rd >>= 2;
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c = 0;
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if(reg.xer & XER_SO)
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c |= CRSO;
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va = reg.r[ra];
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vb = reg.r[rb];
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if(va < vb)
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c |= CRLT;
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else if(va == vb)
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c |= CREQ;
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else
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c |= CRGT;
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c >>= 28;
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reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
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if(trace)
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itrace("%s\tcrf%d,r%d,r%d [cr=#%x]", ci->name, rd, ra, rb, c);
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}
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void
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cntlzw(ulong ir)
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{
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int rs, ra, rb, n;
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getlrrr(ir);
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if(rb)
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undef(ir);
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for(n=0; n<32 && (reg.r[rs] & (1L<<(31-n))) == 0; n++)
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;
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reg.r[ra] = n;
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if(trace)
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itrace("%s%s\tr%d,r%d", ci->name, ir&1?".":"", ra, rs);
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if(ir & 1)
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setcr(0, reg.r[ra]);
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}
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void
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eqv(ulong ir)
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{
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int rs, ra, rb;
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getlrrr(ir);
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reg.r[ra] = ~(reg.r[rs] ^ reg.r[rb]);
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if(trace)
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itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
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if(ir & 1)
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setcr(0, reg.r[ra]);
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}
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void
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extsb(ulong ir)
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{
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int rs, ra, rb;
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getlrrr(ir);
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if(rb)
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undef(ir);
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reg.r[ra] = (schar)reg.r[rs];
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d", ci->name, ir&1?".":"", ra, rs);
|
|
if(ir & 1)
|
|
setcr(0, reg.r[ra]);
|
|
}
|
|
|
|
void
|
|
extsh(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
|
|
getlrrr(ir);
|
|
if(rb)
|
|
undef(ir);
|
|
reg.r[ra] = (short)reg.r[rs];
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d", ci->name, ir&1?".":"", ra, rs);
|
|
if(ir & 1)
|
|
setcr(0, reg.r[ra]);
|
|
}
|
|
|
|
void
|
|
add(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)reg.r[rb];
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(r >> 16)
|
|
reg.xer |= XER_SO | XER_OV; /* TO DO: rubbish */
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
addc(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)reg.r[rb];
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
adde(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)reg.r[rb] + ((reg.xer&XER_CA)!=0);
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
addic(ulong ir)
|
|
{
|
|
int rd, ra;
|
|
long imm;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getairr(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)imm;
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
reg.r[rd] = (ulong)r;
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
|
|
}
|
|
|
|
void
|
|
addiccc(ulong ir)
|
|
{
|
|
int rd, ra;
|
|
long imm;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getairr(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)imm;
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
reg.r[rd] = (ulong)r;
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
|
|
}
|
|
|
|
void
|
|
addme(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
if(rb)
|
|
undef(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + (uvlong)0xFFFFFFFFU + ((reg.xer&XER_CA)!=0);
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
|
|
}
|
|
|
|
void
|
|
addze(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
if(rb)
|
|
undef(ir);
|
|
r = (uvlong)(ulong)reg.r[ra] + ((reg.xer&XER_CA)!=0);
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
|
|
}
|
|
|
|
void
|
|
divw(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
if(reg.r[rb] != 0 && ((ulong)reg.r[ra] != 0x80000000 || reg.r[rb] != -1))
|
|
reg.r[rd] = reg.r[ra]/reg.r[rb];
|
|
else if(ir & OE)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
divwu(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
if(reg.r[rb] != 0)
|
|
reg.r[rd] = (ulong)reg.r[ra]/(ulong)reg.r[rb];
|
|
else if(ir & OE)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
mcrxr(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
if(rd & 3 || ra != 0 || rb != 0 || ir & Rc)
|
|
undef(ir);
|
|
rd >>= 2;
|
|
reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, reg.xer>>28);
|
|
reg.xer &= ~(0xF<<28);
|
|
}
|
|
|
|
void
|
|
mtcrf(ulong ir)
|
|
{
|
|
int rs, crm, i;
|
|
ulong m;
|
|
|
|
if(ir & ((1<<20)|(1<<11)|Rc))
|
|
undef(ir);
|
|
rs = (ir>>21)&0x1F;
|
|
crm = (ir>>12)&0xFF;
|
|
m = 0;
|
|
for(i = 0x80; i; i >>= 1) {
|
|
m <<= 4;
|
|
if(crm & i)
|
|
m |= 0xF;
|
|
}
|
|
reg.cr = (reg.cr & ~m) | (reg.r[rs] & m);
|
|
}
|
|
|
|
void
|
|
mfcr(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
if(ra != 0 || rb != 0 || ir & Rc)
|
|
undef(ir);
|
|
reg.r[rd] = reg.cr;
|
|
}
|
|
|
|
void
|
|
mulhw(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
reg.r[rd] = ((vlong)(long)reg.r[ra]*(long)reg.r[rb])>>32;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
|
|
/* BUG: doesn't set OV */
|
|
}
|
|
|
|
void
|
|
mulhwu(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
reg.r[rd] = ((uvlong)(ulong)reg.r[ra]*(ulong)reg.r[rb])>>32;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]); /* not sure whether CR setting is signed or unsigned */
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
|
|
/* BUG: doesn't set OV */
|
|
}
|
|
|
|
void
|
|
mullw(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
reg.r[rd] = (uvlong)(ulong)reg.r[ra]*(ulong)reg.r[rb];
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
|
|
/* BUG: doesn't set OV */
|
|
}
|
|
|
|
void
|
|
mulli(ulong ir)
|
|
{
|
|
int rd, ra;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
reg.r[rd] = (uvlong)(ulong)reg.r[ra]*(ulong)imm;
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
|
|
}
|
|
|
|
void
|
|
nand(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
|
|
getlrrr(ir);
|
|
reg.r[ra] = ~(reg.r[rs] & reg.r[rb]);
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
neg(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
getarrr(ir);
|
|
if(rb)
|
|
undef(ir);
|
|
if(ir & OE)
|
|
reg.xer &= ~XER_OV;
|
|
if((ulong)reg.r[ra] == 0x80000000) {
|
|
if(ir & OE)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
reg.r[rd] = reg.r[ra];
|
|
} else
|
|
reg.r[rd] = -reg.r[ra];
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
}
|
|
|
|
void
|
|
nor(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
|
|
getlrrr(ir);
|
|
reg.r[ra] = ~(reg.r[rs] | reg.r[rb]);
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
or(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
|
|
getlrrr(ir);
|
|
reg.r[ra] = reg.r[rs] | reg.r[rb];
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace) {
|
|
if(rs == rb)
|
|
itrace("mr%s\tr%d,r%d", ir&1?".":"", ra, rs);
|
|
else
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
}
|
|
|
|
void
|
|
orc(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
|
|
getlrrr(ir);
|
|
reg.r[ra] = reg.r[rs] | ~reg.r[rb];
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
ori(ulong ir)
|
|
{
|
|
int rs, ra;
|
|
ulong imm;
|
|
|
|
getlirr(ir);
|
|
reg.r[ra] = reg.r[rs] | imm;
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
|
|
}
|
|
|
|
void
|
|
oris(ulong ir)
|
|
{
|
|
int rs, ra;
|
|
ulong imm;
|
|
|
|
getlirr(ir);
|
|
reg.r[ra] = reg.r[rs] | (imm<<16);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
|
|
}
|
|
|
|
static ulong
|
|
mkmask(int mb, int me)
|
|
{
|
|
int i;
|
|
ulong v;
|
|
|
|
if(mb > me)
|
|
return mkmask(0, me) | mkmask(mb, 31);
|
|
v = 0;
|
|
for(i=mb; i<=me; i++)
|
|
v |= 1L << (31-i); /* don't need a loop, but i'm lazy */
|
|
return v;
|
|
}
|
|
|
|
static ulong
|
|
rotl(ulong v, int sh)
|
|
{
|
|
if(sh == 0)
|
|
return v;
|
|
return (v<<sh) | (v>>(32-sh));
|
|
}
|
|
|
|
void
|
|
rlwimi(ulong ir)
|
|
{
|
|
int rs, ra, rb, sh;
|
|
ulong m;
|
|
|
|
getlrrr(ir);
|
|
sh = rb;
|
|
m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
|
|
reg.r[ra] = (reg.r[ra] & ~m) | (rotl(reg.r[rs], sh) & m);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,%d,#%lux", ci->name, ra, rs, sh, m);
|
|
if(ir & 1)
|
|
setcr(0, reg.r[ra]);
|
|
}
|
|
|
|
void
|
|
rlwinm(ulong ir)
|
|
{
|
|
int rs, ra, rb, sh;
|
|
ulong m;
|
|
|
|
getlrrr(ir);
|
|
sh = rb;
|
|
m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
|
|
reg.r[ra] = rotl(reg.r[rs], sh) & m;
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,%d,#%lux", ci->name, ir&Rc?".":"", ra, rs, sh, m);
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
}
|
|
|
|
void
|
|
rlwnm(ulong ir)
|
|
{
|
|
int rs, ra, rb, sh;
|
|
ulong m;
|
|
|
|
getlrrr(ir);
|
|
sh = reg.r[rb] & 0x1F;
|
|
m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
|
|
reg.r[ra] = rotl(reg.r[rs], sh) & m;
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,r%d,#%lux", ci->name, ra, rs, rb, m);
|
|
if(ir & 1)
|
|
setcr(0, reg.r[ra]);
|
|
}
|
|
|
|
void
|
|
slw(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
long v;
|
|
|
|
getlrrr(ir);
|
|
v = reg.r[rb];
|
|
if((v & 0x20) == 0) {
|
|
v &= 0x1F;
|
|
reg.r[ra] = (ulong)reg.r[rs] << v;
|
|
} else
|
|
reg.r[ra] = 0;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
sraw(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
long v;
|
|
|
|
getlrrr(ir);
|
|
v = reg.r[rb];
|
|
if((v & 0x20) == 0) {
|
|
v &= 0x1F;
|
|
if(reg.r[rs]&SIGNBIT && v)
|
|
reg.r[ra] = reg.r[rs]>>v | ~((1<<(32-v))-1);
|
|
else
|
|
reg.r[ra] = reg.r[rs]>>v;
|
|
} else
|
|
reg.r[ra] = reg.r[rs]&SIGNBIT? ~0: 0;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
srawi(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
long v;
|
|
|
|
getlrrr(ir);
|
|
v = rb;
|
|
if((v & 0x20) == 0) {
|
|
v &= 0x1F;
|
|
if(reg.r[rs]&SIGNBIT && v)
|
|
reg.r[ra] = reg.r[rs]>>v | ~((1<<(32-v))-1);
|
|
else
|
|
reg.r[ra] = reg.r[rs]>>v;
|
|
} else
|
|
reg.r[ra] = reg.r[rs]&SIGNBIT? ~0: 0;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,$%d", ci->name, ir&1?".":"", ra, rs, v);
|
|
}
|
|
|
|
void
|
|
srw(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
long v;
|
|
|
|
getlrrr(ir);
|
|
v = reg.r[rb];
|
|
if((v & 0x20) == 0)
|
|
reg.r[ra] = (ulong)reg.r[rs] >> (v&0x1F);
|
|
else
|
|
reg.r[ra] = 0;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[ra]);
|
|
if(trace)
|
|
itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
subf(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)reg.r[rb] + 1;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(r >> 16)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
subfc(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)reg.r[rb] + 1;
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
subfe(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)reg.r[rb] + ((reg.xer&XER_CA)!=0);
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
|
|
}
|
|
|
|
void
|
|
subfic(ulong ir)
|
|
{
|
|
int rd, ra;
|
|
long imm;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getairr(ir);
|
|
r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)imm + 1;
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
reg.r[rd] = (ulong)r;
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
|
|
}
|
|
|
|
void
|
|
subfme(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
if(rb)
|
|
undef(ir);
|
|
r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)0xFFFFFFFFU + ((reg.xer&XER_CA)!=0);
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
|
|
}
|
|
|
|
void
|
|
subfze(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
ulong v;
|
|
uvlong r;
|
|
|
|
getarrr(ir);
|
|
if(rb)
|
|
undef(ir);
|
|
r = (uvlong)((ulong)~reg.r[ra]) + ((reg.xer&XER_CA)!=0);
|
|
v = r>>32;
|
|
reg.xer &= ~XER_CA;
|
|
if(v)
|
|
reg.xer |= XER_CA;
|
|
if(ir & OE) {
|
|
reg.xer &= ~XER_OV;
|
|
if(v>>1)
|
|
reg.xer |= XER_SO | XER_OV;
|
|
}
|
|
reg.r[rd] = (ulong)r;
|
|
if(ir & Rc)
|
|
setcr(0, reg.r[rd]);
|
|
if(trace)
|
|
itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
|
|
}
|
|
|
|
void
|
|
xor(ulong ir)
|
|
{
|
|
int rs, ra, rb;
|
|
|
|
getlrrr(ir);
|
|
reg.r[ra] = reg.r[rs] ^ reg.r[rb];
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,r%d", ci->name, ra, rs, rb);
|
|
}
|
|
|
|
void
|
|
xori(ulong ir)
|
|
{
|
|
int rs, ra;
|
|
ulong imm;
|
|
|
|
getlirr(ir);
|
|
reg.r[ra] = reg.r[rs] ^ imm;
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
|
|
}
|
|
|
|
void
|
|
xoris(ulong ir)
|
|
{
|
|
int rs, ra;
|
|
ulong imm;
|
|
|
|
getlirr(ir);
|
|
reg.r[ra] = reg.r[rs] ^ (imm<<16);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
|
|
}
|
|
|
|
void
|
|
lwz(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
|
|
|
|
reg.r[rd] = getmem_w(ea);
|
|
}
|
|
|
|
void
|
|
lwzx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, upd;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==55;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
|
|
reg.r[rd] = getmem_w(ea);
|
|
}
|
|
|
|
void
|
|
lwarx(ulong ir)
|
|
{
|
|
lwzx(ir);
|
|
}
|
|
|
|
void
|
|
lbz(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
|
|
|
|
reg.r[rd] = getmem_b(ea);
|
|
}
|
|
|
|
void
|
|
lbzx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, upd;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==119;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
|
|
reg.r[rd] = getmem_b(ea);
|
|
}
|
|
|
|
void
|
|
stw(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, imm, ra, ea, reg.r[rd], reg.r[rd]);
|
|
putmem_w(ea, reg.r[rd]);
|
|
|
|
}
|
|
|
|
void
|
|
stwx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd, rb;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==183;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, ra, rb, ea, reg.r[rd], reg.r[rd]);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, rb, ea, reg.r[rd], reg.r[rd]);
|
|
}
|
|
putmem_w(ea, reg.r[rd]);
|
|
|
|
}
|
|
|
|
void
|
|
stwcx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, rb;
|
|
|
|
if((ir & Rc) == 0)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, ra, rb, ea, reg.r[rd], reg.r[rd]);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, rb, ea, reg.r[rd], reg.r[rd]);
|
|
}
|
|
putmem_w(ea, reg.r[rd]); /* assume a reservation exists; store succeeded */
|
|
setcr(0, 0);
|
|
|
|
}
|
|
|
|
void
|
|
stb(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd, v;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
v = reg.r[rd] & 0xFF;
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, imm, ra, ea, v, v);
|
|
putmem_b(ea, v);
|
|
}
|
|
|
|
void
|
|
stbx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd, rb, v;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==247;
|
|
v = reg.r[rd] & 0xFF;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, ra, rb, ea, v, v);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, rb, ea, v, v);
|
|
}
|
|
putmem_b(ea, v);
|
|
|
|
}
|
|
|
|
void
|
|
lhz(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int imm, ra, rd, upd;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
|
|
|
|
reg.r[rd] = getmem_h(ea);
|
|
}
|
|
|
|
void
|
|
lhzx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, upd;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==311;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
|
|
reg.r[rd] = getmem_h(ea);
|
|
}
|
|
|
|
void
|
|
lha(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int imm, ra, rd, upd;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
|
|
|
|
reg.r[rd] = (short)getmem_h(ea);
|
|
}
|
|
|
|
void
|
|
lhax(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, upd;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==311;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
|
|
reg.r[rd] = (short)getmem_h(ea);
|
|
}
|
|
|
|
void
|
|
lhbrx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd;
|
|
ulong v;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
v = getmem_h(ea);
|
|
|
|
reg.r[rd] = ((v&0xFF)<<8)|(v&0xFF);
|
|
}
|
|
|
|
void
|
|
sth(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int imm, ra, rd, upd, v;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
upd = (ir&(1L<<26))!=0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
}
|
|
v = reg.r[rd] & 0xFFFF;
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, imm, ra, ea, v, v);
|
|
putmem_h(ea, v);
|
|
|
|
}
|
|
|
|
void
|
|
sthx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, upd, rb, v;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
upd = getxo(ir)==247;
|
|
v = reg.r[rd] & 0xFFFF;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(upd)
|
|
reg.r[ra] = ea;
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, ra, rb, ea, v, v);
|
|
} else {
|
|
if(upd)
|
|
undef(ir);
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, rb, ea, v, v);
|
|
}
|
|
putmem_h(ea, v);
|
|
}
|
|
|
|
void
|
|
sthbrx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, rb;
|
|
ulong v;
|
|
|
|
getarrr(ir);
|
|
ea = reg.r[rb];
|
|
v = reg.r[rd];
|
|
v = ((v&0xFF)<<8)|(v&0xFF);
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, ra, rb, ea, v, v);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
|
|
ci->name, rd, rb, ea, v, v);
|
|
}
|
|
putmem_h(ea, v);
|
|
}
|
|
|
|
void
|
|
lwbrx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, i;
|
|
ulong v;
|
|
|
|
getarrr(ir);
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
ea = reg.r[rb];
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
v = 0;
|
|
for(i = 0; i < 4; i++)
|
|
v = v>>8 | getmem_b(ea++); /* assume unaligned load is allowed */
|
|
reg.r[rd] = v;
|
|
}
|
|
|
|
void
|
|
stwbrx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, i;
|
|
ulong v;
|
|
|
|
getarrr(ir);
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
ea = reg.r[rb];
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
|
|
}
|
|
v = 0;
|
|
for(i = 0; i < 4; i++) {
|
|
putmem_b(ea++, v & 0xFF); /* assume unaligned store is allowed */
|
|
v >>= 8;
|
|
}
|
|
}
|
|
|
|
void
|
|
lswi(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, n, i, r, b;
|
|
|
|
getarrr(ir);
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
n = rb;
|
|
if(n == 0)
|
|
n = 32;
|
|
ea = 0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d),%d ea=%lux", ci->name, rd, ra, n, ea);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(0),%d ea=0", ci->name, rd, n);
|
|
}
|
|
i = -1;
|
|
r = rd-1;
|
|
while(--n >= 0) {
|
|
if(i < 0) {
|
|
r = (r+1)&0x1F;
|
|
if(ra == 0 || r != ra)
|
|
reg.r[r] = 0;
|
|
i = 24;
|
|
}
|
|
b = getmem_b(ea++);
|
|
if(ra == 0 || r != ra)
|
|
reg.r[r] = (reg.r[r] & ~(0xFF<<i)) | (b << i);
|
|
i -= 8;
|
|
}
|
|
}
|
|
|
|
void
|
|
lswx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, n, i, r, b;
|
|
|
|
getarrr(ir);
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
n = reg.xer & 0x7F;
|
|
ea = reg.r[rb];
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux n=%d", ci->name, rd, ra, rb, ea, n);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux n=%d", ci->name, rd, rb, ea, n);
|
|
}
|
|
i = -1;
|
|
r = rd-1;
|
|
while(--n >= 0) {
|
|
if(i < 0) {
|
|
r = (r+1)&0x1F;
|
|
if((ra == 0 || r != ra) && r != rb)
|
|
reg.r[r] = 0;
|
|
i = 24;
|
|
}
|
|
b = getmem_b(ea++);
|
|
if((ra == 0 || r != ra) && r != rb)
|
|
reg.r[r] = (reg.r[r] & ~(0xFF<<i)) | (b << i);
|
|
i -= 8;
|
|
}
|
|
}
|
|
|
|
void
|
|
stswx(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, n, i, r;
|
|
|
|
getarrr(ir);
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
n = reg.xer & 0x7F;
|
|
ea = reg.r[rb];
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d+r%d) ea=%lux n=%d", ci->name, rd, ra, rb, ea, n);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d) ea=%lux n=%d", ci->name, rd, rb, ea, n);
|
|
}
|
|
i = -1;
|
|
r = rd-1;
|
|
while(--n >= 0) {
|
|
if(i < 0) {
|
|
r = (r+1)&0x1F;
|
|
i = 24;
|
|
}
|
|
putmem_b(ea++, (reg.r[r]>>i)&0xFF);
|
|
i -= 8;
|
|
}
|
|
}
|
|
|
|
void
|
|
stswi(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int rb, ra, rd, n, i, r;
|
|
|
|
getarrr(ir);
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
n = rb;
|
|
if(n == 0)
|
|
n = 32;
|
|
ea = 0;
|
|
if(ra) {
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,(r%d),%d ea=%lux", ci->name, rd, ra, n, ea);
|
|
} else {
|
|
if(trace)
|
|
itrace("%s\tr%d,(0),%d ea=0", ci->name, rd, n);
|
|
}
|
|
i = -1;
|
|
r = rd-1;
|
|
while(--n >= 0) {
|
|
if(i < 0) {
|
|
r = (r+1)&0x1F;
|
|
i = 24;
|
|
}
|
|
putmem_b(ea++, (reg.r[r]>>i)&0xFF);
|
|
i -= 8;
|
|
}
|
|
}
|
|
|
|
void
|
|
lmw(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, r;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
if(ra)
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
|
|
|
|
for(r = rd; r <= 31; r++) {
|
|
if(r != 0 && r != rd)
|
|
reg.r[rd] = getmem_w(ea);
|
|
ea += 4;
|
|
}
|
|
}
|
|
|
|
void
|
|
stmw(ulong ir)
|
|
{
|
|
ulong ea;
|
|
int ra, rd, r;
|
|
long imm;
|
|
|
|
getairr(ir);
|
|
ea = imm;
|
|
if(ra)
|
|
ea += reg.r[ra];
|
|
if(trace)
|
|
itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
|
|
|
|
for(r = rd; r <= 31; r++) {
|
|
putmem_w(ea, reg.r[rd]);
|
|
ea += 4;
|
|
}
|
|
}
|
|
|
|
void
|
|
twi(ulong ir)
|
|
{
|
|
int rd, ra;
|
|
long a, imm;
|
|
|
|
getairr(ir);
|
|
a = reg.r[ra];
|
|
if(trace)
|
|
itrace("twi\t#%.2x,r%d,$0x%lux (%ld)", rd, ra, imm, imm);
|
|
if(a < imm && rd&0x10 ||
|
|
a > imm && rd&0x08 ||
|
|
a == imm && rd&0x04 ||
|
|
(ulong)a < imm && rd&0x02 ||
|
|
(ulong)a > imm && rd&0x01) {
|
|
Bprint(bioout, "program_exception (trap type)\n");
|
|
longjmp(errjmp, 0);
|
|
}
|
|
}
|
|
|
|
void
|
|
tw(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
long a, b;
|
|
|
|
getarrr(ir);
|
|
a = reg.r[ra];
|
|
b = reg.r[rb];
|
|
if(trace)
|
|
itrace("tw\t#%.2x,r%d,r%d", rd, ra, rb);
|
|
if(a < b && rd&0x10 ||
|
|
a > b && rd&0x08 ||
|
|
a == b && rd&0x04 ||
|
|
(ulong)a < b && rd&0x02 ||
|
|
(ulong)a > b && rd&0x01) {
|
|
Bprint(bioout, "program_exception (trap type)\n");
|
|
longjmp(errjmp, 0);
|
|
}
|
|
}
|
|
|
|
void
|
|
sync(ulong ir)
|
|
{
|
|
USED(ir);
|
|
if(trace)
|
|
itrace("sync");
|
|
}
|
|
|
|
void
|
|
icbi(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
USED(rd);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d", ci->name, ra, rb);
|
|
}
|
|
|
|
void
|
|
dcbf(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
USED(rd);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d", ci->name, ra, rb);
|
|
}
|
|
|
|
void
|
|
dcbst(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
USED(rd);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d", ci->name, ra, rb);
|
|
}
|
|
|
|
void
|
|
dcbt(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
USED(rd);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d", ci->name, ra, rb);
|
|
}
|
|
|
|
void
|
|
dcbtst(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
USED(rd);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d", ci->name, ra, rb);
|
|
}
|
|
|
|
void
|
|
dcbz(ulong ir)
|
|
{
|
|
int rd, ra, rb;
|
|
|
|
if(ir & Rc)
|
|
undef(ir);
|
|
getarrr(ir);
|
|
USED(rd);
|
|
if(trace)
|
|
itrace("%s\tr%d,r%d", ci->name, ra, rb);
|
|
}
|