![ppatience0](/assets/img/avatar_default.png)
the openbsd sis(4) driver does not actually go through the rest of softreset() with sis cards. also, rev 635 reads the mac address differently, so copy-paste code from openbsd to handle that.
1237 lines
28 KiB
C
1237 lines
28 KiB
C
/*
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* National Semiconductor DP83815
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*
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* Supports only internal PHY and has been tested on:
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* Netgear FA311TX (using Netgear DS108 10/100 hub)
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* SiS 900 within SiS 630
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* To do:
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* check Ethernet address;
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* test autonegotiation on 10 Mbit, and 100 Mbit full duplex;
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* external PHY via MII (should be common code for MII);
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* thresholds;
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* ring sizing;
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* physical link changes/disconnect;
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* push initialisation back to attach.
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*
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* C H Forsyth, forsyth@vitanuova.com, 18th June 2001.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#define DEBUG 0
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#define debug if(DEBUG)print
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enum {
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Nrde = 64,
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Ntde = 64,
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};
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#define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
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typedef struct Des {
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ulong next;
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int cmdsts;
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ulong addr;
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Block* bp;
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} Des;
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enum { /* cmdsts */
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Own = 1<<31, /* set by data producer to hand to consumer */
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More = 1<<30, /* more of packet in next descriptor */
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Intr = 1<<29, /* interrupt when device is done with it */
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Supcrc = 1<<28, /* suppress crc on transmit */
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Inccrc = 1<<28, /* crc included on receive (always) */
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Ok = 1<<27, /* packet ok */
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Size = 0xFFF, /* packet size in bytes */
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/* transmit */
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Txa = 1<<26, /* transmission aborted */
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Tfu = 1<<25, /* transmit fifo underrun */
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Crs = 1<<24, /* carrier sense lost */
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Td = 1<<23, /* transmission deferred */
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Ed = 1<<22, /* excessive deferral */
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Owc = 1<<21, /* out of window collision */
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Ec = 1<<20, /* excessive collisions */
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/* 19-16 collision count */
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/* receive */
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Rxa = 1<<26, /* receive aborted (same as Rxo) */
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Rxo = 1<<25, /* receive overrun */
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Dest = 3<<23, /* destination class */
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Drej= 0<<23, /* packet was rejected */
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Duni= 1<<23, /* unicast */
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Dmulti= 2<<23, /* multicast */
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Dbroad= 3<<23, /* broadcast */
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Long = 1<<22, /* too long packet received */
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Runt = 1<<21, /* packet less than 64 bytes */
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Ise = 1<<20, /* invalid symbol */
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Crce = 1<<19, /* invalid crc */
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Fae = 1<<18, /* frame alignment error */
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Lbp = 1<<17, /* loopback packet */
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Col = 1<<16, /* collision during receive */
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};
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enum { /* PCI vendor & device IDs */
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Nat83815 = (0x0020<<16)|0x100B,
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SiS = 0x1039,
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SiS900 = (0x0900<<16)|SiS,
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SiS7016 = (0x7016<<16)|SiS,
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SiS630bridge = 0x0008,
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/* SiS 900 PCI revision codes */
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SiSrev630s = 0x81,
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SiSrev630e = 0x82,
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SiSrev630ea1 = 0x83,
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SiSrev635 = 0x90,
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SiSeenodeaddr = 8, /* short addr of SiS eeprom mac addr */
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SiS630eenodeaddr = 9, /* likewise for the 630 */
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Nseenodeaddr = 6, /* " for NS eeprom */
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Nat83815avng = 0x403,
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Nat83816avng = 0x505, /* 83816 acts like submodel of 83815 */
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/* using reg. 0x58 to disambiguate. */
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};
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typedef struct Ctlr Ctlr;
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typedef struct Ctlr {
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int port;
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Pcidev* pcidev;
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Ctlr* next;
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int active;
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int id; /* (pcidev->did<<16)|pcidev->vid */
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ushort srom[0xB+1];
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uchar sromea[Eaddrlen]; /* MAC address */
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uchar fd; /* option or auto negotiation */
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int mbps;
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Lock lock;
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Des* rdr; /* receive descriptor ring */
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int nrdr; /* size of rdr */
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int rdrx; /* index into rdr */
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Lock tlock;
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Des* tdr; /* transmit descriptor ring */
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int ntdr; /* size of tdr */
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int tdrh; /* host index into tdr */
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int tdri; /* interface index into tdr */
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int ntq; /* descriptors active */
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int ntqmax;
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ulong rxa; /* receive statistics */
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ulong rxo;
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ulong rlong;
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ulong runt;
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ulong ise;
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ulong crce;
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ulong fae;
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ulong lbp;
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ulong col;
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ulong rxsovr;
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ulong rxorn;
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ulong txa; /* transmit statistics */
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ulong tfu;
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ulong crs;
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ulong td;
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ulong ed;
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ulong owc;
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ulong ec;
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ulong txurn;
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ulong dperr; /* system errors */
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ulong rmabt;
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ulong rtabt;
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ulong sserr;
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ulong rxsover;
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ulong version; /* silicon version; register 0x58h */
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} Ctlr;
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static Ctlr* ctlrhead;
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static Ctlr* ctlrtail;
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enum {
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/* registers (could memory map) */
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Rcr= 0x00, /* command register */
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Rld= 1<<10, /* reload */
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Rst= 1<<8,
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Rxr= 1<<5, /* receiver reset */
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Txr= 1<<4, /* transmitter reset */
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Rxd= 1<<3, /* receiver disable */
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Rxe= 1<<2, /* receiver enable */
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Txd= 1<<1, /* transmitter disable */
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Txe= 1<<0, /* transmitter enable */
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Rcfg= 0x04, /* configuration */
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Lnksts= 1<<31, /* link good */
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Speed100= 1<<30, /* 100 Mb/s link */
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Fdup= 1<<29, /* full duplex */
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Pol= 1<<28, /* polarity reversal (10baseT) */
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Aneg_dn= 1<<27, /* autonegotiation done */
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Pint_acen= 1<<17, /* PHY interrupt auto clear enable */
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Pause_adv= 1<<16, /* advertise pause during auto neg */
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Paneg_ena= 1<<13, /* auto negotiation enable */
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Paneg_all= 7<<13, /* auto negotiation enable 10/100 half & full */
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Ext_phy= 1<<12, /* enable MII for external PHY */
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Phy_rst= 1<<10, /* reset internal PHY */
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Phy_dis= 1<<9, /* disable internal PHY (eg, low power) */
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Req_alg= 1<<7, /* PCI bus request: set means less aggressive */
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Sb= 1<<6, /* single slot back-off not random */
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Pow= 1<<5, /* out of window timer selection */
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Exd= 1<<4, /* disable excessive deferral timer */
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Pesel= 1<<3, /* parity error algorithm selection */
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Brom_dis= 1<<2, /* disable boot rom interface */
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Bem= 1<<0, /* big-endian mode */
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Rmear= 0x08, /* eeprom access */
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Mdc= 1<<6, /* MII mangement check */
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Mddir= 1<<5, /* MII management direction */
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Mdio= 1<<4, /* MII mangement data */
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Eesel= 1<<3, /* EEPROM chip select */
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Eeclk= 1<<2, /* EEPROM clock */
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Eedo= 1<<1, /* EEPROM data out (from chip) */
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Eedi= 1<<0, /* EEPROM data in (to chip) */
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Rptscr= 0x0C, /* pci test control */
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Risr= 0x10, /* interrupt status */
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Txrcmp= 1<<25, /* transmit reset complete */
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Rxrcmp= 1<<24, /* receiver reset complete */
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Dperr= 1<<23, /* detected parity error */
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Sserr= 1<<22, /* signalled system error */
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Rmabt= 1<<21, /* received master abort */
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Rtabt= 1<<20, /* received target abort */
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Rxsovr= 1<<16, /* RX status FIFO overrun */
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Hiberr= 1<<15, /* high bits error set (OR of 25-16) */
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Phy= 1<<14, /* PHY interrupt */
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Pme= 1<<13, /* power management event (wake online) */
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Swi= 1<<12, /* software interrupt */
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Mib= 1<<11, /* MIB service */
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Txurn= 1<<10, /* TX underrun */
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Txidle= 1<<9, /* TX idle */
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Txerr= 1<<8, /* TX packet error */
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Txdesc= 1<<7, /* TX descriptor (with Intr bit done) */
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Txok= 1<<6, /* TX ok */
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Rxorn= 1<<5, /* RX overrun */
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Rxidle= 1<<4, /* RX idle */
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Rxearly= 1<<3, /* RX early threshold */
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Rxerr= 1<<2, /* RX packet error */
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Rxdesc= 1<<1, /* RX descriptor (with Intr bit done) */
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Rxok= 1<<0, /* RX ok */
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Rimr= 0x14, /* interrupt mask */
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Rier= 0x18, /* interrupt enable */
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Ie= 1<<0, /* interrupt enable */
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Rtxdp= 0x20, /* transmit descriptor pointer */
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Rtxcfg= 0x24, /* transmit configuration */
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Csi= 1<<31, /* carrier sense ignore (needed for full duplex) */
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Hbi= 1<<30, /* heartbeat ignore (needed for full duplex) */
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Atp= 1<<28, /* automatic padding of runt packets */
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Mxdma= 7<<20, /* maximum dma transfer field */
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Mxdma32= 4<<20, /* 4x32-bit words (32 bytes) */
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Mxdma64= 5<<20, /* 8x32-bit words (64 bytes) */
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Flth= 0x3F<<8,/* Tx fill threshold, units of 32 bytes (must be > Mxdma) */
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Drth= 0x3F<<0,/* Tx drain threshold (units of 32 bytes) */
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Flth128= 4<<8, /* fill at 128 bytes */
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Drth512= 16<<0, /* drain at 512 bytes */
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Rrxdp= 0x30, /* receive descriptor pointer */
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Rrxcfg= 0x34, /* receive configuration */
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Atx= 1<<28, /* accept transmit packets (needed for full duplex) */
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Rdrth= 0x1F<<1,/* Rx drain threshold (units of 32 bytes) */
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Rdrth64= 2<<1, /* drain at 64 bytes */
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Rccsr= 0x3C, /* CLKRUN control/status */
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Pmests= 1<<15, /* PME status */
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Rwcsr= 0x40, /* wake on lan control/status */
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Rpcr= 0x44, /* pause control/status */
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Rrfcr= 0x48, /* receive filter/match control */
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Rfen= 1<<31, /* receive filter enable */
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Aab= 1<<30, /* accept all broadcast */
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Aam= 1<<29, /* accept all multicast */
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Aau= 1<<28, /* accept all unicast */
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Apm= 1<<27, /* accept on perfect match */
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Apat= 0xF<<23,/* accept on pattern match */
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Aarp= 1<<22, /* accept ARP */
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Mhen= 1<<21, /* multicast hash enable */
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Uhen= 1<<20, /* unicast hash enable */
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Ulm= 1<<19, /* U/L bit mask */
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/* bits 0-9 are rfaddr */
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Rrfdr= 0x4C, /* receive filter/match data */
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Rbrar= 0x50, /* boot rom address */
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Rbrdr= 0x54, /* boot rom data */
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Rsrr= 0x58, /* silicon revision */
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Rmibc= 0x5C, /* MIB control */
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/* 60-78 MIB data */
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/* PHY registers */
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Rbmcr= 0x80, /* basic mode configuration */
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Reset= 1<<15,
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Sel100= 1<<13, /* select 100Mb/sec if no auto neg */
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Anena= 1<<12, /* auto negotiation enable */
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Anrestart= 1<<9, /* restart auto negotiation */
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Selfdx= 1<<8, /* select full duplex if no auto neg */
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Rbmsr= 0x84, /* basic mode status */
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Ancomp= 1<<5, /* autonegotiation complete */
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Rphyidr1= 0x88,
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Rphyidr2= 0x8C,
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Ranar= 0x90, /* autonegotiation advertisement */
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Ranlpar= 0x94, /* autonegotiation link partner ability */
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Raner= 0x98, /* autonegotiation expansion */
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Rannptr= 0x9C, /* autonegotiation next page TX */
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Rphysts= 0xC0, /* PHY status */
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Rmicr= 0xC4, /* MII control */
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Inten= 1<<1, /* PHY interrupt enable */
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Rmisr= 0xC8, /* MII status */
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Rfcscr= 0xD0, /* false carrier sense counter */
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Rrecr= 0xD4, /* receive error counter */
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Rpcsr= 0xD8, /* 100Mb config/status */
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Rphycr= 0xE4, /* PHY control */
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Rtbscr= 0xE8, /* 10BaseT status/control */
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};
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/*
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* eeprom addresses
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* 7 to 9 (16 bit words): mac address, shifted and reversed
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*/
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#define csr32r(c, r) (inl((c)->port+(r)))
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#define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
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#define csr16r(c, r) (ins((c)->port+(r)))
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#define csr16w(c, r, l) (outs((c)->port+(r), (ulong)(l)))
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static void
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dumpcregs(Ctlr *ctlr)
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{
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int i;
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for(i=0; i<=0x5C; i+=4)
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print("%2.2ux %8.8lux\n", i, csr32r(ctlr, i));
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}
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static void
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promiscuous(void* arg, int on)
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{
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Ctlr *ctlr;
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ulong w;
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ctlr = ((Ether*)arg)->ctlr;
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ilock(&ctlr->lock);
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w = csr32r(ctlr, Rrfcr);
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if(on != ((w&Aau)!=0)){
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csr32w(ctlr, Rrfcr, w & ~Rfen);
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csr32w(ctlr, Rrfcr, Rfen | (w ^ Aau));
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}
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iunlock(&ctlr->lock);
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}
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static void
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attach(Ether* ether)
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{
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Ctlr *ctlr;
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ctlr = ether->ctlr;
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ilock(&ctlr->lock);
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if(0)
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dumpcregs(ctlr);
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csr32w(ctlr, Rcr, Rxe);
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iunlock(&ctlr->lock);
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}
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static long
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ifstat(Ether* ether, void* a, long n, ulong offset)
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{
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Ctlr *ctlr;
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char *buf, *p;
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int i, l, len;
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ctlr = ether->ctlr;
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ether->crcs = ctlr->crce;
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ether->frames = ctlr->runt+ctlr->ise+ctlr->rlong+ctlr->fae;
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ether->buffs = ctlr->rxorn+ctlr->tfu;
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ether->overflows = ctlr->rxsovr;
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if(n == 0)
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return 0;
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p = smalloc(READSTR);
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l = snprint(p, READSTR, "Rxa: %lud\n", ctlr->rxa);
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l += snprint(p+l, READSTR-l, "Rxo: %lud\n", ctlr->rxo);
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l += snprint(p+l, READSTR-l, "Rlong: %lud\n", ctlr->rlong);
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l += snprint(p+l, READSTR-l, "Runt: %lud\n", ctlr->runt);
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l += snprint(p+l, READSTR-l, "Ise: %lud\n", ctlr->ise);
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l += snprint(p+l, READSTR-l, "Fae: %lud\n", ctlr->fae);
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l += snprint(p+l, READSTR-l, "Lbp: %lud\n", ctlr->lbp);
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l += snprint(p+l, READSTR-l, "Tfu: %lud\n", ctlr->tfu);
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l += snprint(p+l, READSTR-l, "Txa: %lud\n", ctlr->txa);
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l += snprint(p+l, READSTR-l, "CRC Error: %lud\n", ctlr->crce);
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l += snprint(p+l, READSTR-l, "Collision Seen: %lud\n", ctlr->col);
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l += snprint(p+l, READSTR-l, "Frame Too Long: %lud\n", ctlr->rlong);
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l += snprint(p+l, READSTR-l, "Runt Frame: %lud\n", ctlr->runt);
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l += snprint(p+l, READSTR-l, "Rx Underflow Error: %lud\n", ctlr->rxorn);
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l += snprint(p+l, READSTR-l, "Tx Underrun: %lud\n", ctlr->txurn);
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l += snprint(p+l, READSTR-l, "Excessive Collisions: %lud\n", ctlr->ec);
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l += snprint(p+l, READSTR-l, "Late Collision: %lud\n", ctlr->owc);
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l += snprint(p+l, READSTR-l, "Loss of Carrier: %lud\n", ctlr->crs);
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l += snprint(p+l, READSTR-l, "Parity: %lud\n", ctlr->dperr);
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l += snprint(p+l, READSTR-l, "Aborts: %lud\n", ctlr->rmabt+ctlr->rtabt);
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l += snprint(p+l, READSTR-l, "RX Status overrun: %lud\n", ctlr->rxsover);
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snprint(p+l, READSTR-l, "ntqmax: %d\n", ctlr->ntqmax);
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ctlr->ntqmax = 0;
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buf = a;
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len = readstr(offset, buf, n, p);
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if(offset > l)
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offset -= l;
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else
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offset = 0;
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buf += len;
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n -= len;
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l = snprint(p, READSTR, "srom:");
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for(i = 0; i < nelem(ctlr->srom); i++){
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if(i && ((i & 0x0F) == 0))
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l += snprint(p+l, READSTR-l, "\n ");
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l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->srom[i]);
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}
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snprint(p+l, READSTR-l, "\n");
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len += readstr(offset, buf, n, p);
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free(p);
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return len;
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}
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static void
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txstart(Ether* ether)
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{
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Ctlr *ctlr;
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Block *bp;
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Des *des;
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int started;
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ctlr = ether->ctlr;
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started = 0;
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while(ctlr->ntq < ctlr->ntdr-1){
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bp = qget(ether->oq);
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if(bp == nil)
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break;
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des = &ctlr->tdr[ctlr->tdrh];
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des->bp = bp;
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des->addr = PADDR(bp->rp);
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ctlr->ntq++;
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coherence();
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des->cmdsts = Own | BLEN(bp);
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ctlr->tdrh = NEXT(ctlr->tdrh, ctlr->ntdr);
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started = 1;
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}
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if(started){
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coherence();
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csr32w(ctlr, Rcr, Txe); /* prompt */
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}
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if(ctlr->ntq > ctlr->ntqmax)
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ctlr->ntqmax = ctlr->ntq;
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}
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static void
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transmit(Ether* ether)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = ether->ctlr;
|
|
ilock(&ctlr->tlock);
|
|
txstart(ether);
|
|
iunlock(&ctlr->tlock);
|
|
}
|
|
|
|
static void
|
|
txrxcfg(Ctlr *ctlr, int txdrth)
|
|
{
|
|
ulong rx, tx;
|
|
|
|
rx = csr32r(ctlr, Rrxcfg);
|
|
tx = csr32r(ctlr, Rtxcfg);
|
|
if(ctlr->fd){
|
|
rx |= Atx;
|
|
tx |= Csi | Hbi;
|
|
}else{
|
|
rx &= ~Atx;
|
|
tx &= ~(Csi | Hbi);
|
|
}
|
|
tx &= ~(Mxdma|Drth|Flth);
|
|
tx |= Mxdma64 | Flth128 | txdrth;
|
|
csr32w(ctlr, Rtxcfg, tx);
|
|
rx &= ~(Mxdma|Rdrth);
|
|
rx |= Mxdma64 | Rdrth64;
|
|
csr32w(ctlr, Rrxcfg, rx);
|
|
}
|
|
|
|
static void
|
|
interrupt(Ureg*, void* arg)
|
|
{
|
|
int len, status, cmdsts, n;
|
|
Ctlr *ctlr;
|
|
Ether *ether;
|
|
Des *des;
|
|
Block *bp;
|
|
|
|
ether = arg;
|
|
ctlr = ether->ctlr;
|
|
|
|
while((status = csr32r(ctlr, Risr)) != 0){
|
|
|
|
status &= ~(Pme|Mib);
|
|
|
|
if(status & Hiberr){
|
|
if(status & Rxsovr)
|
|
ctlr->rxsover++;
|
|
if(status & Sserr)
|
|
ctlr->sserr++;
|
|
if(status & Dperr)
|
|
ctlr->dperr++;
|
|
if(status & Rmabt)
|
|
ctlr->rmabt++;
|
|
if(status & Rtabt)
|
|
ctlr->rtabt++;
|
|
status &= ~(Hiberr|Txrcmp|Rxrcmp|Rxsovr|Dperr|Sserr|Rmabt|Rtabt);
|
|
}
|
|
|
|
/* update link state */
|
|
if(status&Phy){
|
|
status &= ~Phy;
|
|
csr32r(ctlr, Rcfg);
|
|
n = csr32r(ctlr, Rcfg);
|
|
// iprint("83815 phy %x %x\n", n, n&Lnksts);
|
|
ether->link = (n&Lnksts) != 0;
|
|
}
|
|
|
|
/*
|
|
* Received packets.
|
|
*/
|
|
if(status & (Rxdesc|Rxok|Rxerr|Rxearly|Rxorn)){
|
|
des = &ctlr->rdr[ctlr->rdrx];
|
|
while((cmdsts = des->cmdsts) & Own){
|
|
if((cmdsts&Ok) == 0){
|
|
if(cmdsts & Rxa)
|
|
ctlr->rxa++;
|
|
if(cmdsts & Rxo)
|
|
ctlr->rxo++;
|
|
if(cmdsts & Long)
|
|
ctlr->rlong++;
|
|
if(cmdsts & Runt)
|
|
ctlr->runt++;
|
|
if(cmdsts & Ise)
|
|
ctlr->ise++;
|
|
if(cmdsts & Crce)
|
|
ctlr->crce++;
|
|
if(cmdsts & Fae)
|
|
ctlr->fae++;
|
|
if(cmdsts & Lbp)
|
|
ctlr->lbp++;
|
|
if(cmdsts & Col)
|
|
ctlr->col++;
|
|
}
|
|
else if(bp = iallocb(Rbsz)){
|
|
len = (cmdsts&Size)-4;
|
|
if(len <= 0){
|
|
debug("ns83815: packet len %d <=0\n", len);
|
|
freeb(des->bp);
|
|
}else{
|
|
des->bp->wp = des->bp->rp+len;
|
|
etheriq(ether, des->bp, 1);
|
|
}
|
|
des->bp = bp;
|
|
des->addr = PADDR(bp->rp);
|
|
coherence();
|
|
}else{
|
|
debug("ns83815: interrupt: iallocb for input buffer failed\n");
|
|
des->bp->next = 0;
|
|
}
|
|
|
|
des->cmdsts = Rbsz;
|
|
coherence();
|
|
|
|
ctlr->rdrx = NEXT(ctlr->rdrx, ctlr->nrdr);
|
|
des = &ctlr->rdr[ctlr->rdrx];
|
|
}
|
|
status &= ~(Rxdesc|Rxok|Rxerr|Rxearly|Rxorn);
|
|
}
|
|
|
|
/*
|
|
* Check the transmit side:
|
|
* check for Transmit Underflow and Adjust
|
|
* the threshold upwards;
|
|
* free any transmitted buffers and try to
|
|
* top-up the ring.
|
|
*/
|
|
if(status & Txurn){
|
|
ctlr->txurn++;
|
|
ilock(&ctlr->lock);
|
|
/* change threshold */
|
|
iunlock(&ctlr->lock);
|
|
status &= ~(Txurn);
|
|
}
|
|
|
|
ilock(&ctlr->tlock);
|
|
while(ctlr->ntq){
|
|
des = &ctlr->tdr[ctlr->tdri];
|
|
cmdsts = des->cmdsts;
|
|
if(cmdsts & Own)
|
|
break;
|
|
|
|
if((cmdsts & Ok) == 0){
|
|
if(cmdsts & Txa)
|
|
ctlr->txa++;
|
|
if(cmdsts & Tfu)
|
|
ctlr->tfu++;
|
|
if(cmdsts & Td)
|
|
ctlr->td++;
|
|
if(cmdsts & Ed)
|
|
ctlr->ed++;
|
|
if(cmdsts & Owc)
|
|
ctlr->owc++;
|
|
if(cmdsts & Ec)
|
|
ctlr->ec++;
|
|
ether->oerrs++;
|
|
}
|
|
|
|
freeb(des->bp);
|
|
des->bp = nil;
|
|
des->cmdsts = 0;
|
|
|
|
ctlr->ntq--;
|
|
ctlr->tdri = NEXT(ctlr->tdri, ctlr->ntdr);
|
|
}
|
|
txstart(ether);
|
|
iunlock(&ctlr->tlock);
|
|
|
|
status &= ~(Txurn|Txidle|Txerr|Txdesc|Txok);
|
|
|
|
/*
|
|
* Anything left not catered for?
|
|
*/
|
|
if(status)
|
|
print("#l%d: status %8.8uX\n", ether->ctlrno, status);
|
|
}
|
|
}
|
|
|
|
static void
|
|
ctlrinit(Ether* ether)
|
|
{
|
|
Ctlr *ctlr;
|
|
Des *des, *last;
|
|
|
|
ctlr = ether->ctlr;
|
|
|
|
/*
|
|
* Allocate suitable aligned descriptors
|
|
* for the transmit and receive rings;
|
|
* initialise the receive ring;
|
|
* initialise the transmit ring;
|
|
* unmask interrupts and start the transmit side.
|
|
*/
|
|
des = xspanalloc((ctlr->nrdr+ctlr->ntdr)*sizeof(Des), 32, 0);
|
|
ctlr->tdr = des;
|
|
ctlr->rdr = des+ctlr->ntdr;
|
|
|
|
last = nil;
|
|
for(des = ctlr->rdr; des < &ctlr->rdr[ctlr->nrdr]; des++){
|
|
des->bp = iallocb(Rbsz);
|
|
if(des->bp == nil)
|
|
panic("ether83815: can't allocate receive buffer");
|
|
des->cmdsts = Rbsz;
|
|
des->addr = PADDR(des->bp->rp);
|
|
if(last != nil)
|
|
last->next = PADDR(des);
|
|
last = des;
|
|
}
|
|
ctlr->rdr[ctlr->nrdr-1].next = PADDR(ctlr->rdr);
|
|
ctlr->rdrx = 0;
|
|
csr32w(ctlr, Rrxdp, PADDR(ctlr->rdr));
|
|
|
|
last = nil;
|
|
for(des = ctlr->tdr; des < &ctlr->tdr[ctlr->ntdr]; des++){
|
|
des->cmdsts = 0;
|
|
des->bp = nil;
|
|
des->addr = ~0;
|
|
if(last != nil)
|
|
last->next = PADDR(des);
|
|
last = des;
|
|
}
|
|
ctlr->tdr[ctlr->ntdr-1].next = PADDR(ctlr->tdr);
|
|
ctlr->tdrh = 0;
|
|
ctlr->tdri = 0;
|
|
csr32w(ctlr, Rtxdp, PADDR(ctlr->tdr));
|
|
|
|
txrxcfg(ctlr, Drth512);
|
|
|
|
csr32w(ctlr, Rimr, Dperr|Sserr|Rmabt|Rtabt|Rxsovr|Hiberr|Txurn|Txerr|
|
|
Txdesc|Txok|Rxorn|Rxerr|Rxdesc|Rxok); /* Phy|Pme|Mib */
|
|
csr32w(ctlr, Rmicr, Inten); /* enable phy interrupts */
|
|
csr32r(ctlr, Risr); /* clear status */
|
|
csr32w(ctlr, Rier, Ie);
|
|
}
|
|
|
|
static void
|
|
eeclk(Ctlr *ctlr, int clk)
|
|
{
|
|
csr32w(ctlr, Rmear, Eesel | clk);
|
|
microdelay(2);
|
|
}
|
|
|
|
static void
|
|
eeidle(Ctlr *ctlr)
|
|
{
|
|
int i;
|
|
|
|
eeclk(ctlr, 0);
|
|
eeclk(ctlr, Eeclk);
|
|
for(i=0; i<25; i++){
|
|
eeclk(ctlr, 0);
|
|
eeclk(ctlr, Eeclk);
|
|
}
|
|
eeclk(ctlr, 0);
|
|
csr32w(ctlr, Rmear, 0);
|
|
microdelay(2);
|
|
}
|
|
|
|
static ushort
|
|
eegetw(Ctlr *ctlr, int a)
|
|
{
|
|
int d, i, w;
|
|
|
|
eeidle(ctlr);
|
|
eeclk(ctlr, 0);
|
|
eeclk(ctlr, Eeclk);
|
|
d = 0x180 | a;
|
|
for(i=0x400; i; i>>=1){
|
|
if(d & i)
|
|
csr32w(ctlr, Rmear, Eesel|Eedi);
|
|
else
|
|
csr32w(ctlr, Rmear, Eesel);
|
|
eeclk(ctlr, Eeclk);
|
|
eeclk(ctlr, 0);
|
|
microdelay(2);
|
|
}
|
|
w = 0;
|
|
for(i=0x8000; i; i >>= 1){
|
|
eeclk(ctlr, Eeclk);
|
|
if(csr32r(ctlr, Rmear) & Eedo)
|
|
w |= i;
|
|
microdelay(2);
|
|
eeclk(ctlr, 0);
|
|
}
|
|
eeidle(ctlr);
|
|
return w;
|
|
}
|
|
|
|
static int
|
|
resetctlr(Ctlr *ctlr)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Soft-reset the controller
|
|
*/
|
|
csr32w(ctlr, Rcr, Rst);
|
|
for(i=0;; i++){
|
|
if(i > 100){
|
|
print("ns83815: soft reset did not complete\n");
|
|
return -1;
|
|
}
|
|
microdelay(250);
|
|
if((csr32r(ctlr, Rcr) & Rst) == 0)
|
|
break;
|
|
delay(1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
shutdown(Ether* ether)
|
|
{
|
|
Ctlr *ctlr = ether->ctlr;
|
|
|
|
print("ether83815 shutting down\n");
|
|
csr32w(ctlr, Rcr, Rxd|Txd); /* disable transceiver */
|
|
resetctlr(ctlr);
|
|
}
|
|
|
|
static int
|
|
softreset(Ctlr* ctlr, int resetphys)
|
|
{
|
|
int i, w;
|
|
|
|
/*
|
|
* Soft-reset the controller
|
|
*/
|
|
resetctlr(ctlr);
|
|
if(ctlr->id != Nat83815)
|
|
return 0;
|
|
csr32w(ctlr, Rccsr, Pmests);
|
|
csr32w(ctlr, Rccsr, 0);
|
|
csr32w(ctlr, Rcfg, csr32r(ctlr, Rcfg) | Pint_acen);
|
|
ctlr->version = csr32r(ctlr, Rsrr);
|
|
if(resetphys){
|
|
/*
|
|
* Soft-reset the PHY
|
|
*/
|
|
csr32w(ctlr, Rbmcr, Reset);
|
|
for(i=0;; i++){
|
|
if(i > 100){
|
|
print("ns83815: PHY soft reset time out\n");
|
|
return -1;
|
|
}
|
|
if((csr32r(ctlr, Rbmcr) & Reset) == 0)
|
|
break;
|
|
delay(1);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Initialisation values, in sequence (see 4.4 Recommended Registers Configuration)
|
|
*/
|
|
csr16w(ctlr, 0xCC, 0x0001); /* PGSEL */
|
|
csr16w(ctlr, 0xE4, 0x189C); /* PMCCSR */
|
|
csr16w(ctlr, 0xFC, 0x0000); /* TSTDAT */
|
|
csr16w(ctlr, 0xF4, 0x5040); /* DSPCFG */
|
|
csr16w(ctlr, 0xF8, 0x008C); /* SDCFG */
|
|
|
|
/*
|
|
* Auto negotiate
|
|
*/
|
|
csr16r(ctlr, Rbmsr); /* clear latched bits */
|
|
debug("anar: %4.4ux\n", csr16r(ctlr, Ranar));
|
|
csr16w(ctlr, Rbmcr, Anena);
|
|
if(csr16r(ctlr, Ranar) == 0 || (csr32r(ctlr, Rcfg) & Aneg_dn) == 0){
|
|
csr16w(ctlr, Rbmcr, Anena|Anrestart);
|
|
for(i=0;; i++){
|
|
if(i > 3000){
|
|
print("ns83815: auto neg timed out\n");
|
|
return -1;
|
|
}
|
|
if((w = csr16r(ctlr, Rbmsr)) & Ancomp)
|
|
break;
|
|
delay(1);
|
|
}
|
|
debug("%d ms\n", i);
|
|
w &= 0xFFFF;
|
|
debug("bmsr: %4.4ux\n", w);
|
|
USED(w);
|
|
}
|
|
debug("anar: %4.4ux\n", csr16r(ctlr, Ranar));
|
|
debug("anlpar: %4.4ux\n", csr16r(ctlr, Ranlpar));
|
|
debug("aner: %4.4ux\n", csr16r(ctlr, Raner));
|
|
debug("physts: %4.4ux\n", csr16r(ctlr, Rphysts));
|
|
debug("tbscr: %4.4ux\n", csr16r(ctlr, Rtbscr));
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
media(Ether* ether)
|
|
{
|
|
Ctlr* ctlr;
|
|
ulong cfg;
|
|
|
|
ctlr = ether->ctlr;
|
|
cfg = csr32r(ctlr, Rcfg);
|
|
ctlr->fd = (cfg & Fdup) != 0;
|
|
ether->link = (cfg&Lnksts) != 0;
|
|
return (cfg&(Lnksts|Speed100)) == Lnksts? 10: 100;
|
|
}
|
|
|
|
static char* mediatable[9] = {
|
|
"10BASE-T", /* TP */
|
|
"10BASE-2", /* BNC */
|
|
"10BASE-5", /* AUI */
|
|
"100BASE-TX",
|
|
"10BASE-TFD",
|
|
"100BASE-TXFD",
|
|
"100BASE-T4",
|
|
"100BASE-FX",
|
|
"100BASE-FXFD",
|
|
};
|
|
|
|
static int
|
|
is630(ulong id, Pcidev *p)
|
|
{
|
|
if(id == SiS900)
|
|
switch (p->rid) {
|
|
case SiSrev630s:
|
|
case SiSrev630e:
|
|
case SiSrev630ea1:
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
enum {
|
|
MagicReg = 0x48,
|
|
MagicRegSz = 1,
|
|
Magicrden = 0x40, /* read enable, apparently */
|
|
Paddr= 0x70, /* address port */
|
|
Pdata= 0x71, /* data port */
|
|
};
|
|
|
|
/* rcmos() originally from LANL's SiS 900 driver's rcmos() */
|
|
static int
|
|
sisrdcmos(Ctlr *ctlr)
|
|
{
|
|
int i;
|
|
unsigned reg;
|
|
ulong port;
|
|
Pcidev *p;
|
|
|
|
debug("ns83815: SiS 630 rev. %ux reading mac address from cmos\n", ctlr->pcidev->rid);
|
|
p = pcimatch(nil, SiS, SiS630bridge);
|
|
if(p == nil) {
|
|
print("ns83815: no SiS 630 rev. %ux bridge for mac addr\n",
|
|
ctlr->pcidev->rid);
|
|
return 0;
|
|
}
|
|
port = p->mem[0].bar & ~0x01;
|
|
debug("ns83815: SiS 630 rev. %ux reading mac addr from cmos via bridge at port 0x%lux\n", ctlr->pcidev->rid, port);
|
|
|
|
reg = pcicfgr8(p, MagicReg);
|
|
pcicfgw8(p, MagicReg, reg|Magicrden);
|
|
|
|
for (i = 0; i < Eaddrlen; i++) {
|
|
outb(port+Paddr, SiS630eenodeaddr + i);
|
|
ctlr->sromea[i] = inb(port+Pdata);
|
|
}
|
|
|
|
pcicfgw8(p, MagicReg, reg & ~Magicrden);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* If this is a SiS 630E chipset with an embedded SiS 900 controller,
|
|
* we have to read the MAC address from the APC CMOS RAM. - sez freebsd.
|
|
* However, CMOS *is* NVRAM normally. See devrtc.c:440, memory.c:88.
|
|
*/
|
|
static void
|
|
sissrom(Ctlr *ctlr)
|
|
{
|
|
union {
|
|
uchar eaddr[Eaddrlen];
|
|
ushort alignment;
|
|
} ee;
|
|
int i, off = SiSeenodeaddr, cnt = sizeof ee.eaddr / sizeof(short);
|
|
ushort *shp = (ushort *)ee.eaddr;
|
|
|
|
if(ctlr->id == SiS900 && ctlr->pcidev->rid == SiSrev635) {
|
|
csr32w(ctlr, Rcr, csr32r(ctlr, Rcr) | Rld);
|
|
csr32w(ctlr, Rcr, csr32r(ctlr, Rcr) & ~Rld);
|
|
csr32w(ctlr, Rrfcr, csr32r(ctlr, Rrfcr) & ~Rfen);
|
|
|
|
csr32w(ctlr, Rrfcr, 0);
|
|
*shp++ = csr32r(ctlr, Rrfdr);
|
|
csr32w(ctlr, Rrfcr, 1<<16);
|
|
*shp++ = csr32r(ctlr, Rrfdr);
|
|
csr32w(ctlr, Rrfcr, 1<<17);
|
|
*shp = csr32r(ctlr, Rrfdr);
|
|
|
|
csr32w(ctlr, Rrfcr, csr32r(ctlr, Rrfcr) | Rfen);
|
|
memmove(ctlr->sromea, ee.eaddr, sizeof ctlr->sromea);
|
|
} else if(!is630(ctlr->id, ctlr->pcidev) || !sisrdcmos(ctlr)) {
|
|
for (i = 0; i < cnt; i++)
|
|
*shp++ = eegetw(ctlr, off++);
|
|
memmove(ctlr->sromea, ee.eaddr, sizeof ctlr->sromea);
|
|
}
|
|
}
|
|
|
|
ushort
|
|
søkrisee(Ctlr *c, int n)
|
|
{
|
|
int i;
|
|
uint cmd;
|
|
ushort r;
|
|
|
|
csr32w(c, Rmear, Eesel);
|
|
|
|
cmd = 0x180|n;
|
|
for(i = 10; i >= 0; i--){
|
|
n = 1<<3;
|
|
if(cmd&(1<<i))
|
|
n |= 1;
|
|
csr32w(c, Rmear, n);
|
|
csr32r(c, Rmear);
|
|
csr32w(c, Rmear, n|4);
|
|
csr32r(c, Rmear);
|
|
}
|
|
|
|
csr32w(c, Rmear, 1<<3);
|
|
csr32r(c, Rmear);
|
|
|
|
r = 0;
|
|
for(i = 0; i < 16; i++){
|
|
csr32w(c, Rmear, 1<<3 | 1<<2);
|
|
csr32r(c, Rmear);
|
|
if(csr32r(c, Rmear) & 2)
|
|
r |= 1<<i;
|
|
csr32w(c, Rmear, 1<<3);
|
|
csr32r(c, Rmear);
|
|
}
|
|
|
|
csr32w(c, Rmear, 1<<3);
|
|
csr32w(c, Rmear, 0);
|
|
|
|
return r;
|
|
}
|
|
|
|
static void
|
|
nsnormalea(Ctlr *ctlr)
|
|
{
|
|
int i, j;
|
|
|
|
/*
|
|
* the MAC address is reversed, straddling word boundaries
|
|
*/
|
|
j = Nseenodeaddr*16 + 15;
|
|
for(i = 0; i < 48; i++){
|
|
ctlr->sromea[i>>3] |= ((ctlr->srom[j>>4] >> (15-(j&0xF))) & 1) << (i&7);
|
|
j++;
|
|
}
|
|
}
|
|
|
|
static void
|
|
ns403ea(Ctlr *ctlr)
|
|
{
|
|
int i;
|
|
ushort s, t;
|
|
|
|
s = ctlr->srom[6];
|
|
for(i = 0; i < 3; i++){
|
|
t = ctlr->srom[i+7];
|
|
ctlr->sromea[i*2] = t<<1 | s>>15;
|
|
ctlr->sromea[i*2+1] = t>>7;
|
|
s = t;
|
|
}
|
|
}
|
|
|
|
static void
|
|
nssrom(Ctlr* ctlr)
|
|
{
|
|
int i, ns403;
|
|
ulong vers;
|
|
ushort (*ee)(Ctlr*, int);
|
|
|
|
vers = ctlr->version;
|
|
ns403 = vers == Nat83815avng || vers == Nat83816avng;
|
|
if(ns403){
|
|
ee = søkrisee;
|
|
print("soekris %lx\n", vers);
|
|
}else
|
|
ee = eegetw;
|
|
|
|
for(i = 0; i < nelem(ctlr->srom); i++)
|
|
ctlr->srom[i] = ee(ctlr, i);
|
|
|
|
if(ns403)
|
|
ns403ea(ctlr);
|
|
else
|
|
nsnormalea(ctlr);
|
|
}
|
|
|
|
static void
|
|
srom(Ctlr* ctlr)
|
|
{
|
|
memset(ctlr->sromea, 0, sizeof(ctlr->sromea));
|
|
switch (ctlr->id) {
|
|
case SiS900:
|
|
case SiS7016:
|
|
sissrom(ctlr);
|
|
break;
|
|
case Nat83815:
|
|
nssrom(ctlr);
|
|
break;
|
|
default:
|
|
print("ns83815: srom: unknown id 0x%ux\n", ctlr->id);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
scanpci83815(void)
|
|
{
|
|
Ctlr *ctlr;
|
|
Pcidev *p;
|
|
ulong id;
|
|
|
|
p = nil;
|
|
while(p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != Pcibcnet || p->ccru != 0)
|
|
continue;
|
|
id = (p->did<<16)|p->vid;
|
|
switch(id){
|
|
default:
|
|
continue;
|
|
|
|
case Nat83815:
|
|
break;
|
|
case SiS900:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* bar[0] is the I/O port register address and
|
|
* bar[1] is the memory-mapped register address.
|
|
*/
|
|
ctlr = malloc(sizeof(Ctlr));
|
|
if(ctlr == nil){
|
|
print("ns83815: can't allocate memory\n");
|
|
continue;
|
|
}
|
|
ctlr->port = p->mem[0].bar & ~0x01;
|
|
ctlr->pcidev = p;
|
|
ctlr->id = id;
|
|
|
|
if(ioalloc(ctlr->port, p->mem[0].size, 0, "ns83815") < 0){
|
|
print("ns83815: port 0x%uX in use\n", ctlr->port);
|
|
free(ctlr);
|
|
continue;
|
|
}
|
|
|
|
if(softreset(ctlr, 0) == -1){
|
|
free(ctlr);
|
|
continue;
|
|
}
|
|
srom(ctlr);
|
|
|
|
if(ctlrhead != nil)
|
|
ctlrtail->next = ctlr;
|
|
else
|
|
ctlrhead = ctlr;
|
|
ctlrtail = ctlr;
|
|
}
|
|
}
|
|
|
|
/* multicast already on, don't need to do anything */
|
|
static void
|
|
multicast(void*, uchar*, int)
|
|
{
|
|
}
|
|
|
|
static int
|
|
reset(Ether* ether)
|
|
{
|
|
Ctlr *ctlr;
|
|
int i, x;
|
|
ulong ctladdr;
|
|
uchar ea[Eaddrlen];
|
|
static int scandone;
|
|
|
|
if(scandone == 0){
|
|
scanpci83815();
|
|
scandone = 1;
|
|
}
|
|
|
|
/*
|
|
* Any adapter matches if no ether->port is supplied,
|
|
* otherwise the ports must match.
|
|
*/
|
|
for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
if(ctlr->active)
|
|
continue;
|
|
if(ether->port == 0 || ether->port == ctlr->port){
|
|
ctlr->active = 1;
|
|
break;
|
|
}
|
|
}
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
ether->ctlr = ctlr;
|
|
ether->port = ctlr->port;
|
|
ether->irq = ctlr->pcidev->intl;
|
|
ether->tbdf = ctlr->pcidev->tbdf;
|
|
|
|
/*
|
|
* Check if the adapter's station address is to be overridden.
|
|
* If not, read it from the EEPROM and set in ether->ea prior to
|
|
* loading the station address in the hardware.
|
|
*/
|
|
memset(ea, 0, Eaddrlen);
|
|
if(memcmp(ea, ether->ea, Eaddrlen) == 0)
|
|
memmove(ether->ea, ctlr->sromea, Eaddrlen);
|
|
for(i=0; i<Eaddrlen; i+=2){
|
|
x = ether->ea[i] | (ether->ea[i+1]<<8);
|
|
ctladdr = (ctlr->id == Nat83815? i: i<<15);
|
|
csr32w(ctlr, Rrfcr, ctladdr);
|
|
csr32w(ctlr, Rrfdr, x);
|
|
}
|
|
csr32w(ctlr, Rrfcr, Rfen|Apm|Aab|Aam);
|
|
|
|
ether->mbps = media(ether);
|
|
|
|
/*
|
|
* Look for a medium override in case there's no autonegotiation
|
|
* the autonegotiation fails.
|
|
*/
|
|
|
|
for(i = 0; i < ether->nopt; i++){
|
|
if(cistrcmp(ether->opt[i], "FD") == 0){
|
|
ctlr->fd = 1;
|
|
continue;
|
|
}
|
|
for(x = 0; x < nelem(mediatable); x++){
|
|
debug("compare <%s> <%s>\n", mediatable[x],
|
|
ether->opt[i]);
|
|
if(cistrcmp(mediatable[x], ether->opt[i]) == 0){
|
|
if(x != 4 && x >= 3)
|
|
ether->mbps = 100;
|
|
else
|
|
ether->mbps = 10;
|
|
switch(x){
|
|
default:
|
|
ctlr->fd = 0;
|
|
break;
|
|
|
|
case 0x04: /* 10BASE-TFD */
|
|
case 0x05: /* 100BASE-TXFD */
|
|
case 0x08: /* 100BASE-FXFD */
|
|
ctlr->fd = 1;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Initialise descriptor rings, ethernet address.
|
|
*/
|
|
ctlr->nrdr = Nrde;
|
|
ctlr->ntdr = Ntde;
|
|
pcisetbme(ctlr->pcidev);
|
|
ctlrinit(ether);
|
|
|
|
/*
|
|
* Linkage to the generic ethernet driver.
|
|
*/
|
|
ether->attach = attach;
|
|
ether->transmit = transmit;
|
|
ether->interrupt = interrupt;
|
|
ether->ifstat = ifstat;
|
|
|
|
ether->arg = ether;
|
|
ether->promiscuous = promiscuous;
|
|
ether->multicast = multicast;
|
|
ether->shutdown = shutdown;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ether83815link(void)
|
|
{
|
|
addethercard("83815", reset);
|
|
}
|