128ea44a89
a portable SG_NOEXEC segment attribute was added to allow non-executable (physical) segments. which will set the PTENOEXEC bits for putmmu(). in the future, this can be used to make non-executable stack / bss segments. the SG_DEVICE attribute was added to distinguish between mmio regions and uncached memory. only matterns on arm64. on arm, theres the issue that PTEUNCACHED would have no bits set when using the hardware bit definitions. this is the reason bcm, kw, teg2 and omap kernels use arteficial PTE constants. on zynq, the XN bit was used as a hack to give PTEUNCACHED a non-zero value and when the bit is clear then cache attributes where added to the pte. to fix this, PTECACHED constant was added. the portable mmu code in fault.c will now explicitely set PTECACHED bits for cached memory and PTEUNCACHED for uncached memory. that way the hardware bit definitions can be used everywhere.
142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* Memory and machine-specific definitions. Used in C and assembler.
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*/
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#define KiB 1024u /* Kibi 0x0000000000000400 */
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#define MiB 1048576u /* Mebi 0x0000000000100000 */
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#define GiB 1073741824u /* Gibi 000000000040000000 */
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/*
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* Sizes:
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* L0 L1 L2 L3
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* 4K 2M 1G 512G
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* 16K 32M 64G 128T
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* 64K 512M 4T -
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*/
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#define PGSHIFT 16 /* log(BY2PG) */
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#define BY2PG (1ULL<<PGSHIFT) /* bytes per page */
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#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
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#define PGROUND(s) ROUND(s, BY2PG)
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/* effective virtual address space */
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#define EVASHIFT 34
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#define EVAMASK ((1ULL<<EVASHIFT)-1)
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#define PTSHIFT (PGSHIFT-3)
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#define PTLEVELS (((EVASHIFT-PGSHIFT)+PTSHIFT-1)/PTSHIFT)
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#define PTLX(v, l) ((((v) & EVAMASK) >> (PGSHIFT + (l)*PTSHIFT)) & ((1 << PTSHIFT)-1))
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#define PGLSZ(l) (1ULL << (PGSHIFT + (l)*PTSHIFT))
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#define PTL1X(v, l) (L1TABLEX(v, l) | PTLX(v, l))
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#define L1TABLEX(v, l) (L1TABLE(v, l) << PTSHIFT)
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#define L1TABLES ((-KSEG0+PGLSZ(2)-1)/PGLSZ(2))
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#define L1TABLE(v, l) (L1TABLES - ((PTLX(v, 2) % L1TABLES) >> (((l)-1)*PTSHIFT)) + (l)-1)
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#define L1TOPSIZE (1ULL << (EVASHIFT - PTLEVELS*PTSHIFT))
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#define MAXMACH 4 /* max # cpus system can run */
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#define MACHSIZE (8*KiB)
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#define KSTACK (8*KiB)
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#define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
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#define TRAPFRAMESIZE (38*8)
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#define KSEG0 (0xFFFFFFFE00000000ULL)
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#define KMAP (0xFFFFFFFE00000000ULL)
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#define FRAMEBUFFER (0xFFFFFFFFA0000000ULL|PTEWT)
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#define VMAP (0xFFFFFFFFB0000000ULL)
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#define VIRTIO2 (0xFFFFFFFFBC000000ULL) /* 0x7C000000 - 0xFC000000 */
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#define VIRTIO1 (0xFFFFFFFFBD000000ULL) /* 0x7D000000 - 0xFD000000 */
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#define VIRTIO (0xFFFFFFFFBE000000ULL) /* 0x7E000000 0x3F000000 0xFE000000 */
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#define ARMLOCAL (0xFFFFFFFFBF800000ULL) /* - 0x40000000 0xFF800000 */
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#define VGPIO (0xFFFFFFFFBF900000ULL|PTEUNCACHED) /* virtual gpio for pi3 ACT LED */
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#define KZERO (0xFFFFFFFFC0000000ULL) /* kernel address space */
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#define SPINTABLE (KZERO+0xd8)
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#define CONFADDR (KZERO+0x100)
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#define REBOOTADDR (0x1c00) /* reboot code - physical address */
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#define VCBUFFER (KZERO+0x3400) /* videocore mailbox buffer */
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#define L1 (L1TOP-L1SIZE)
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#define L1SIZE ((L1TABLES+PTLEVELS-2)*BY2PG)
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#define L1TOP ((MACHADDR(MAXMACH-1)-L1TOPSIZE)&-BY2PG)
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#define MACHADDR(n) (KTZERO-((n)+1)*MACHSIZE)
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#define KTZERO (KZERO+0x80000) /* kernel text start */
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#define UZERO 0ULL /* user segment */
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#define UTZERO (UZERO+0x10000) /* user text start */
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#define USTKTOP ((EVAMASK>>1)-0xFFFF) /* user segment end +1 */
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#define USTKSIZE (16*1024*1024) /* user stack size */
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#define BLOCKALIGN 64 /* only used in allocb.c */
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/*
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* Sizes
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*/
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#define BI2BY 8 /* bits per byte */
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#define BY2SE 4
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#define BY2WD 8
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#define BY2V 8 /* only used in xalloc.c */
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#define PTEMAPMEM (1024*1024)
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#define PTEPERTAB (PTEMAPMEM/BY2PG)
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#define SEGMAPSIZE 1984
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#define SSEGMAPSIZE 16
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#define PPN(x) ((x)&~(BY2PG-1))
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#define SHARE_NONE 0
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#define SHARE_OUTER 2
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#define SHARE_INNER 3
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#define CACHE_UC 0
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#define CACHE_WB 1
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#define CACHE_WT 2
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#define CACHE_WB_NA 3
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#define MA_MEM_WB 0
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#define MA_MEM_WT 1
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#define MA_MEM_UC 2
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#define MA_DEV_nGnRnE 3
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#define MA_DEV_nGnRE 4
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#define MA_DEV_nGRE 5
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#define MA_DEV_GRE 6
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#define PTEVALID 1
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#define PTEBLOCK 0
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#define PTETABLE 2
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#define PTEPAGE 2
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#define PTEMA(x) ((x)<<2)
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#define PTEAP(x) ((x)<<6)
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#define PTESH(x) ((x)<<8)
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#define PTEAF (1<<10)
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#define PTENG (1<<11)
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#define PTEPXN (1ULL<<53)
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#define PTEUXN (1ULL<<54)
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#define PTEKERNEL PTEAP(0)
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#define PTEUSER PTEAP(1)
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#define PTEWRITE PTEAP(0)
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#define PTERONLY PTEAP(2)
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#define PTENOEXEC (PTEPXN|PTEUXN)
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#define PTECACHED PTEMA(MA_MEM_WB)
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#define PTEWT PTEMA(MA_MEM_WT)
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#define PTEUNCACHED PTEMA(MA_MEM_UC)
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#define PTEDEVICE PTEMA(MA_DEV_nGnRE)
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/*
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* Physical machine information from here on.
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* PHYS addresses as seen from the arm cpu.
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* BUS addresses as seen from the videocore gpu.
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*/
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#define PHYSDRAM 0
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#define MIN(a, b) ((a) < (b)? (a): (b))
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#define MAX(a, b) ((a) > (b)? (a): (b))
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