952 lines
18 KiB
C
952 lines
18 KiB
C
/*
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* Avanstar Xp pci uart driver
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "uartaxp.i"
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typedef struct Cc Cc;
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typedef struct Ccb Ccb;
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typedef struct Ctlr Ctlr;
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typedef struct Gcb Gcb;
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/*
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* Global Control Block.
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* Service Request fields must be accessed using XCHG.
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*/
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struct Gcb {
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u16int gcw; /* Global Command Word */
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u16int gsw; /* Global Status Word */
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u16int gsr; /* Global Service Request */
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u16int abs; /* Available Buffer Space */
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u16int bt; /* Board Type */
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u16int cpv; /* Control Program Version */
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u16int ccbn; /* Ccb count */
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u16int ccboff; /* Ccb offset */
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u16int ccbsz; /* Ccb size */
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u16int gcw2; /* Global Command Word 2 */
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u16int gsw2; /* Global Status Word 2 */
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u16int esr; /* Error Service Request */
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u16int isr; /* Input Service Request */
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u16int osr; /* Output Service Request */
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u16int msr; /* Modem Service Request */
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u16int csr; /* Command Service Request */
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};
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/*
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* Channel Control Block.
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*/
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struct Ccb {
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u16int br; /* Baud Rate */
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u16int df; /* Data Format */
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u16int lp; /* Line Protocol */
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u16int ibs; /* Input Buffer Size */
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u16int obs; /* Output Buffer Size */
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u16int ibtr; /* Ib Trigger Rate */
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u16int oblw; /* Ob Low Watermark */
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u8int ixon[2]; /* IXON characters */
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u16int ibhw; /* Ib High Watermark */
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u16int iblw; /* Ib Low Watermark */
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u16int cc; /* Channel Command */
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u16int cs; /* Channel Status */
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u16int ibsa; /* Ib Start Addr */
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u16int ibea; /* Ib Ending Addr */
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u16int obsa; /* Ob Start Addr */
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u16int obea; /* Ob Ending Addr */
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u16int ibwp; /* Ib write pointer (RO) */
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u16int ibrp; /* Ib read pointer (R/W) */
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u16int obwp; /* Ob write pointer (R/W) */
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u16int obrp; /* Ob read pointer (RO) */
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u16int ces; /* Communication Error Status */
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u16int bcp; /* Bad Character Pointer */
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u16int mc; /* Modem Control */
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u16int ms; /* Modem Status */
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u16int bs; /* Blocking Status */
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u16int crf; /* Character Received Flag */
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u8int ixoff[2]; /* IXOFF characters */
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u16int cs2; /* Channel Status 2 */
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u8int sec[2]; /* Strip/Error Characters */
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};
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enum { /* br */
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Br76800 = 0xFF00,
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Br115200 = 0xFF01,
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};
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enum { /* df */
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Db5 = 0x0000, /* Data Bits - 5 bits/byte */
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Db6 = 0x0001, /* 6 bits/byte */
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Db7 = 0x0002, /* 7 bits/byte */
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Db8 = 0x0003, /* 8 bits/byte */
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DbMASK = 0x0003,
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Sb1 = 0x0000, /* 1 Stop Bit */
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Sb2 = 0x0004, /* 2 Stop Bit */
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SbMASK = 0x0004,
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Np = 0x0000, /* No Parity */
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Op = 0x0008, /* Odd Parity */
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Ep = 0x0010, /* Even Parity */
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Mp = 0x0020, /* Mark Parity */
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Sp = 0x0030, /* Space Parity */
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PMASK = 0x0038,
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Cmn = 0x0000, /* Channel Mode Normal */
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Cme = 0x0040, /* CM Echo */
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Cmll = 0x0080, /* CM Local Loopback */
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Cmrl = 0x00C0, /* CM Remote Loopback */
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};
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enum { /* lp */
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Ixon = 0x0001, /* Obey IXON/IXOFF */
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Ixany = 0x0002, /* Any character retarts Tx */
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Ixgen = 0x0004, /* Generate IXON/IXOFF */
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Cts = 0x0008, /* CTS controls Tx */
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Dtr = 0x0010, /* Rx controls DTR */
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½d = 0x0020, /* RTS off during Tx */
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Rts = 0x0040, /* generate RTS */
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Emcs = 0x0080, /* Enable Modem Control */
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Ecs = 0x1000, /* Enable Character Stripping */
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Eia422 = 0x2000, /* EIA422 */
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};
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enum { /* cc */
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Ccu = 0x0001, /* Configure Channel and UART */
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Cco = 0x0002, /* Configure Channel Only */
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Fib = 0x0004, /* Flush Input Buffer */
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Fob = 0x0008, /* Flush Output Buffer */
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Er = 0x0010, /* Enable Receiver */
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Dr = 0x0020, /* Disable Receiver */
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Et = 0x0040, /* Enable Transmitter */
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Dt = 0x0080, /* Disable Transmitter */
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};
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enum { /* ces */
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Oe = 0x0001, /* Overrun Error */
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Pe = 0x0002, /* Parity Error */
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Fe = 0x0004, /* Framing Error */
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Br = 0x0008, /* Break Received */
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};
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enum { /* mc */
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Adtr = 0x0001, /* Assert DTR */
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Arts = 0x0002, /* Assert RTS */
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Ab = 0x0010, /* Assert BREAK */
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};
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enum { /* ms */
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Scts = 0x0001, /* Status od CTS */
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Sdsr = 0x0002, /* Status of DSR */
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Sri = 0x0004, /* Status of RI */
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Sdcd = 0x0008, /* Status of DCD */
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};
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enum { /* bs */
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Rd = 0x0001, /* Receiver Disabled */
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Td = 0x0002, /* Transmitter Disabled */
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Tbxoff = 0x0004, /* Tx Blocked by XOFF */
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Tbcts = 0x0008, /* Tx Blocked by CTS */
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Rbxoff = 0x0010, /* Rx Blocked by XOFF */
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Rbrts = 0x0020, /* Rx Blocked by RTS */
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};
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enum { /* Local Configuration */
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Range = 0x00,
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Remap = 0x04,
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Region = 0x18,
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Mb0 = 0x40, /* Mailbox 0 */
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Ldb = 0x60, /* PCI to Local Doorbell */
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Pdb = 0x64, /* Local to PCI Doorbell */
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Ics = 0x68, /* Interrupt Control/Status */
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Mcc = 0x6C, /* Misc. Command and Control */
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};
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enum { /* Mb0 */
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Edcc = 1, /* exec. downloaded code cmd */
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Aic = 0x10, /* adapter init'zed correctly */
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Cpr = 1ul << 31, /* control program ready */
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};
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enum { /* Mcc */
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Rcr = 1ul << 29, /* reload config. reg.s */
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Asr = 1ul << 30, /* pci adapter sw reset */
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Lis = 1ul << 31, /* local init status */
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};
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typedef struct Cc Cc;
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typedef struct Ccb Ccb;
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typedef struct Ctlr Ctlr;
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/*
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* Channel Control, one per uart.
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* Devuart communicates via the PhysUart functions with
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* a Uart* argument. Uart.regs is filled in by this driver
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* to point to a Cc, and Cc.ctlr points to the Axp board
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* controller.
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*/
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struct Cc {
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int uartno;
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Ccb* ccb;
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Ctlr* ctlr;
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Rendez;
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Uart;
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};
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typedef struct Ctlr {
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char* name;
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Pcidev* pcidev;
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int ctlrno;
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Ctlr* next;
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u32int* reg;
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uchar* mem;
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Gcb* gcb;
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int im; /* interrupt mask */
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Cc cc[16];
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} Ctlr;
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#define csr32r(c, r) (*((c)->reg+((r)/4)))
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#define csr32w(c, r, v) (*((c)->reg+((r)/4)) = (v))
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static Ctlr* axpctlrhead;
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static Ctlr* axpctlrtail;
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extern PhysUart axpphysuart;
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static int
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axpccdone(void* ccb)
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{
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return !((Ccb*)ccb)->cc; /* hw sets ccb->cc to zero */
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}
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static void
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axpcc(Cc* cc, int cmd)
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{
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Ccb *ccb;
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int timeo;
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u16int cs;
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ccb = cc->ccb;
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ccb->cc = cmd;
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if(!cc->ctlr->im)
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for(timeo = 0; timeo < 1000000; timeo++){
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if(!ccb->cc)
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break;
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microdelay(1);
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}
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else
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tsleep(cc, axpccdone, ccb, 1000);
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cs = ccb->cs;
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if(ccb->cc || cs){
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print("%s: cmd %#ux didn't terminate: %#ux %#ux\n",
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cc->name, cmd, ccb->cc, cs);
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if(cc->ctlr->im)
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error(Eio);
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}
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}
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static long
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axpstatus(Uart* uart, void* buf, long n, long offset)
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{
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char *p;
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Ccb *ccb;
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u16int bs, fstat, ms;
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ccb = ((Cc*)(uart->regs))->ccb;
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p = malloc(READSTR);
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bs = ccb->bs;
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fstat = ccb->df;
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ms = ccb->ms;
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snprint(p, READSTR,
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"b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
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"dev(%d) type(%d) framing(%d) overruns(%d) "
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"berr(%d) serr(%d)%s%s%s%s\n",
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uart->baud,
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uart->hup_dcd,
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ms & Sdsr,
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uart->hup_dsr,
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(fstat & DbMASK) + 5,
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0,
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(fstat & PMASK) ? ((fstat & Ep) == Ep? 'e': 'o'): 'n',
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(bs & Rbrts) ? 1 : 0,
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(fstat & Sb2) ? 2 : 1,
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0,
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uart->dev,
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uart->type,
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uart->ferr,
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uart->oerr,
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uart->berr,
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uart->serr,
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(ms & Scts) ? " cts" : "",
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(ms & Sdsr) ? " dsr" : "",
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(ms & Sdcd) ? " dcd" : "",
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(ms & Sri) ? " ring" : ""
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);
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n = readstr(offset, buf, n, p);
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free(p);
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return n;
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}
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static void
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axpfifo(Uart*, int)
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{
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}
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static void
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axpdtr(Uart* uart, int on)
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{
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Ccb *ccb;
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u16int mc;
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ccb = ((Cc*)(uart->regs))->ccb;
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mc = ccb->mc;
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if(on)
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mc |= Adtr;
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else
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mc &= ~Adtr;
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ccb->mc = mc;
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}
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/*
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* can be called from uartstageinput() during an input interrupt,
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* with uart->rlock ilocked or the uart qlocked, sometimes both.
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*/
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static void
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axprts(Uart* uart, int on)
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{
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Ccb *ccb;
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u16int mc;
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ccb = ((Cc*)(uart->regs))->ccb;
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mc = ccb->mc;
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if(on)
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mc |= Arts;
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else
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mc &= ~Arts;
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ccb->mc = mc;
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}
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static void
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axpmodemctl(Uart* uart, int on)
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{
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Ccb *ccb;
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u16int lp;
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ccb = ((Cc*)(uart->regs))->ccb;
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ilock(&uart->tlock);
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lp = ccb->lp;
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if(on){
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lp |= Cts|Rts;
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lp &= ~Emcs;
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uart->cts = ccb->ms & Scts;
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}
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else{
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lp &= ~(Cts|Rts);
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lp |= Emcs;
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uart->cts = 1;
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}
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uart->modem = on;
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iunlock(&uart->tlock);
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ccb->lp = lp;
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axpcc(uart->regs, Ccu);
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}
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static int
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axpparity(Uart* uart, int parity)
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{
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Ccb *ccb;
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u16int df;
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switch(parity){
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default:
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return -1;
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case 'e':
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parity = Ep;
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break;
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case 'o':
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parity = Op;
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break;
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case 'n':
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parity = Np;
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break;
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}
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ccb = ((Cc*)(uart->regs))->ccb;
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df = ccb->df & ~PMASK;
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ccb->df = df|parity;
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axpcc(uart->regs, Ccu);
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return 0;
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}
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static int
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axpstop(Uart* uart, int stop)
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{
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Ccb *ccb;
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u16int df;
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switch(stop){
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default:
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return -1;
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case 1:
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stop = Sb1;
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break;
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case 2:
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stop = Sb2;
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break;
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}
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ccb = ((Cc*)(uart->regs))->ccb;
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df = ccb->df & ~SbMASK;
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ccb->df = df|stop;
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axpcc(uart->regs, Ccu);
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return 0;
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}
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static int
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axpbits(Uart* uart, int bits)
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{
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Ccb *ccb;
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u16int df;
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bits -= 5;
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if(bits < 0 || bits > 3)
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return -1;
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ccb = ((Cc*)(uart->regs))->ccb;
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df = ccb->df & ~DbMASK;
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ccb->df = df|bits;
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axpcc(uart->regs, Ccu);
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return 0;
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}
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static int
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axpbaud(Uart* uart, int baud)
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{
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Ccb *ccb;
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int i, ibtr;
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/*
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* Set baud rate (high rates are special - only 16 bits).
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*/
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if(baud <= 0)
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return -1;
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uart->baud = baud;
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ccb = ((Cc*)(uart->regs))->ccb;
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switch(baud){
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default:
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ccb->br = baud;
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break;
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case 76800:
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ccb->br = Br76800;
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break;
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case 115200:
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ccb->br = Br115200;
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break;
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}
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/*
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* Set trigger level to about 50 per second.
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*/
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ibtr = baud/500;
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i = (ccb->ibea - ccb->ibsa)/2;
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if(ibtr > i)
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ibtr = i;
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ccb->ibtr = ibtr;
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axpcc(uart->regs, Ccu);
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return 0;
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}
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static void
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axpbreak(Uart* uart, int ms)
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{
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Ccb *ccb;
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u16int mc;
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/*
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* Send a break.
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*/
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if(ms <= 0)
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ms = 200;
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ccb = ((Cc*)(uart->regs))->ccb;
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mc = ccb->mc;
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ccb->mc = Ab|mc;
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tsleep(&up->sleep, return0, 0, ms);
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ccb->mc = mc & ~Ab;
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}
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/* only called from interrupt service */
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static void
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axpmc(Cc* cc)
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{
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int old;
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Ccb *ccb;
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u16int ms;
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ccb = cc->ccb;
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ms = ccb->ms;
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if(ms & Scts){
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ilock(&cc->tlock);
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old = cc->cts;
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cc->cts = ms & Scts;
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if(old == 0 && cc->cts)
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cc->ctsbackoff = 2;
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iunlock(&cc->tlock);
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}
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if(ms & Sdsr){
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old = ms & Sdsr;
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if(cc->hup_dsr && cc->dsr && !old)
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cc->dohup = 1;
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cc->dsr = old;
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}
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if(ms & Sdcd){
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old = ms & Sdcd;
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if(cc->hup_dcd && cc->dcd && !old)
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cc->dohup = 1;
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cc->dcd = old;
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}
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}
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/* called from uartkick() with uart->tlock ilocked */
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static void
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axpkick(Uart* uart)
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{
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Cc *cc;
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Ccb *ccb;
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uchar *ep, *mem, *rp, *wp, *bp;
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if(uart->cts == 0 || uart->blocked)
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return;
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cc = uart->regs;
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ccb = cc->ccb;
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mem = (uchar*)cc->ctlr->gcb;
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bp = mem + ccb->obsa;
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rp = mem + ccb->obrp;
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wp = mem + ccb->obwp;
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ep = mem + ccb->obea;
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while(wp != rp-1 && (rp != bp || wp != ep)){
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/*
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* if we've exhausted the uart's output buffer,
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* ask for more from the output queue, and quit if there
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* isn't any.
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*/
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|
if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
|
|
break;
|
|
*wp++ = *(uart->op++);
|
|
if(wp > ep)
|
|
wp = bp;
|
|
ccb->obwp = wp - mem;
|
|
}
|
|
}
|
|
|
|
/* only called from interrupt service */
|
|
static void
|
|
axprecv(Cc* cc)
|
|
{
|
|
Ccb *ccb;
|
|
uchar *ep, *mem, *rp, *wp;
|
|
|
|
ccb = cc->ccb;
|
|
|
|
mem = (uchar*)cc->ctlr->gcb;
|
|
rp = mem + ccb->ibrp;
|
|
wp = mem + ccb->ibwp;
|
|
ep = mem + ccb->ibea;
|
|
|
|
while(rp != wp){
|
|
uartrecv(cc, *rp++); /* ilocks cc->tlock */
|
|
if(rp > ep)
|
|
rp = mem + ccb->ibsa;
|
|
ccb->ibrp = rp - mem;
|
|
}
|
|
}
|
|
|
|
static void
|
|
axpinterrupt(Ureg*, void* arg)
|
|
{
|
|
int work;
|
|
Cc *cc;
|
|
Ctlr *ctlr;
|
|
u32int ics;
|
|
u16int r, sr;
|
|
|
|
work = 0;
|
|
ctlr = arg;
|
|
ics = csr32r(ctlr, Ics);
|
|
if(ics & 0x0810C000)
|
|
print("%s: unexpected interrupt %#ux\n", ctlr->name, ics);
|
|
if(!(ics & 0x00002000)) {
|
|
/* we get a steady stream of these on consoles */
|
|
// print("%s: non-doorbell interrupt\n", ctlr->name);
|
|
ctlr->gcb->gcw2 = 0x0001; /* set Gintack */
|
|
return;
|
|
}
|
|
|
|
// while(work to do){
|
|
cc = ctlr->cc;
|
|
for(sr = xchgw(&ctlr->gcb->isr, 0); sr != 0; sr >>= 1){
|
|
if(sr & 0x0001)
|
|
work++, axprecv(cc);
|
|
cc++;
|
|
}
|
|
cc = ctlr->cc;
|
|
for(sr = xchgw(&ctlr->gcb->osr, 0); sr != 0; sr >>= 1){
|
|
if(sr & 0x0001)
|
|
work++, uartkick(&cc->Uart);
|
|
cc++;
|
|
}
|
|
cc = ctlr->cc;
|
|
for(sr = xchgw(&ctlr->gcb->csr, 0); sr != 0; sr >>= 1){
|
|
if(sr & 0x0001)
|
|
work++, wakeup(cc);
|
|
cc++;
|
|
}
|
|
cc = ctlr->cc;
|
|
for(sr = xchgw(&ctlr->gcb->msr, 0); sr != 0; sr >>= 1){
|
|
if(sr & 0x0001)
|
|
work++, axpmc(cc);
|
|
cc++;
|
|
}
|
|
cc = ctlr->cc;
|
|
for(sr = xchgw(&ctlr->gcb->esr, 0); sr != 0; sr >>= 1){
|
|
if(sr & 0x0001){
|
|
r = cc->ccb->ms;
|
|
if(r & Oe)
|
|
cc->oerr++;
|
|
if(r & Pe)
|
|
cc->perr++;
|
|
if(r & Fe)
|
|
cc->ferr++;
|
|
if (r & (Oe|Pe|Fe))
|
|
work++;
|
|
}
|
|
cc++;
|
|
}
|
|
// }
|
|
/* only meaningful if we don't share the irq */
|
|
if (0 && !work)
|
|
print("%s: interrupt with no work\n", ctlr->name);
|
|
csr32w(ctlr, Pdb, 1); /* clear doorbell interrupt */
|
|
ctlr->gcb->gcw2 = 0x0001; /* set Gintack */
|
|
}
|
|
|
|
static void
|
|
axpdisable(Uart* uart)
|
|
{
|
|
Cc *cc;
|
|
u16int lp;
|
|
Ctlr *ctlr;
|
|
|
|
/*
|
|
* Turn off DTR and RTS, disable interrupts.
|
|
*/
|
|
(*uart->phys->dtr)(uart, 0);
|
|
(*uart->phys->rts)(uart, 0);
|
|
|
|
cc = uart->regs;
|
|
lp = cc->ccb->lp;
|
|
cc->ccb->lp = Emcs|lp;
|
|
axpcc(cc, Dt|Dr|Fob|Fib|Ccu);
|
|
|
|
/*
|
|
* The Uart is qlocked.
|
|
*/
|
|
ctlr = cc->ctlr;
|
|
ctlr->im &= ~(1<<cc->uartno);
|
|
if(ctlr->im == 0)
|
|
intrdisable(ctlr->pcidev->intl, axpinterrupt, ctlr,
|
|
ctlr->pcidev->tbdf, ctlr->name);
|
|
}
|
|
|
|
static void
|
|
axpenable(Uart* uart, int ie)
|
|
{
|
|
Cc *cc;
|
|
Ctlr *ctlr;
|
|
u16int lp;
|
|
|
|
cc = uart->regs;
|
|
ctlr = cc->ctlr;
|
|
|
|
/*
|
|
* Enable interrupts and turn on DTR and RTS.
|
|
* Be careful if this is called to set up a polled serial line
|
|
* early on not to try to enable interrupts as interrupt-
|
|
* -enabling mechanisms might not be set up yet.
|
|
*/
|
|
if(ie){
|
|
/*
|
|
* The Uart is qlocked.
|
|
*/
|
|
if(ctlr->im == 0){
|
|
intrenable(ctlr->pcidev->intl, axpinterrupt, ctlr,
|
|
ctlr->pcidev->tbdf, ctlr->name);
|
|
csr32w(ctlr, Ics, 0x00031F00);
|
|
csr32w(ctlr, Pdb, 1);
|
|
ctlr->gcb->gcw2 = 1;
|
|
}
|
|
ctlr->im |= 1<<cc->uartno;
|
|
}
|
|
|
|
(*uart->phys->dtr)(uart, 1);
|
|
(*uart->phys->rts)(uart, 1);
|
|
|
|
/*
|
|
* Make sure we control RTS, DTR and break.
|
|
*/
|
|
lp = cc->ccb->lp;
|
|
cc->ccb->lp = Emcs|lp;
|
|
cc->ccb->oblw = 64;
|
|
axpcc(cc, Et|Er|Ccu);
|
|
}
|
|
|
|
static void*
|
|
axpdealloc(Ctlr* ctlr)
|
|
{
|
|
int i;
|
|
|
|
for(i = 0; i < 16; i++){
|
|
if(ctlr->cc[i].name != nil)
|
|
free(ctlr->cc[i].name);
|
|
}
|
|
if(ctlr->reg != nil)
|
|
vunmap(ctlr->reg, ctlr->pcidev->mem[0].size);
|
|
if(ctlr->mem != nil)
|
|
vunmap(ctlr->mem, ctlr->pcidev->mem[2].size);
|
|
if(ctlr->name != nil)
|
|
free(ctlr->name);
|
|
free(ctlr);
|
|
|
|
return nil;
|
|
}
|
|
|
|
static Uart*
|
|
axpalloc(int ctlrno, Pcidev* pcidev)
|
|
{
|
|
Cc *cc;
|
|
uchar *p;
|
|
Ctlr *ctlr;
|
|
void *addr;
|
|
char name[64];
|
|
u32int bar, r;
|
|
int i, n, timeo;
|
|
|
|
ctlr = malloc(sizeof(Ctlr));
|
|
seprint(name, name+sizeof(name), "uartaxp%d", ctlrno);
|
|
kstrdup(&ctlr->name, name);
|
|
ctlr->pcidev = pcidev;
|
|
ctlr->ctlrno = ctlrno;
|
|
|
|
/*
|
|
* Access to runtime registers.
|
|
*/
|
|
bar = pcidev->mem[0].bar;
|
|
if((addr = vmap(bar & ~0x0F, pcidev->mem[0].size)) == 0){
|
|
print("%s: can't map registers at %#ux\n", ctlr->name, bar);
|
|
return axpdealloc(ctlr);
|
|
}
|
|
ctlr->reg = addr;
|
|
print("%s: port 0x%ux irq %d ", ctlr->name, bar, pcidev->intl);
|
|
|
|
/*
|
|
* Local address space 0.
|
|
*/
|
|
bar = pcidev->mem[2].bar;
|
|
if((addr = vmap(bar & ~0x0F, pcidev->mem[2].size)) == 0){
|
|
print("%s: can't map memory at %#ux\n", ctlr->name, bar);
|
|
return axpdealloc(ctlr);
|
|
}
|
|
ctlr->mem = addr;
|
|
ctlr->gcb = (Gcb*)(ctlr->mem+0x10000);
|
|
print("mem 0x%ux size %d: ", bar, pcidev->mem[2].size);
|
|
|
|
/*
|
|
* Toggle the software reset and wait for
|
|
* the adapter local init status to indicate done.
|
|
*
|
|
* The two 'delay(100)'s below are important,
|
|
* without them the board seems to become confused
|
|
* (perhaps it needs some 'quiet time' because the
|
|
* timeout loops are not sufficient in themselves).
|
|
*/
|
|
r = csr32r(ctlr, Mcc);
|
|
csr32w(ctlr, Mcc, r|Asr);
|
|
microdelay(1);
|
|
csr32w(ctlr, Mcc, r&~Asr);
|
|
delay(100);
|
|
|
|
for(timeo = 0; timeo < 100000; timeo++){
|
|
if(csr32r(ctlr, Mcc) & Lis)
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
if(!(csr32r(ctlr, Mcc) & Lis)){
|
|
print("%s: couldn't reset\n", ctlr->name);
|
|
return axpdealloc(ctlr);
|
|
}
|
|
print("downloading...");
|
|
/*
|
|
* Copy the control programme to the card memory.
|
|
* The card's i960 control structures live at 0xD000.
|
|
*/
|
|
if(sizeof(uartaxpcp) > 0xD000){
|
|
print("%s: control programme too big\n", ctlr->name);
|
|
return axpdealloc(ctlr);
|
|
}
|
|
/* TODO: is this right for more than 1 card? devastar does the same */
|
|
csr32w(ctlr, Remap, 0xA0000001);
|
|
for(i = 0; i < sizeof(uartaxpcp); i++)
|
|
ctlr->mem[i] = uartaxpcp[i];
|
|
/*
|
|
* Execute downloaded code and wait for it
|
|
* to signal ready.
|
|
*/
|
|
csr32w(ctlr, Mb0, Edcc);
|
|
delay(100);
|
|
/* the manual says to wait for Cpr for 1 second */
|
|
for(timeo = 0; timeo < 10000; timeo++){
|
|
if(csr32r(ctlr, Mb0) & Cpr)
|
|
break;
|
|
microdelay(100);
|
|
}
|
|
if(!(csr32r(ctlr, Mb0) & Cpr)){
|
|
print("control programme not ready; Mb0 %#ux\n",
|
|
csr32r(ctlr, Mb0));
|
|
print("%s: distribution panel not connected or card not fully seated?\n",
|
|
ctlr->name);
|
|
|
|
return axpdealloc(ctlr);
|
|
}
|
|
print("\n");
|
|
|
|
n = ctlr->gcb->ccbn;
|
|
if(ctlr->gcb->bt != 0x12 || n > 16){
|
|
print("%s: wrong board type %#ux, %d channels\n",
|
|
ctlr->name, ctlr->gcb->bt, ctlr->gcb->ccbn);
|
|
return axpdealloc(ctlr);
|
|
}
|
|
|
|
p = ((uchar*)ctlr->gcb) + ctlr->gcb->ccboff;
|
|
for(i = 0; i < n; i++){
|
|
cc = &ctlr->cc[i];
|
|
cc->ccb = (Ccb*)p;
|
|
p += ctlr->gcb->ccbsz;
|
|
cc->uartno = i;
|
|
cc->ctlr = ctlr;
|
|
|
|
cc->regs = cc; /* actually Uart->regs */
|
|
seprint(name, name+sizeof(name), "uartaxp%d%2.2d", ctlrno, i);
|
|
kstrdup(&cc->name, name);
|
|
cc->freq = 0;
|
|
cc->bits = 8;
|
|
cc->stop = 1;
|
|
cc->parity = 'n';
|
|
cc->baud = 9600;
|
|
cc->phys = &axpphysuart;
|
|
cc->console = 0;
|
|
cc->special = 0;
|
|
|
|
cc->next = &ctlr->cc[i+1];
|
|
}
|
|
ctlr->cc[n-1].next = nil;
|
|
|
|
ctlr->next = nil;
|
|
if(axpctlrhead != nil)
|
|
axpctlrtail->next = ctlr;
|
|
else
|
|
axpctlrhead = ctlr;
|
|
axpctlrtail = ctlr;
|
|
|
|
return ctlr->cc;
|
|
}
|
|
|
|
static Uart*
|
|
axppnp(void)
|
|
{
|
|
Pcidev *p;
|
|
int ctlrno;
|
|
Uart *head, *tail, *uart;
|
|
|
|
/*
|
|
* Loop through all PCI devices looking for simple serial
|
|
* controllers (ccrb == 0x07) and configure the ones which
|
|
* are familiar.
|
|
*/
|
|
head = tail = nil;
|
|
ctlrno = 0;
|
|
for(p = pcimatch(nil, 0, 0); p != nil; p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != 0x07)
|
|
continue;
|
|
|
|
switch((p->did<<16)|p->vid){
|
|
default:
|
|
continue;
|
|
case (0x6001<<16)|0x114F: /* AvanstarXp */
|
|
if((uart = axpalloc(ctlrno, p)) == nil)
|
|
continue;
|
|
break;
|
|
}
|
|
|
|
if(head != nil)
|
|
tail->next = uart;
|
|
else
|
|
head = uart;
|
|
for(tail = uart; tail->next != nil; tail = tail->next)
|
|
;
|
|
ctlrno++;
|
|
}
|
|
|
|
return head;
|
|
}
|
|
|
|
PhysUart axpphysuart = {
|
|
.name = "AvanstarXp",
|
|
.pnp = axppnp,
|
|
.enable = axpenable,
|
|
.disable = axpdisable,
|
|
.kick = axpkick,
|
|
.dobreak = axpbreak,
|
|
.baud = axpbaud,
|
|
.bits = axpbits,
|
|
.stop = axpstop,
|
|
.parity = axpparity,
|
|
.modemctl = axpmodemctl,
|
|
.rts = axprts,
|
|
.dtr = axpdtr,
|
|
.status = axpstatus,
|
|
.fifo = axpfifo,
|
|
.getc = nil,
|
|
.putc = nil,
|
|
};
|