ebf85fb7b7
fixes bug with libmemdraw where the linker would hoist the final ADD $const, SP at the end over loads from the stack causing the front to fall off once a interrupt hits.
695 lines
11 KiB
C
695 lines
11 KiB
C
#include "l.h"
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enum
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{
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E_HILO = 1<<0,
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E_FCR = 1<<1,
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E_MCR = 1<<2,
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E_MEM = 1<<3,
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E_MEMSP = 1<<4, /* uses offset and size */
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E_MEMSB = 1<<5, /* uses offset and size */
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ANYMEM = E_MEM|E_MEMSP|E_MEMSB,
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DELAY = BRANCH|LOAD|FCMP,
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};
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typedef struct Sch Sch;
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typedef struct Dep Dep;
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struct Dep
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{
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ulong ireg;
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ulong freg;
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ulong cc;
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};
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struct Sch
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{
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Prog p;
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Dep set;
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Dep used;
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long soffset;
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char size;
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char nop;
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char comp;
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};
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void regsused(Sch*, Prog*);
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int depend(Sch*, Sch*);
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int conflict(Sch*, Sch*);
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int offoverlap(Sch*, Sch*);
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void dumpbits(Sch*, Dep*);
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void
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sched(Prog *p0, Prog *pe)
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{
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Prog *p, *q;
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Sch sch[NSCHED], *s, *t, *u, *se, stmp;
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/*
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* build side structure
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*/
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s = sch;
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for(p=p0;; p=p->link) {
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memset(s, 0, sizeof(*s));
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s->p = *p;
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regsused(s, p);
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if(debug['X']) {
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Bprint(&bso, "%P\t\tset", &s->p);
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dumpbits(s, &s->set);
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Bprint(&bso, "; used");
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dumpbits(s, &s->used);
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if(s->comp)
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Bprint(&bso, "; compound");
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if(s->p.mark & LOAD)
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Bprint(&bso, "; load");
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if(s->p.mark & BRANCH)
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Bprint(&bso, "; branch");
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if(s->p.mark & FCMP)
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Bprint(&bso, "; fcmp");
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Bprint(&bso, "\n");
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}
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if(p == pe)
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break;
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s++;
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}
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se = s;
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/*
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* prepass to move things around
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* does nothing, but tries to make
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* the actual scheduler work better
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*/
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for(s=sch; s<=se; s++) {
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if(!(s->p.mark & LOAD))
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continue;
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/* always good to put nonconflict loads together */
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for(t=s+1; t<=se; t++) {
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if(!(t->p.mark & LOAD))
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continue;
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if(t->p.mark & BRANCH || t->set.ireg & (1<<REGSP))
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break;
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if(conflict(s, t))
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break;
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for(u=t-1; u>s; u--)
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if(depend(u, t))
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goto no11;
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u = s+1;
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stmp = *t;
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memmove(s+2, u, (uchar*)t - (uchar*)u);
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*u = stmp;
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break;
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}
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no11:
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/* put schedule fodder above load */
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for(t=s+1; t<=se; t++) {
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if(t->p.mark & BRANCH || t->set.ireg & (1<<REGSP))
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break;
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if(s > sch && conflict(s-1, t))
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continue;
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for(u=t-1; u>=s; u--)
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if(depend(t, u))
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goto no1;
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stmp = *t;
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memmove(s+1, s, (uchar*)t - (uchar*)s);
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*s = stmp;
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if(!(s->p.mark & LOAD))
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break;
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no1:;
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}
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}
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for(s=se; s>=sch; s--) {
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if(!(s->p.mark & DELAY))
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continue;
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if(s < se)
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if(!conflict(s, s+1))
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goto out3;
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/*
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* s is load, s+1 is immediate use of result or end of block
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* t is the trial instruction to insert between s and s+1
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*/
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if(!debug['Y'])
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for(t=s-1; t>=sch; t--) {
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if(t->comp)
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if(s->p.mark & BRANCH)
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goto no2;
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if(t->p.mark & DELAY)
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if(s >= se || conflict(t, s+1))
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goto no2;
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for(u=t+1; u<=s; u++)
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if(depend(u, t))
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goto no2;
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goto out2;
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no2:;
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}
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if(debug['X'])
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Bprint(&bso, "?l%P\n", &s->p);
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s->nop = 1;
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if(debug['v']) {
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if(s->p.mark & LOAD) {
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nop.load.count++;
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nop.load.outof++;
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}
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if(s->p.mark & BRANCH) {
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nop.branch.count++;
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nop.branch.outof++;
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}
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if(s->p.mark & FCMP) {
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nop.fcmp.count++;
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nop.fcmp.outof++;
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}
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}
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continue;
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out2:
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if(debug['X']) {
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Bprint(&bso, "!l%P\n", &t->p);
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Bprint(&bso, "%P\n", &s->p);
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}
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stmp = *t;
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memmove(t, t+1, (uchar*)s - (uchar*)t);
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*s = stmp;
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s--;
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out3:
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if(debug['v']) {
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if(s->p.mark & LOAD)
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nop.load.outof++;
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if(s->p.mark & BRANCH)
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nop.branch.outof++;
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if(s->p.mark & FCMP)
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nop.fcmp.outof++;
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}
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}
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/* Avoid HI/LO use->set */
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t = sch+1;
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for(s=sch; s<se-1; s++, t++) {
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if((s->used.cc & E_HILO) == 0)
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continue;
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if(t->set.cc & E_HILO)
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s->nop = 2;
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}
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/*
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* put it all back
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*/
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for(s=sch, p=p0; s<=se; s++, p=q) {
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q = p->link;
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if(q != s->p.link) {
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*p = s->p;
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p->link = q;
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}
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while(s->nop--)
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addnop(p);
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}
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if(debug['X']) {
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Bprint(&bso, "\n");
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Bflush(&bso);
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}
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}
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void
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regsused(Sch *s, Prog *realp)
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{
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int c, ar, ad, ld, sz;
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ulong m;
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Prog *p;
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p = &s->p;
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s->comp = compound(p);
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s->nop = 0;
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if(s->comp) {
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s->set.ireg |= 1<<REGTMP;
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s->used.ireg |= 1<<REGTMP;
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}
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ar = 0; /* dest is really reference */
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ad = 0; /* source/dest is really address */
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ld = 0; /* opcode is load instruction */
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sz = 20; /* size of load/store for overlap computation */
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/*
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* flags based on opcode
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*/
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switch(p->as) {
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case ATEXT:
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curtext = realp;
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autosize = p->to.offset + 4;
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ad = 1;
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break;
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case AJAL:
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c = p->reg;
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if(c == NREG)
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c = REGLINK;
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s->set.ireg |= 1<<c;
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ar = 1;
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ad = 1;
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break;
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case ABGEZAL:
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case ABLTZAL:
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s->set.ireg |= 1<<REGLINK;
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case ABEQ:
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case ABGEZ:
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case ABGTZ:
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case ABLEZ:
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case ABLTZ:
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case ABNE:
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ar = 1;
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ad = 1;
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break;
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case ABFPT:
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case ABFPF:
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ad = 1;
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s->used.cc |= E_FCR;
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break;
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case ACMPEQD:
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case ACMPEQF:
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case ACMPGED:
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case ACMPGEF:
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case ACMPGTD:
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case ACMPGTF:
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ar = 1;
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s->set.cc |= E_FCR;
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p->mark |= FCMP;
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break;
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case AJMP:
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ar = 1;
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ad = 1;
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break;
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case AMOVB:
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case AMOVBU:
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sz = 1;
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ld = 1;
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break;
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case AMOVH:
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case AMOVHU:
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sz = 2;
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ld = 1;
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break;
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case AMOVF:
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case AMOVW:
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case AMOVWL:
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case AMOVWR:
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sz = 4;
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ld = 1;
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break;
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case AMOVD:
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case AMOVV:
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case AMOVVL:
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case AMOVVR:
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sz = 8;
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ld = 1;
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break;
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case ADIV:
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case ADIVU:
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case AMUL:
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case AMULU:
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case AREM:
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case AREMU:
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s->set.cc = E_HILO;
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case AADD:
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case AADDU:
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case AAND:
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case ANOR:
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case AOR:
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case ASGT:
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case ASGTU:
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case ASLL:
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case ASRA:
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case ASRL:
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case ASUB:
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case ASUBU:
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case AXOR:
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case AADDD:
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case AADDF:
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case AADDW:
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case ASUBD:
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case ASUBF:
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case ASUBW:
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case AMULF:
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case AMULD:
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case AMULW:
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case ADIVF:
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case ADIVD:
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case ADIVW:
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if(p->reg == NREG) {
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if(p->to.type == D_REG || p->to.type == D_FREG)
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p->reg = p->to.reg;
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if(p->reg == NREG)
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print("botch %P\n", p);
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}
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break;
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}
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/*
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* flags based on 'to' field
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*/
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c = p->to.class;
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if(c == 0) {
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c = aclass(&p->to) + 1;
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p->to.class = c;
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}
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c--;
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switch(c) {
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default:
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print("unknown class %d %D\n", c, &p->to);
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case C_ZCON:
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case C_SCON:
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case C_ADD0CON:
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case C_AND0CON:
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case C_ADDCON:
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case C_ANDCON:
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case C_UCON:
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case C_LCON:
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case C_NONE:
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case C_SBRA:
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case C_LBRA:
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break;
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case C_HI:
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case C_LO:
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s->set.cc |= E_HILO;
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break;
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case C_FCREG:
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s->set.cc |= E_FCR;
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break;
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case C_MREG:
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s->set.cc |= E_MCR;
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break;
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case C_ZOREG:
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case C_SOREG:
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case C_LOREG:
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c = p->to.reg;
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s->used.ireg |= 1<<c;
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if(ad)
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break;
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s->size = sz;
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s->soffset = regoff(&p->to);
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m = ANYMEM;
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if(c == REGSB)
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m = E_MEMSB;
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if(c == REGSP)
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m = E_MEMSP;
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if(ar)
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s->used.cc |= m;
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else
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s->set.cc |= m;
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break;
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case C_SACON:
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case C_LACON:
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s->used.ireg |= 1<<REGSP;
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break;
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case C_SECON:
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case C_LECON:
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s->used.ireg |= 1<<REGSB;
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break;
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case C_REG:
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if(ar)
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s->used.ireg |= 1<<p->to.reg;
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else
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s->set.ireg |= 1<<p->to.reg;
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break;
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case C_FREG:
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/* do better -- determine double prec */
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if(ar) {
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s->used.freg |= 1<<p->to.reg;
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s->used.freg |= 1<<(p->to.reg|1);
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} else {
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s->set.freg |= 1<<p->to.reg;
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s->set.freg |= 1<<(p->to.reg|1);
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}
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if(ld && p->from.type == D_REG)
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p->mark |= LOAD;
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break;
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case C_SAUTO:
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case C_LAUTO:
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s->used.ireg |= 1<<REGSP;
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if(ad)
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break;
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s->size = sz;
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s->soffset = regoff(&p->to);
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if(ar)
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s->used.cc |= E_MEMSP;
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else
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s->set.cc |= E_MEMSP;
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break;
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case C_SEXT:
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case C_LEXT:
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s->used.ireg |= 1<<REGSB;
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if(ad)
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break;
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s->size = sz;
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s->soffset = regoff(&p->to);
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if(ar)
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s->used.cc |= E_MEMSB;
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else
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s->set.cc |= E_MEMSB;
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break;
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}
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/*
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* flags based on 'from' field
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*/
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c = p->from.class;
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if(c == 0) {
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c = aclass(&p->from) + 1;
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p->from.class = c;
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}
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c--;
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switch(c) {
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default:
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print("unknown class %d %D\n", c, &p->from);
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case C_ZCON:
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case C_SCON:
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case C_ADD0CON:
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case C_AND0CON:
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case C_ADDCON:
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case C_ANDCON:
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case C_UCON:
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case C_LCON:
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case C_NONE:
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case C_SBRA:
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case C_LBRA:
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break;
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case C_HI:
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case C_LO:
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s->used.cc |= E_HILO;
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break;
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case C_FCREG:
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s->used.cc |= E_FCR;
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break;
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case C_MREG:
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s->used.cc |= E_MCR;
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break;
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case C_ZOREG:
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case C_SOREG:
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case C_LOREG:
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c = p->from.reg;
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s->used.ireg |= 1<<c;
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if(ld)
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p->mark |= LOAD;
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s->size = sz;
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s->soffset = regoff(&p->from);
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m = ANYMEM;
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if(c == REGSB)
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m = E_MEMSB;
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if(c == REGSP)
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m = E_MEMSP;
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s->used.cc |= m;
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break;
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case C_SACON:
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case C_LACON:
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s->used.ireg |= 1<<REGSP;
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break;
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case C_SECON:
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case C_LECON:
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s->used.ireg |= 1<<REGSB;
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break;
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case C_REG:
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s->used.ireg |= 1<<p->from.reg;
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break;
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case C_FREG:
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/* do better -- determine double prec */
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s->used.freg |= 1<<p->from.reg;
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s->used.freg |= 1<<(p->from.reg|1);
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if(ld && p->to.type == D_REG)
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p->mark |= LOAD;
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break;
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case C_SAUTO:
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case C_LAUTO:
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s->used.ireg |= 1<<REGSP;
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if(ld)
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p->mark |= LOAD;
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if(ad)
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break;
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s->size = sz;
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s->soffset = regoff(&p->from);
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s->used.cc |= E_MEMSP;
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break;
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case C_SEXT:
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case C_LEXT:
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s->used.ireg |= 1<<REGSB;
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if(ld)
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p->mark |= LOAD;
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if(ad)
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break;
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s->size = sz;
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s->soffset = regoff(&p->from);
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s->used.cc |= E_MEMSB;
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break;
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}
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c = p->reg;
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if(c != NREG) {
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if(p->from.type == D_FREG || p->to.type == D_FREG) {
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s->used.freg |= 1<<c;
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s->used.freg |= 1<<(c|1);
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} else
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s->used.ireg |= 1<<c;
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}
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s->set.ireg &= ~(1<<REGZERO); /* R0 cant be set */
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}
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/*
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* test to see if 2 instrictions can be
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* interchanged without changing semantics
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*/
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int
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depend(Sch *sa, Sch *sb)
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{
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ulong x;
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|
|
if(sa->set.ireg & (sb->set.ireg|sb->used.ireg))
|
|
return 1;
|
|
if(sb->set.ireg & sa->used.ireg)
|
|
return 1;
|
|
|
|
if(sa->set.freg & (sb->set.freg|sb->used.freg))
|
|
return 1;
|
|
if(sb->set.freg & sa->used.freg)
|
|
return 1;
|
|
|
|
/*
|
|
* special case.
|
|
* loads from same address cannot pass.
|
|
* this is for hardware fifo's and the like
|
|
*/
|
|
if(sa->used.cc & sb->used.cc & E_MEM)
|
|
if(sa->p.reg == sb->p.reg)
|
|
if(regoff(&sa->p.from) == regoff(&sb->p.from))
|
|
return 1;
|
|
|
|
x = (sa->set.cc & (sb->set.cc|sb->used.cc)) |
|
|
(sb->set.cc & sa->used.cc);
|
|
if(x) {
|
|
/*
|
|
* allow SB and SP to pass each other.
|
|
* allow SB to pass SB iff doffsets are ok
|
|
* anything else conflicts
|
|
*/
|
|
if(x != E_MEMSP && x != E_MEMSB)
|
|
return 1;
|
|
x = sa->set.cc | sb->set.cc |
|
|
sa->used.cc | sb->used.cc;
|
|
if(x & E_MEM)
|
|
return 1;
|
|
if(offoverlap(sa, sb))
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
offoverlap(Sch *sa, Sch *sb)
|
|
{
|
|
|
|
if(sa->soffset < sb->soffset) {
|
|
if(sa->soffset+sa->size > sb->soffset)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
if(sb->soffset+sb->size > sa->soffset)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* test 2 adjacent instructions
|
|
* and find out if inserted instructions
|
|
* are desired to prevent stalls.
|
|
*/
|
|
int
|
|
conflict(Sch *sa, Sch *sb)
|
|
{
|
|
if(sa->set.ireg & sb->used.ireg)
|
|
return 1;
|
|
if(sa->set.freg & sb->used.freg)
|
|
return 1;
|
|
if(sa->set.cc & sb->used.cc)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
compound(Prog *p)
|
|
{
|
|
Optab *o;
|
|
|
|
o = oplook(p);
|
|
if(o->size != 4)
|
|
return 1;
|
|
if(p->to.type == D_REG && p->to.reg == REGSB)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
dumpbits(Sch *s, Dep *d)
|
|
{
|
|
int i;
|
|
|
|
for(i=0; i<32; i++)
|
|
if(d->ireg & (1<<i))
|
|
Bprint(&bso, " R%d", i);
|
|
for(i=0; i<32; i++)
|
|
if(d->freg & (1<<i))
|
|
Bprint(&bso, " F%d", i);
|
|
for(i=0; i<32; i++)
|
|
switch(d->cc & (1<<i)) {
|
|
default:
|
|
break;
|
|
case E_HILO:
|
|
Bprint(&bso, " HILO");
|
|
break;
|
|
case E_FCR:
|
|
Bprint(&bso, " FCR");
|
|
break;
|
|
case E_MCR:
|
|
Bprint(&bso, " MCR");
|
|
break;
|
|
case E_MEM:
|
|
Bprint(&bso, " MEM%d", s->size);
|
|
break;
|
|
case E_MEMSB:
|
|
Bprint(&bso, " SB%d", s->size);
|
|
break;
|
|
case E_MEMSP:
|
|
Bprint(&bso, " SP%d", s->size);
|
|
break;
|
|
}
|
|
}
|