61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
this is a plan 9 port to the Trimslice with tegra2 soc: dual-core,
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dual-issue 1GHz Cortex-A9 system (v7a arch).
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dram is 1GB at 0.
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linux believes that u-boot runs in the bottom 4MB.
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the l2 cache is a non-architectural bag nailed on the side.
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mp arm systems have a generic interrupt controller; this one is gic v1(!).
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vfp 3 floating-point is present.
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section numbers (§) are in the tegra 2 tech. ref. man.
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for a minimal cpu server, need these devices to work:
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clock signals §5 (leave to u-boot),
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pad mux + gpio crap §8, §11 and §18 (leave to u-boot),
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☑ 1 cpu §13,
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☑ uart (16[45]50) §22,
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☑ gic (gic.v1.pdf),
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☑ clock §6—7,
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☑ ether8169 via pcie §31.
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then add these:
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☑ 2nd cpu (cortex.a9.mpcore.pdf),
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☑ l2 cache (l2cache.pl310.pdf, errata),
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☑ fpu (cortex.a9.fp.pdf),
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☑ user profiling,
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kprof,
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in-line 64-bit arithmetic,
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eventually might want:
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usb (e.g., for sata) §26,
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nor flash §17,
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video §29,
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and the really horrid ones:
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nand flash §16,
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mmc §25.
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physical memory map
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0 1GB ram
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40000000 256K iram (audio/video memory)
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50000000 cortex-a9 cpu regs, periphbase, intr distrib, memsel,
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l2 cache
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54000000 graphics regs
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58000000 gart (graphics window)
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60000000 256MB ppsb bus dev regs, including semas, intr ctlr, dma,
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arm7 cache, gpio, except. vects
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70000000 256MB apc bus regs, including uarts, nand, nor, spi, rtc
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80000000 1GB ahb extern mem, pcie for cpu only
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90000000-97ffffff pcie 0 mem(?)
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a0000000-a7ffffff pcie 0 prefetch mem, includes rtl8111dl ether(?)
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a0020000 ether region 4
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a0024000 ether region 2
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c0000000 256MB ahb bus virtual b0000000
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c3000000-c80007ff 81MB ide, usb, sata, mmc
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d0000000 256MB nor flash virtual 40000000
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f000f000 4K mmu tlb
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fff00000 48K irom boot code
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ffff0000 64K high vectors
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use 0xc0000000 as KZERO.
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