e4ce6aadac
we might as well handle the per process cycle counter in the portable part instead of duplicating the code in every arch and have inconsistent implementations. we now have a portable kenter() and kexit() function, that is ment to be used in trap/syscall from user, which updates the counters. some kernels missed initializing Mach.cyclefreq.
1079 lines
23 KiB
C
1079 lines
23 KiB
C
/*
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* arm mpcore generic interrupt controller (gic) v1
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* traps, exceptions, interrupts, system calls.
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*
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* there are two pieces: the interrupt distributor and the cpu interface.
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*
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* memset or memmove on any of the distributor registers generates an
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* exception like this one:
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* panic: external abort 0x28 pc 0xc048bf68 addr 0x50041800
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*
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* we use l1 and l2 cache ops to force vectors to be visible everywhere.
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*
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* apparently irqs 0—15 (SGIs) are always enabled.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "../port/error.h"
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#include "ureg.h"
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#include "arm.h"
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#define ISSGI(irq) ((uint)(irq) < Nsgi)
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enum {
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Debug = 0,
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Nvec = 8, /* # of vectors at start of lexception.s */
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Bi2long = BI2BY * sizeof(long),
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Nirqs = 1024,
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Nsgi = 16, /* software-generated (inter-processor) intrs */
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Nppi = 32, /* sgis + other private peripheral intrs */
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};
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typedef struct Intrcpuregs Intrcpuregs;
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typedef struct Intrdistregs Intrdistregs;
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/*
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* almost this entire register set is buggered.
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* the distributor is supposed to be per-system, not per-cpu,
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* yet some registers are banked per-cpu, as marked.
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*/
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struct Intrdistregs { /* distributor */
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ulong ctl;
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ulong ctlrtype;
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ulong distid;
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uchar _pad0[0x80 - 0xc];
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/* botch: *[0] are banked per-cpu from here */
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/* bit maps */
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ulong grp[32]; /* in group 1 (non-secure) */
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ulong setena[32]; /* forward to cpu interfaces */
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ulong clrena[32];
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ulong setpend[32];
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ulong clrpend[32];
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ulong setact[32]; /* active? */
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ulong clract[32];
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/* botch: *[0] are banked per-cpu until here */
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uchar pri[1020]; /* botch: pri[0] — pri[7] are banked per-cpu */
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ulong _rsrvd1;
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/* botch: targ[0] through targ[7] are banked per-cpu and RO */
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uchar targ[1020]; /* byte bit maps: cpu targets indexed by intr */
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ulong _rsrvd2;
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/* botch: cfg[1] is banked per-cpu */
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ulong cfg[64]; /* bit pairs: edge? 1-N? */
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ulong _pad1[64];
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ulong nsac[64]; /* bit pairs (v2 only) */
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/* software-generated intrs (a.k.a. sgi) */
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ulong swgen; /* intr targets */
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uchar _pad2[0xf10 - 0xf04];
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uchar clrsgipend[16]; /* bit map (v2 only) */
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uchar setsgipend[16]; /* bit map (v2 only) */
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};
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enum {
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/* ctl bits */
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Forw2cpuif = 1,
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/* ctlrtype bits */
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Cpunoshft = 5,
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Cpunomask = MASK(3),
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Intrlines = MASK(5),
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/* cfg bits */
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Level = 0<<1,
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Edge = 1<<1, /* edge-, not level-sensitive */
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Toall = 0<<0,
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To1 = 1<<0, /* vs. to all */
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/* swgen bits */
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Totargets = 0,
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Tonotme = 1<<24,
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Tome = 2<<24,
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};
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/* each cpu sees its own registers at the same base address (soc.intr) */
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struct Intrcpuregs {
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ulong ctl;
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ulong primask;
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ulong binpt; /* group pri vs subpri split */
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ulong ack;
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ulong end;
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ulong runpri;
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ulong hipripend;
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/* aliased regs (secure, for group 1) */
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ulong alibinpt;
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ulong aliack; /* (v2 only) */
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ulong aliend; /* (v2 only) */
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ulong alihipripend; /* (v2 only) */
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uchar _pad0[0xd0 - 0x2c];
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ulong actpri[4]; /* (v2 only) */
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ulong nsactpri[4]; /* (v2 only) */
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uchar _pad0[0xfc - 0xf0];
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ulong ifid; /* ro */
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uchar _pad0[0x1000 - 0x100];
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ulong deact; /* wo (v2 only) */
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};
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enum {
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/* ctl bits */
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Enable = 1,
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Eoinodeact = 1<<9, /* (v2 only) */
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/* (ali) ack/end/hipriend/deact bits */
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Intrmask = MASK(10),
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Cpuidshift = 10,
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Cpuidmask = MASK(3),
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/* ifid bits */
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Archversshift = 16,
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Archversmask = MASK(4),
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};
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typedef struct Vctl Vctl;
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typedef struct Vctl {
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Vctl* next; /* handlers on this vector */
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char *name; /* of driver, xallocated */
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void (*f)(Ureg*, void*); /* handler to call */
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void* a; /* argument to call it with */
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} Vctl;
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static Lock vctllock;
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static Vctl* vctl[Nirqs];
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/*
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* Layout at virtual address 0.
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*/
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typedef struct Vpage0 {
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void (*vectors[Nvec])(void);
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u32int vtable[Nvec];
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} Vpage0;
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enum
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{
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Ntimevec = 20 /* number of time buckets for each intr */
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};
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ulong intrtimes[Nirqs][Ntimevec];
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uvlong ninterrupt;
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uvlong ninterruptticks;
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int irqtooearly = 1;
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static ulong shadena[32]; /* copy of enable bits, saved by intcmaskall */
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static Lock distlock, nintrlock;
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extern int notify(Ureg*);
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static void dumpstackwithureg(Ureg *ureg);
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void
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printrs(int base, ulong word)
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{
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int bit;
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for (bit = 0; word; bit++, word >>= 1)
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if (word & 1)
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iprint(" %d", base + bit);
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}
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void
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dumpintrs(char *what, ulong *bits)
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{
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int i, first, some;
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ulong word;
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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first = 1;
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some = 0;
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USED(idp);
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for (i = 0; i < nelem(idp->setpend); i++) {
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word = bits[i];
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if (word) {
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if (first) {
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first = 0;
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iprint("%s", what);
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}
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some = 1;
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printrs(i * Bi2long, word);
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}
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}
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if (!some)
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iprint("%s none", what);
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iprint("\n");
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}
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void
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dumpintrpend(void)
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{
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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iprint("\ncpu%d gic regs:\n", m->machno);
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dumpintrs("group 1", idp->grp);
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dumpintrs("enabled", idp->setena);
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dumpintrs("pending", idp->setpend);
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dumpintrs("active ", idp->setact);
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}
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/*
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* keep histogram of interrupt service times
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*/
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void
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intrtime(Mach*, int vno)
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{
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ulong diff;
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ulong x;
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x = perfticks();
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diff = x - m->perf.intrts;
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m->perf.intrts = x;
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m->perf.inintr += diff;
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if(up == nil && m->perf.inidle > diff)
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m->perf.inidle -= diff;
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if (m->cpumhz == 0)
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return; /* don't divide by zero */
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diff /= m->cpumhz*100; /* quantum = 100µsec */
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if(diff >= Ntimevec)
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diff = Ntimevec-1;
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if ((uint)vno >= Nirqs)
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vno = Nirqs-1;
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intrtimes[vno][diff]++;
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}
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static ulong
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intack(Intrcpuregs *icp)
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{
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return icp->ack & Intrmask;
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}
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static void
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intdismiss(Intrcpuregs *icp, ulong ack)
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{
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icp->end = ack;
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coherence();
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}
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static int
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irqinuse(uint irq)
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{
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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return idp->setena[irq / Bi2long] & (1 << (irq % Bi2long));
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}
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void
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intcunmask(uint irq)
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{
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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ilock(&distlock);
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idp->setena[irq / Bi2long] = 1 << (irq % Bi2long);
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iunlock(&distlock);
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}
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void
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intcmask(uint irq)
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{
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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ilock(&distlock);
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idp->clrena[irq / Bi2long] = 1 << (irq % Bi2long);
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iunlock(&distlock);
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}
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static void
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intcmaskall(Intrdistregs *idp) /* mask all intrs for all cpus */
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{
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int i;
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for (i = 0; i < nelem(idp->setena); i++)
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shadena[i] = idp->setena[i];
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for (i = 0; i < nelem(idp->clrena); i++)
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idp->clrena[i] = ~0;
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coherence();
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}
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static void
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intcunmaskall(Intrdistregs *idp) /* unused */
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{
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int i;
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for (i = 0; i < nelem(idp->setena); i++)
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idp->setena[i] = shadena[i];
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coherence();
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}
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static ulong
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permintrs(Intrdistregs *idp, int base, int r)
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{
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ulong perms;
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idp->clrena[r] = ~0; /* disable all */
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coherence();
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perms = idp->clrena[r];
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if (perms) {
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iprint("perm intrs:");
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printrs(base, perms);
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iprint("\n");
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}
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return perms;
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}
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static void
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intrcfg(Intrdistregs *idp)
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{
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int i, cpumask;
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ulong pat;
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/* set up all interrupts as level-sensitive, to one cpu (0) */
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pat = 0;
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for (i = 0; i < Bi2long; i += 2)
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pat |= (Level | To1) << i;
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if (m->machno == 0) { /* system-wide & cpu0 cfg */
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for (i = 0; i < nelem(idp->grp); i++)
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idp->grp[i] = 0; /* secure */
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for (i = 0; i < nelem(idp->pri); i++)
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idp->pri[i] = 0; /* highest priority */
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/* set up all interrupts as level-sensitive, to one cpu (0) */
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for (i = 0; i < nelem(idp->cfg); i++)
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idp->cfg[i] = pat;
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/* first Nppi are read-only for SGIs and PPIs */
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cpumask = 1<<0; /* just cpu 0 */
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navailcpus = getncpus();
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for (i = Nppi; i < sizeof idp->targ; i++)
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idp->targ[i] = cpumask;
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coherence();
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intcmaskall(idp);
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for (i = 0; i < nelem(idp->clrena); i++) {
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// permintrs(idp, i * Bi2long, i);
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idp->clrpend[i] = idp->clract[i] = idp->clrena[i] = ~0;
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}
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} else { /* per-cpu config */
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idp->grp[0] = 0; /* secure */
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for (i = 0; i < 8; i++)
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idp->pri[i] = 0; /* highest priority */
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/* idp->targ[0 through Nppi-1] are supposed to be read-only */
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for (i = 0; i < Nppi; i++)
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idp->targ[i] = 1<<m->machno;
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idp->cfg[1] = pat;
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coherence();
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// permintrs(idp, i * Bi2long, i);
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idp->clrpend[0] = idp->clract[0] = idp->clrena[0] = ~0;
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/* on cpu1, irq Extpmuirq (118) is always pending here */
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}
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coherence();
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}
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void
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intrto(int cpu, int irq)
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{
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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/* first Nppi are read-only for SGIs and the like */
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ilock(&distlock);
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idp->targ[irq] = 1 << cpu;
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iunlock(&distlock);
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}
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void
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intrsto(int cpu) /* unused */
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{
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int i;
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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/* first Nppi are read-only for SGIs and the like */
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for (i = Nppi; i < sizeof idp->targ; i++)
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intrto(cpu, i);
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USED(idp);
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}
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void
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intrcpu(int cpu)
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{
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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ilock(&distlock);
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idp->swgen = Totargets | 1 << (cpu + 16) | m->machno;
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iunlock(&distlock);
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}
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/*
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* set up for exceptions
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*/
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void
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trapinit(void)
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{
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int s;
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Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
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Intrcpuregs *icp = (Intrcpuregs *)soc.intr;
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Vpage0 *vpage0;
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enum { Vecsize = sizeof vpage0->vectors + sizeof vpage0->vtable, };
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|
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/*
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* set up the exception vectors, high and low.
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*
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* we can't use cache ops on HVECTORS address, since they
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* work on virtual addresses, and only those that have a
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* physical address == PADDR(virtual).
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*/
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if (m->machno == 0) {
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vpage0 = (Vpage0*)HVECTORS;
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memmove(vpage0->vectors, vectors, sizeof(vpage0->vectors));
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memmove(vpage0->vtable, vtable, sizeof(vpage0->vtable));
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vpage0 = (Vpage0*)KADDR(0);
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memmove(vpage0->vectors, vectors, sizeof(vpage0->vectors));
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memmove(vpage0->vtable, vtable, sizeof(vpage0->vtable));
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|
|
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allcache->wbse(vpage0, Vecsize);
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cacheiinv();
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}
|
|
|
|
/*
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* set up the stack pointers for the exception modes for this cpu.
|
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* they point to small `save areas' in Mach, not actual stacks.
|
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*/
|
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s = splhi(); /* make these modes ignore intrs too */
|
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setr13(PsrMfiq, m->sfiq);
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setr13(PsrMirq, m->sirq);
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setr13(PsrMmon, m->smon);
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setr13(PsrMabt, m->sabt);
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setr13(PsrMund, m->sund);
|
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setr13(PsrMsys, m->ssys);
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splx(s);
|
|
|
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assert((idp->distid & MASK(12)) == 0x43b); /* made by arm */
|
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assert((icp->ifid & MASK(12)) == 0x43b); /* made by arm */
|
|
|
|
ilock(&distlock);
|
|
idp->ctl = 0;
|
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icp->ctl = 0;
|
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coherence();
|
|
|
|
intrcfg(idp); /* some per-cpu cfg here */
|
|
|
|
icp->ctl = Enable;
|
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icp->primask = (uchar)~0; /* let all priorities through */
|
|
coherence();
|
|
|
|
idp->ctl = Forw2cpuif;
|
|
iunlock(&distlock);
|
|
}
|
|
|
|
void
|
|
intrsoff(void)
|
|
{
|
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ilock(&distlock);
|
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intcmaskall((Intrdistregs *)soc.intrdist);
|
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iunlock(&distlock);
|
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}
|
|
|
|
void
|
|
intrcpushutdown(void)
|
|
{
|
|
Intrcpuregs *icp = (Intrcpuregs *)soc.intr;
|
|
|
|
icp->ctl = 0;
|
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icp->primask = 0; /* let no priorities through */
|
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coherence();
|
|
}
|
|
|
|
/* called from cpu0 after other cpus are shutdown */
|
|
void
|
|
intrshutdown(void)
|
|
{
|
|
Intrdistregs *idp = (Intrdistregs *)soc.intrdist;
|
|
|
|
intrsoff();
|
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idp->ctl = 0;
|
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intrcpushutdown();
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}
|
|
|
|
/*
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* enable an irq interrupt
|
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* note that the same private interrupt may be enabled on multiple cpus
|
|
*/
|
|
int
|
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irqenable(uint irq, void (*f)(Ureg*, void*), void* a, char *name)
|
|
{
|
|
Vctl *v;
|
|
|
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if(irq >= nelem(vctl))
|
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panic("irqenable irq %d", irq);
|
|
|
|
if (irqtooearly) {
|
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iprint("irqenable for %d %s called too early\n", irq, name);
|
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return -1;
|
|
}
|
|
/*
|
|
* if in use, could be a private interrupt on a secondary cpu,
|
|
* so don't add anything to the vector chain. irqs should
|
|
* otherwise be one-to-one with devices.
|
|
*/
|
|
if(!ISSGI(irq) && irqinuse(irq)) {
|
|
lock(&vctllock);
|
|
if (vctl[irq] == nil) {
|
|
dumpintrpend();
|
|
panic("non-sgi irq %d in use yet no Vctl allocated", irq);
|
|
}
|
|
unlock(&vctllock);
|
|
}
|
|
/* could be 1st use of this irq or could be an sgi (always in use) */
|
|
else if (vctl[irq] == nil) {
|
|
v = malloc(sizeof(Vctl));
|
|
if (v == nil)
|
|
panic("irqenable: malloc Vctl");
|
|
v->f = f;
|
|
v->a = a;
|
|
v->name = malloc(strlen(name)+1);
|
|
if (v->name == nil)
|
|
panic("irqenable: malloc name");
|
|
strcpy(v->name, name);
|
|
|
|
lock(&vctllock);
|
|
if (vctl[irq] != nil) {
|
|
/* allocation race: someone else did it first */
|
|
free(v->name);
|
|
free(v);
|
|
} else {
|
|
v->next = vctl[irq];
|
|
vctl[irq] = v;
|
|
}
|
|
unlock(&vctllock);
|
|
}
|
|
intcunmask(irq);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* disable an irq interrupt
|
|
*/
|
|
int
|
|
irqdisable(uint irq, void (*f)(Ureg*, void*), void* a, char *name)
|
|
{
|
|
Vctl **vp, *v;
|
|
|
|
if(irq >= nelem(vctl))
|
|
panic("irqdisable irq %d", irq);
|
|
|
|
lock(&vctllock);
|
|
for(vp = &vctl[irq]; v = *vp; vp = &v->next)
|
|
if (v->f == f && v->a == a && strcmp(v->name, name) == 0){
|
|
print("irqdisable: remove %s\n", name);
|
|
*vp = v->next;
|
|
free(v->name);
|
|
free(v);
|
|
break;
|
|
}
|
|
|
|
if(v == nil)
|
|
print("irqdisable: irq %d, name %s not enabled\n", irq, name);
|
|
if(vctl[irq] == nil){
|
|
print("irqdisable: clear icmr bit %d\n", irq);
|
|
intcmask(irq);
|
|
}
|
|
unlock(&vctllock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* called by trap to handle access faults
|
|
*/
|
|
static void
|
|
faultarm(Ureg *ureg, uintptr va, int user, int read)
|
|
{
|
|
int n, insyscall;
|
|
|
|
if(up == nil) {
|
|
dumpstackwithureg(ureg);
|
|
panic("faultarm: cpu%d: nil up, %sing %#p at %#p",
|
|
m->machno, (read? "read": "writ"), va, ureg->pc);
|
|
}
|
|
insyscall = up->insyscall;
|
|
up->insyscall = 1;
|
|
|
|
n = fault(va, ureg->pc, read); /* goes spllo */
|
|
splhi();
|
|
if(n < 0){
|
|
char buf[ERRMAX];
|
|
|
|
if(!user){
|
|
dumpstackwithureg(ureg);
|
|
panic("fault: cpu%d: kernel %sing %#p at %#p",
|
|
m->machno, read? "read": "writ", va, ureg->pc);
|
|
}
|
|
/* don't dump registers; programs suicide all the time */
|
|
snprint(buf, sizeof buf, "sys: trap: fault %s va=%#p",
|
|
read? "read": "write", va);
|
|
postnote(up, 1, buf, NDebug);
|
|
}
|
|
up->insyscall = insyscall;
|
|
}
|
|
|
|
/*
|
|
* called by trap to handle interrupts.
|
|
* returns true iff a clock interrupt, thus maybe reschedule.
|
|
*/
|
|
static int
|
|
irq(Ureg* ureg)
|
|
{
|
|
int clockintr, ack;
|
|
uint irqno, handled, t, ticks;
|
|
Intrcpuregs *icp = (Intrcpuregs *)soc.intr;
|
|
Vctl *v;
|
|
|
|
ticks = perfticks();
|
|
handled = 0;
|
|
ack = intack(icp);
|
|
irqno = ack & Intrmask;
|
|
|
|
if (irqno >= nelem(vctl)) {
|
|
iprint("trap: irq %d >= # vectors (%d)\n", irqno, nelem(vctl));
|
|
intdismiss(icp, ack);
|
|
return 0;
|
|
}
|
|
|
|
if (irqno == Loctmrirq) /* this is a clock intr? */
|
|
m->inclockintr++; /* yes, count nesting */
|
|
if(m->machno && m->inclockintr > 1) {
|
|
iprint("cpu%d: nested clock intrs\n", m->machno);
|
|
m->inclockintr--;
|
|
intdismiss(icp, ack);
|
|
return 0;
|
|
}
|
|
|
|
for(v = vctl[irqno]; v != nil; v = v->next)
|
|
if (v->f) {
|
|
if (islo())
|
|
panic("trap: pl0 before trap handler for %s",
|
|
v->name);
|
|
v->f(ureg, v->a);
|
|
if (islo())
|
|
panic("trap: %s lowered pl", v->name);
|
|
// splhi(); /* in case v->f lowered pl */
|
|
handled++;
|
|
}
|
|
if(!handled)
|
|
if (irqno >= 1022)
|
|
iprint("cpu%d: ignoring spurious interrupt\n", m->machno);
|
|
else {
|
|
intcmask(irqno);
|
|
iprint("cpu%d: unexpected interrupt %d, now masked\n",
|
|
m->machno, irqno);
|
|
}
|
|
t = perfticks();
|
|
if (0) { /* left over from another port? */
|
|
ilock(&nintrlock);
|
|
ninterrupt++;
|
|
if(t < ticks)
|
|
ninterruptticks += ticks-t;
|
|
else
|
|
ninterruptticks += t-ticks;
|
|
iunlock(&nintrlock);
|
|
}
|
|
USED(t, ticks);
|
|
clockintr = m->inclockintr == 1;
|
|
if (irqno == Loctmrirq)
|
|
m->inclockintr--;
|
|
|
|
intdismiss(icp, ack);
|
|
intrtime(m, irqno);
|
|
return clockintr;
|
|
}
|
|
|
|
/*
|
|
* returns 1 if the instruction writes memory, 0 otherwise
|
|
*/
|
|
int
|
|
writetomem(ulong inst)
|
|
{
|
|
/* swap always write memory */
|
|
if((inst & 0x0FC00000) == 0x01000000)
|
|
return 1;
|
|
|
|
/* loads and stores are distinguished by bit 20 */
|
|
if(inst & (1<<20))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
datafault(Ureg *ureg, int user)
|
|
{
|
|
int x;
|
|
ulong inst, fsr;
|
|
uintptr va;
|
|
|
|
va = farget();
|
|
|
|
if (m->probing && !user) {
|
|
if (m->trapped++ > 0) {
|
|
dumpstackwithureg(ureg);
|
|
panic("trap: recursive probe %#lux", va);
|
|
}
|
|
ureg->pc += 4; /* continue after faulting instr'n */
|
|
return;
|
|
}
|
|
|
|
inst = *(ulong*)(ureg->pc);
|
|
/* bits 12 and 10 have to be concatenated with status */
|
|
x = fsrget();
|
|
fsr = (x>>7) & 0x20 | (x>>6) & 0x10 | x & 0xf;
|
|
switch(fsr){
|
|
default:
|
|
case 0xa: /* ? was under external abort */
|
|
panic("unknown data fault, 6b fsr %#lux", fsr);
|
|
break;
|
|
case 0x0:
|
|
panic("vector exception at %#lux", ureg->pc);
|
|
break;
|
|
case 0x1: /* alignment fault */
|
|
case 0x3: /* access flag fault (section) */
|
|
if(user){
|
|
char buf[ERRMAX];
|
|
|
|
snprint(buf, sizeof buf,
|
|
"sys: alignment: pc %#lux va %#p\n",
|
|
ureg->pc, va);
|
|
postnote(up, 1, buf, NDebug);
|
|
} else {
|
|
dumpstackwithureg(ureg);
|
|
panic("kernel alignment: pc %#lux va %#p", ureg->pc, va);
|
|
}
|
|
break;
|
|
case 0x2:
|
|
panic("terminal exception at %#lux", ureg->pc);
|
|
break;
|
|
case 0x4: /* icache maint fault */
|
|
case 0x6: /* access flag fault (page) */
|
|
case 0x8: /* precise external abort, non-xlat'n */
|
|
case 0x28:
|
|
case 0x16: /* imprecise ext. abort, non-xlt'n */
|
|
case 0x36:
|
|
panic("external non-translation abort %#lux pc %#lux addr %#p",
|
|
fsr, ureg->pc, va);
|
|
break;
|
|
case 0xc: /* l1 translation, precise ext. abort */
|
|
case 0x2c:
|
|
case 0xe: /* l2 translation, precise ext. abort */
|
|
case 0x2e:
|
|
panic("external translation abort %#lux pc %#lux addr %#p",
|
|
fsr, ureg->pc, va);
|
|
break;
|
|
case 0x1c: /* l1 translation, precise parity err */
|
|
case 0x1e: /* l2 translation, precise parity err */
|
|
case 0x18: /* imprecise parity or ecc err */
|
|
panic("translation parity error %#lux pc %#lux addr %#p",
|
|
fsr, ureg->pc, va);
|
|
break;
|
|
case 0x5: /* translation fault, no section entry */
|
|
case 0x7: /* translation fault, no page entry */
|
|
faultarm(ureg, va, user, !writetomem(inst));
|
|
break;
|
|
case 0x9:
|
|
case 0xb:
|
|
/* domain fault, accessing something we shouldn't */
|
|
if(user){
|
|
char buf[ERRMAX];
|
|
|
|
snprint(buf, sizeof buf,
|
|
"sys: access violation: pc %#lux va %#p\n",
|
|
ureg->pc, va);
|
|
postnote(up, 1, buf, NDebug);
|
|
} else
|
|
panic("kernel access violation: pc %#lux va %#p",
|
|
ureg->pc, va);
|
|
break;
|
|
case 0xd:
|
|
case 0xf:
|
|
/* permission error, copy on write or real permission error */
|
|
faultarm(ureg, va, user, !writetomem(inst));
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* here on all exceptions other than syscall (SWI) and reset
|
|
*/
|
|
void
|
|
trap(Ureg *ureg)
|
|
{
|
|
int clockintr, user, rem;
|
|
uintptr va, ifar, ifsr;
|
|
|
|
splhi(); /* paranoia */
|
|
if(up != nil)
|
|
rem = ((char*)ureg)-up->kstack;
|
|
else
|
|
rem = ((char*)ureg)-((char*)m+sizeof(Mach));
|
|
if(rem < 1024) {
|
|
iprint("trap: %d stack bytes left, up %#p ureg %#p m %#p cpu%d at pc %#lux\n",
|
|
rem, up, ureg, m, m->machno, ureg->pc);
|
|
dumpstackwithureg(ureg);
|
|
panic("trap: %d stack bytes left, up %#p ureg %#p at pc %#lux",
|
|
rem, up, ureg, ureg->pc);
|
|
}
|
|
|
|
m->perf.intrts = perfticks();
|
|
user = kenter(ureg);
|
|
/*
|
|
* All interrupts/exceptions should be resumed at ureg->pc-4,
|
|
* except for Data Abort which resumes at ureg->pc-8.
|
|
*/
|
|
if(ureg->type == (PsrMabt+1))
|
|
ureg->pc -= 8;
|
|
else
|
|
ureg->pc -= 4;
|
|
|
|
clockintr = 0; /* if set, may call sched() before return */
|
|
switch(ureg->type){
|
|
default:
|
|
panic("unknown trap; type %#lux, psr mode %#lux", ureg->type,
|
|
ureg->psr & PsrMask);
|
|
break;
|
|
case PsrMirq:
|
|
m->intr++;
|
|
clockintr = irq(ureg);
|
|
if(0 && up && !clockintr)
|
|
preempted(); /* this causes spurious suicides */
|
|
break;
|
|
case PsrMabt: /* prefetch (instruction) fault */
|
|
va = ureg->pc;
|
|
ifsr = cprdsc(0, CpFSR, 0, CpIFSR);
|
|
ifsr = (ifsr>>7) & 0x8 | ifsr & 0x7;
|
|
switch(ifsr){
|
|
case 0x02: /* instruction debug event (BKPT) */
|
|
if(user)
|
|
postnote(up, 1, "sys: breakpoint", NDebug);
|
|
else{
|
|
iprint("kernel bkpt: pc %#lux inst %#ux\n",
|
|
va, *(u32int*)va);
|
|
panic("kernel bkpt");
|
|
}
|
|
break;
|
|
default:
|
|
ifar = cprdsc(0, CpFAR, 0, CpIFAR);
|
|
if (va != ifar)
|
|
iprint("trap: cpu%d: i-fault va %#p != ifar %#p\n",
|
|
m->machno, va, ifar);
|
|
faultarm(ureg, va, user, 1);
|
|
break;
|
|
}
|
|
break;
|
|
case PsrMabt+1: /* data fault */
|
|
datafault(ureg, user);
|
|
break;
|
|
case PsrMund: /* undefined instruction */
|
|
if(!user) {
|
|
if (ureg->pc & 3) {
|
|
iprint("rounding fault pc %#lux down to word\n",
|
|
ureg->pc);
|
|
ureg->pc &= ~3;
|
|
}
|
|
if (Debug)
|
|
iprint("mathemu: cpu%d fpon %d instr %#8.8lux at %#p\n",
|
|
m->machno, m->fpon, *(ulong *)ureg->pc,
|
|
ureg->pc);
|
|
dumpstackwithureg(ureg);
|
|
panic("cpu%d: undefined instruction: pc %#lux inst %#ux",
|
|
m->machno, ureg->pc, ((u32int*)ureg->pc)[0]);
|
|
} else if(seg(up, ureg->pc, 0) != nil &&
|
|
*(u32int*)ureg->pc == 0xD1200070)
|
|
postnote(up, 1, "sys: breakpoint", NDebug);
|
|
else if(fpuemu(ureg) == 0){ /* didn't find any FP instrs? */
|
|
char buf[ERRMAX];
|
|
|
|
snprint(buf, sizeof buf,
|
|
"undefined instruction: pc %#lux instr %#8.8lux\n",
|
|
ureg->pc, *(ulong *)ureg->pc);
|
|
postnote(up, 1, buf, NDebug);
|
|
}
|
|
break;
|
|
}
|
|
splhi();
|
|
|
|
/* delaysched set because we held a lock or because our quantum ended */
|
|
if(up && up->delaysched && clockintr){
|
|
sched(); /* can cause more traps */
|
|
splhi();
|
|
}
|
|
|
|
if(user){
|
|
if(up->procctl || up->nnote)
|
|
notify(ureg);
|
|
kexit(ureg);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Fill in enough of Ureg to get a stack trace, and call a function.
|
|
* Used by debugging interface rdb.
|
|
*/
|
|
void
|
|
callwithureg(void (*fn)(Ureg*))
|
|
{
|
|
Ureg ureg;
|
|
|
|
memset(&ureg, 0, sizeof ureg);
|
|
ureg.pc = getcallerpc(&fn);
|
|
ureg.sp = (uintptr)&fn;
|
|
fn(&ureg);
|
|
}
|
|
|
|
static void
|
|
dumpstackwithureg(Ureg *ureg)
|
|
{
|
|
int x;
|
|
uintptr l, v, i, estack;
|
|
char *s;
|
|
|
|
dumpregs(ureg);
|
|
if((s = getconf("*nodumpstack")) != nil && strcmp(s, "0") != 0){
|
|
iprint("dumpstack disabled\n");
|
|
return;
|
|
}
|
|
delay(1000);
|
|
iprint("dumpstack\n");
|
|
|
|
x = 0;
|
|
x += iprint("ktrace /kernel/path %#.8lux %#.8lux %#.8lux # pc, sp, link\n",
|
|
ureg->pc, ureg->sp, ureg->r14);
|
|
delay(20);
|
|
i = 0;
|
|
if(up
|
|
&& (uintptr)&l >= (uintptr)up->kstack
|
|
&& (uintptr)&l <= (uintptr)up->kstack+KSTACK)
|
|
estack = (uintptr)up->kstack+KSTACK;
|
|
else if((uintptr)&l >= (uintptr)m->stack
|
|
&& (uintptr)&l <= (uintptr)m+MACHSIZE)
|
|
estack = (uintptr)m+MACHSIZE;
|
|
else
|
|
return;
|
|
x += iprint("estackx %p\n", estack);
|
|
|
|
for(l = (uintptr)&l; l < estack; l += sizeof(uintptr)){
|
|
v = *(uintptr*)l;
|
|
if((KTZERO < v && v < (uintptr)etext) || estack-l < 32){
|
|
x += iprint("%.8p ", v);
|
|
delay(20);
|
|
i++;
|
|
}
|
|
if(i == 8){
|
|
i = 0;
|
|
x += iprint("\n");
|
|
delay(20);
|
|
}
|
|
}
|
|
if(i)
|
|
iprint("\n");
|
|
delay(3000);
|
|
}
|
|
|
|
void
|
|
dumpstack(void)
|
|
{
|
|
callwithureg(dumpstackwithureg);
|
|
}
|
|
|
|
/*
|
|
* dump system control coprocessor registers
|
|
*/
|
|
static void
|
|
dumpscr(void)
|
|
{
|
|
iprint("0:\t%#8.8ux id\n", cpidget());
|
|
iprint("\t%8.8#ux ct\n", cpctget());
|
|
iprint("1:\t%#8.8ux control\n", controlget());
|
|
iprint("2:\t%#8.8ux ttb\n", ttbget());
|
|
iprint("3:\t%#8.8ux dac\n", dacget());
|
|
iprint("4:\t(reserved)\n");
|
|
iprint("5:\t%#8.8ux fsr\n", fsrget());
|
|
iprint("6:\t%#8.8ux far\n", farget());
|
|
iprint("7:\twrite-only cache\n");
|
|
iprint("8:\twrite-only tlb\n");
|
|
iprint("13:\t%#8.8ux pid\n", pidget());
|
|
delay(10);
|
|
}
|
|
|
|
/*
|
|
* dump general registers
|
|
*/
|
|
static void
|
|
dumpgpr(Ureg* ureg)
|
|
{
|
|
if(up != nil)
|
|
iprint("cpu%d: registers for %s %lud\n",
|
|
m->machno, up->text, up->pid);
|
|
else
|
|
iprint("cpu%d: registers for kernel\n", m->machno);
|
|
|
|
delay(20);
|
|
iprint("%#8.8lux\tr0\n", ureg->r0);
|
|
iprint("%#8.8lux\tr1\n", ureg->r1);
|
|
iprint("%#8.8lux\tr2\n", ureg->r2);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr3\n", ureg->r3);
|
|
iprint("%#8.8lux\tr4\n", ureg->r4);
|
|
iprint("%#8.8lux\tr5\n", ureg->r5);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr6\n", ureg->r6);
|
|
iprint("%#8.8lux\tr7\n", ureg->r7);
|
|
iprint("%#8.8lux\tr8\n", ureg->r8);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr9 (up)\n", ureg->r9);
|
|
iprint("%#8.8lux\tr10 (m)\n", ureg->r10);
|
|
iprint("%#8.8lux\tr11 (loader temporary)\n", ureg->r11);
|
|
iprint("%#8.8lux\tr12 (SB)\n", ureg->r12);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr13 (sp)\n", ureg->r13);
|
|
iprint("%#8.8lux\tr14 (link)\n", ureg->r14);
|
|
iprint("%#8.8lux\tr15 (pc)\n", ureg->pc);
|
|
delay(20);
|
|
iprint("%10.10lud\ttype\n", ureg->type);
|
|
iprint("%#8.8lux\tpsr\n", ureg->psr);
|
|
delay(500);
|
|
}
|
|
|
|
void
|
|
dumpregs(Ureg* ureg)
|
|
{
|
|
dumpgpr(ureg);
|
|
dumpscr();
|
|
}
|
|
|
|
vlong
|
|
probeaddr(uintptr addr)
|
|
{
|
|
vlong v;
|
|
|
|
ilock(&m->probelock);
|
|
m->trapped = 0;
|
|
m->probing = 1;
|
|
coherence();
|
|
|
|
v = *(ulong *)addr; /* this may cause a fault */
|
|
coherence();
|
|
|
|
m->probing = 0;
|
|
if (m->trapped)
|
|
v = -1;
|
|
iunlock(&m->probelock);
|
|
return v;
|
|
}
|