128ea44a89
a portable SG_NOEXEC segment attribute was added to allow non-executable (physical) segments. which will set the PTENOEXEC bits for putmmu(). in the future, this can be used to make non-executable stack / bss segments. the SG_DEVICE attribute was added to distinguish between mmio regions and uncached memory. only matterns on arm64. on arm, theres the issue that PTEUNCACHED would have no bits set when using the hardware bit definitions. this is the reason bcm, kw, teg2 and omap kernels use arteficial PTE constants. on zynq, the XN bit was used as a hack to give PTEUNCACHED a non-zero value and when the bit is clear then cache attributes where added to the pte. to fix this, PTECACHED constant was added. the portable mmu code in fault.c will now explicitely set PTECACHED bits for cached memory and PTEUNCACHED for uncached memory. that way the hardware bit definitions can be used everywhere.
145 lines
4.3 KiB
C
145 lines
4.3 KiB
C
/*
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* Memory and machine-specific definitions. Used in C and assembler.
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*/
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#define KiB 1024u /* Kibi 0x0000000000000400 */
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#define MiB 1048576u /* Mebi 0x0000000000100000 */
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#define GiB 1073741824u /* Gibi 000000000040000000 */
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#define MIN(a, b) ((a) < (b)? (a): (b))
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#define MAX(a, b) ((a) > (b)? (a): (b))
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/*
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* Not sure where these macros should go.
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* This probably isn't right but will do for now.
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* The macro names are problematic too.
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*/
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/*
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* In B(o), 'o' is the bit offset in the register.
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* For multi-bit fields use F(v, o, w) where 'v' is the value
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* of the bit-field of width 'w' with LSb at bit offset 'o'.
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*/
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#define B(o) (1<<(o))
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#define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
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#define FCLR(d, o, w) ((d) & ~(((1<<(w))-1)<<(o)))
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#define FEXT(d, o, w) (((d)>>(o)) & ((1<<(w))-1))
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#define FINS(d, o, w, v) (FCLR((d), (o), (w))|F((v), (o), (w)))
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#define FSET(d, o, w) ((d)|(((1<<(w))-1)<<(o)))
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#define FMASK(o, w) (((1<<(w))-1)<<(o))
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/*
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* Sizes
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*/
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#define BY2PG (4*KiB) /* bytes per page */
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#define PGSHIFT 12 /* log(BY2PG) */
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#define PGROUND(s) ROUND(s, BY2PG)
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#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
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/* max # of cpus system can run. tegra2 cpu ids are two bits wide. */
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#define MAXMACH 4
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#define MACHSIZE BY2PG
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#define L1SIZE (4 * BY2PG)
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#define KSTACK (16*KiB) /* was 8K */
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#define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
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/*
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* Magic registers
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*/
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#define USER 9 /* R9 is up-> */
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#define MACH 10 /* R10 is m-> */
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/*
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* Address spaces.
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* KTZERO is used by kprof and dumpstack (if any).
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*
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* KZERO (0xc0000000) is mapped to physical 0 (start of dram).
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* u-boot claims to occupy the first 4 MB of dram, but we're willing to
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* step on it once we're loaded.
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*
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* L2 PTEs are stored in 4K before cpu0's Mach (8K to 12K above KZERO).
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* cpu0's Mach struct is at L1 - MACHSIZE(4K) to L1 (12K to 16K above KZERO).
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* L1 PTEs are stored from L1 to L1+32K (16K to 48K above KZERO).
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* plan9.ini is loaded at CONFADDR (4MB).
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* KTZERO may be anywhere after that.
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*/
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#define KSEG0 0xC0000000 /* kernel segment */
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/* mask to check segment; good for 1GB dram */
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#define KSEGM 0xC0000000
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#define KZERO KSEG0 /* kernel address space */
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#define L1 (KZERO+16*KiB) /* cpu0 l1 page table; 16KiB aligned */
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#define CONFADDR (KZERO+0x400000) /* unparsed plan9.ini */
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#define CACHECONF (CONFADDR+48*KiB)
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/* KTZERO must match loadaddr in mkfile */
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#define KTZERO (KZERO+0x410000) /* kernel text start */
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#define L2pages (2*MiB) /* high memory reserved for l2 page tables */
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#define RESRVDHIMEM (64*KiB + MiB + L2pages) /* avoid HVECTOR, l2 pages */
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/* we assume that we have 1 GB of ram, which is true for all trimslices. */
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#define DRAMSIZE GiB
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#define UZERO 0 /* user segment */
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#define UTZERO (UZERO+BY2PG) /* user text start */
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/*
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* moved USTKTOP down to 1GB to keep MMIO space out of user space.
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* moved it down another MB to utterly avoid KADDR(stack_base) mapping
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* to high exception vectors. see confinit().
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*/
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#define USTKTOP (0x40000000 - 64*KiB - MiB) /* user segment end +1 */
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#define USTKSIZE (8*1024*1024) /* user stack size */
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/* address at which to copy and execute rebootcode */
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#define REBOOTADDR KADDR(0x100)
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/*
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* Legacy...
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*/
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#define BLOCKALIGN CACHELINESZ /* only used in allocb.c */
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/*
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* Sizes
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*/
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#define BI2BY 8 /* bits per byte */
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#define BY2SE 4
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#define BY2WD 4
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#define BY2V 8 /* only used in xalloc.c */
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#define CACHELINESZ 32 /* bytes per cache line */
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#define PTEMAPMEM (1024*1024)
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#define PTEPERTAB (PTEMAPMEM/BY2PG)
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#define SEGMAPSIZE 1984 /* magic 16*124 */
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#define SSEGMAPSIZE 16 /* magic */
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#define PPN(x) ((x)&~(BY2PG-1)) /* pure page number? */
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/*
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* These bits are completely artificial.
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* With a little work these move to port.
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*/
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#define PTEVALID (1<<0)
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#define PTERONLY 0
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#define PTEWRITE (1<<1)
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#define PTECACHED 0
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#define PTEUNCACHED (1<<2)
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/*
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* Physical machine information from here on.
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*/
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#define PHYSDRAM 0
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#define PHYSIO 0x50000000 /* cpu */
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#define VIRTIO PHYSIO
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#define PHYSL2BAG 0x50043000 /* l2 cache bag-on-the-side */
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#define PHYSEVP 0x6000f100 /* undocumented `exception vector' */
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#define PHYSCONS 0x70006000 /* uart console */
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#define PHYSIOEND 0xc0000000 /* end of ahb mem & pcie */
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#define PHYSAHB 0xc0000000 /* ahb bus */
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#define VIRTAHB 0xb0000000
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#define P2VAHB(pa) ((pa) - PHYSAHB + VIRTAHB)
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#define PHYSNOR 0xd0000000
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#define VIRTNOR 0x40000000
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