139 lines
2.5 KiB
C
139 lines
2.5 KiB
C
/*
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* tegra 2 SoC clocks; excludes cortex-a timers.
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*
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* SoC provides these shared clocks:
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* 4 29-bit count-down `timers' @ 1MHz,
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* 1 32-bit count-up time-stamp counter @ 1MHz,
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* and a real-time clock @ 32KHz.
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* the tegra watchdog (tegra 2 ref man §5.4.1) is tied to timers, not rtc.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "arm.h"
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typedef struct Shrdtmr Shrdtmr;
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typedef struct µscnt µscnt;
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/* tegra2 shared-intr timer registers */
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struct Shrdtmr { /* 29-bit count-down timer (4); unused */
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ulong trigger;
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ulong prescnt;
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};
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enum {
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/* trigger bits */
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Enable = 1u<<31,
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Periodintr = 1<<30,
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Countmask = MASK(29),
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/* prescnt bits */
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Intrclr = 1<<30,
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/* Countmask is ro */
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};
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struct µscnt { /* tegra2 shared 32-bit count-up µs counter (1) */
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ulong cntr;
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/*
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* oscillator clock fraction - 1; initially 0xb (11) from u-boot
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* for 12MHz periphclk.
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*/
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ulong cfg;
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uchar _pad0[0x3c - 0x8];
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ulong freeze;
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};
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enum {
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/* cfg bits */
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Dividendshift = 8,
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Dividendmask = MASK(8),
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Divisorshift = 0,
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Divisormask = MASK(8),
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};
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void
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tegclockintr(void)
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{
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int junk;
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Shrdtmr *tmr;
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/* appease the tegra dog */
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tmr = (Shrdtmr *)soc.tmr[0];
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junk = tmr->trigger;
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USED(junk);
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}
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/*
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* if on cpu0, shutdown the shared tegra2 watchdog timer.
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*/
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void
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tegclockshutdown(void)
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{
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Shrdtmr *tmr;
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if (m->machno == 0) {
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tmr = (Shrdtmr *)soc.tmr[0];
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tmr->prescnt = tmr->trigger = 0;
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coherence();
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}
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}
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void
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tegwdogintr(Ureg *, void *v)
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{
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int junk;
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Shrdtmr *tmr;
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tmr = (Shrdtmr *)v;
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tmr->prescnt |= Intrclr;
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coherence();
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/* the lousy documentation says we also have to read trigger */
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junk = tmr->trigger;
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USED(junk);
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}
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/* start tegra2 shared watch dog */
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void
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tegclock0init(void)
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{
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Shrdtmr *tmr;
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tmr = (Shrdtmr *)soc.tmr[0];
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irqenable(Tn0irq, tegwdogintr, tmr, "tegra watchdog");
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/*
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* tegra watchdog only fires on the second missed interrupt, thus /2.
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*/
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tmr->trigger = (Dogsectimeout * Mhz / 2 - 1) | Periodintr | Enable;
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coherence();
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}
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/*
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* µscnt is a freerunning timer (cycle counter); it needs no
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* initialisation, wraps and does not dispatch interrupts.
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*/
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void
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tegclockinit(void)
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{
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ulong old;
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µscnt *µs = (µscnt *)soc.µs;
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/* verify µs counter sanity */
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assert(µs->cfg == 0xb); /* set by u-boot */
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old = µs->cntr;
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delay(1);
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assert(old != µs->cntr);
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}
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ulong
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perfticks(void) /* MHz rate, assumed by timing loops */
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{
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ulong v;
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/* keep it non-zero to prevent m->fastclock ever going to zero. */
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v = ((µscnt *)soc.µs)->cntr;
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return v == 0? 1: v;
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}
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