310 lines
10 KiB
C
310 lines
10 KiB
C
/*
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* arm-specific definitions for cortex-a8 and -a9
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* these are used in C and assembler
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*
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* `cortex' refers to the cortex-a8 or -a9.
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*/
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#define NREGS 15 /* general-purpose regs, R0 through R14 */
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/*
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* Program Status Registers
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*/
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#define PsrMusr 0x00000010 /* mode */
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#define PsrMfiq 0x00000011
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#define PsrMirq 0x00000012
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#define PsrMsvc 0x00000013 /* `protected mode for OS' */
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#define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */
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#define PsrMabt 0x00000017
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#define PsrMund 0x0000001B
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#define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */
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#define PsrMask 0x0000001F
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#define PsrThumb 0x00000020 /* beware hammers */
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#define PsrDfiq 0x00000040 /* disable FIQ interrupts */
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#define PsrDirq 0x00000080 /* disable IRQ interrupts */
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#define PsrDasabt 0x00000100 /* disable asynch aborts */
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#define PsrBigend 0x00000200
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#define PsrJaz 0x01000000 /* java mode */
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#define PsrV 0x10000000 /* overflow */
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#define PsrC 0x20000000 /* carry/borrow/extend */
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#define PsrZ 0x40000000 /* zero */
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#define PsrN 0x80000000 /* negative/less than */
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#define PsrMbz (PsrJaz|PsrThumb|PsrBigend) /* these bits must be 0 */
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/*
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* MCR and MRC are anti-mnemonic.
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* MTCP coproc, opcode1, Rd, CRn, CRm[, opcode2] # arm -> coproc
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* MFCP coproc, opcode1, Rd, CRn, CRm[, opcode2] # coproc -> arm
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*/
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#define MTCP MCR
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#define MFCP MRC
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/* instruction decoding */
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#define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC)
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#define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op))
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#define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op))
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/*
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* Coprocessors
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*/
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#define CpOFPA 1 /* ancient 7500 FPA */
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#define CpFP 10 /* float FP, VFP cfg. */
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#define CpDFP 11 /* double FP */
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#define CpSC 15 /* System Control */
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/*
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* Primary (CRn) CpSC registers.
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*/
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#define CpID 0 /* ID and cache type */
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#define CpCONTROL 1 /* miscellaneous control */
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#define CpTTB 2 /* Translation Table Base(s) */
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#define CpDAC 3 /* Domain Access Control */
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#define CpFSR 5 /* Fault Status */
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#define CpFAR 6 /* Fault Address */
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#define CpCACHE 7 /* cache/write buffer control */
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#define CpTLB 8 /* TLB control */
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#define CpCLD 9 /* L2 Cache Lockdown, op1==1 */
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#define CpTLD 10 /* TLB Lockdown, with op2 */
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#define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */
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#define CpPID 13 /* Process ID */
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#define CpDTLB 15 /* TLB, L1 cache stuff (cortex) */
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/*
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* CpTTB op1==0, Crm==0 opcode2 values.
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*/
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#define CpTTB0 0 /* secure ttb */
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#define CpTTB1 1 /* non-secure ttb (v7) */
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#define CpTTBctl 2 /* v7 */
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/*
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* CpFSR op1==0, Crm==0 opcode 2 values.
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*/
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#define CpDFSR 0 /* data fault status */
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#define CpIFSR 1 /* instruction fault status */
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/*
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* CpFAR op1==0, Crm==0 opcode 2 values.
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*/
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#define CpDFAR 0 /* data fault address */
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#define CpIFAR 2 /* instruction fault address */
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/*
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* CpID Secondary (CRm) registers.
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*/
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#define CpIDidct 0
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/*
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* CpID CpIDidct op1==0 opcode2 fields.
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*/
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#define CpIDid 0 /* main ID */
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#define CpIDct 1 /* cache type */
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#define CpIDtlb 3 /* tlb type (cortex) */
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#define CpIDmpid 5 /* multiprocessor id (cortex) */
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/* CpIDid op1 values */
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#define CpIDcsize 1 /* cache size (cortex) */
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#define CpIDcssel 2 /* cache size select (cortex) */
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/*
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* CpID CpIDidct op1==CpIDcsize opcode2 fields.
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*/
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#define CpIDcasize 0 /* cache size */
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#define CpIDclvlid 1 /* cache-level id */
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/*
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* CpCONTROL op2 codes, op1==0, Crm==0.
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*/
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#define CpMainctl 0 /* sctlr */
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#define CpAuxctl 1
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#define CpCPaccess 2
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/*
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* CpCONTROL: op1==0, CRm==0, op2==CpMainctl.
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* main control register.
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* cortex/armv7 has more ops and CRm values.
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*/
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#define CpCmmu 0x00000001 /* M: MMU enable */
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#define CpCalign 0x00000002 /* A: alignment fault enable */
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#define CpCdcache 0x00000004 /* C: data cache on */
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#define CpBigend (1<<7)
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#define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */
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#define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */
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#define CpCicache 0x00001000 /* I: instruction cache on */
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#define CpChv 0x00002000 /* V: high vectors */
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#define CpCrr (1<<14) /* RR: round robin vs random cache replacement */
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#define CpCha (1<<17) /* HA: hw access flag enable */
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#define CpCdz (1<<19) /* DZ: divide by zero fault enable (not cortex-a9) */
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#define CpCfi (1<<21) /* FI: fast intrs */
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#define CpCve (1<<24) /* VE: intr vectors enable */
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#define CpCee (1<<25) /* EE: exception endianness: big */
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#define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. (RO) */
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#define CpCtre (1<<28) /* TRE: TEX remap enable */
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#define CpCafe (1<<29) /* AFE: access flag (ttb) enable */
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#define CpCte (1<<30) /* TE: thumb exceptions */
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#define CpCsbz (1<<31 | CpCte | CpCafe | CpCtre | 1<<26 | CpCee | CpCve | \
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CpCfi | 3<<19 | CpCha | 1<<15 | 3<<8 | CpBigend) /* must be 0 (armv7) */
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#define CpCsbo (3<<22 | 1<<18 | 1<<16 | CpChv | CpCsw | 017<<3) /* must be 1 (armv7) */
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/*
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* CpCONTROL: op1==0, CRm==0, op2==CpAuxctl.
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* Auxiliary control register on cortex-a9.
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* these differ from even the cortex-a8 bits.
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*/
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#define CpACparity (1<<9)
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#define CpACca1way (1<<8) /* cache in a single way */
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#define CpACcaexcl (1<<7) /* exclusive cache */
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#define CpACsmp (1<<6) /* SMP l1 caches coherence; needed for ldrex/strex */
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#define CpAClwr0line (1<<3) /* write full cache line of 0s; see Fullline0 */
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#define CpACl1pref (1<<2) /* l1 prefetch enable */
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#define CpACl2pref (1<<1) /* l2 prefetch enable */
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#define CpACmaintbcast (1<<0) /* broadcast cache & tlb maint. ops */
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/*
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* CpCONTROL Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpCONTROLscr 1
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#define CpSCRscr 0 /* secure configuration */
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/*
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* CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0.
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* In ARM-speak, 'flush' means invalidate and 'clean' means writeback.
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*/
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#define CpCACHEintr 0 /* interrupt (op2==4) */
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#define CpCACHEisi 1 /* inner-sharable I cache (v7) */
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#define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */
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#define CpCACHEinvi 5 /* instruction, branch table */
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#define CpCACHEinvd 6 /* data or unified */
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// #define CpCACHEinvu 7 /* unified (not on cortex) */
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#define CpCACHEva2pa 8 /* va -> pa translation (cortex) */
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#define CpCACHEwb 10 /* writeback */
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#define CpCACHEinvdse 11 /* data or unified by mva */
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#define CpCACHEwbi 14 /* writeback+invalidate */
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#define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */
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#define CpCACHEse 1 /* single entry */
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#define CpCACHEsi 2 /* set/index (set/way) */
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#define CpCACHEtest 3 /* test loop */
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#define CpCACHEwait 4 /* wait (prefetch flush on cortex) */
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#define CpCACHEdmbarr 5 /* wb only (cortex) */
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#define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */
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#define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */
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/*
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* CpTLB Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpTLBinvi 5 /* instruction */
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#define CpTLBinvd 6 /* data */
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#define CpTLBinvu 7 /* unified */
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#define CpTLBinv 0 /* invalidate all */
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#define CpTLBinvse 1 /* invalidate single entry */
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#define CpTBLasid 2 /* by ASID (cortex) */
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/*
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* CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex)
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*/
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#define CpCLDena 12 /* enables */
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#define CpCLDcyc 13 /* cycle counter */
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#define CpCLDuser 14 /* user enable */
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#define CpCLDenapmnc 0
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#define CpCLDenacyc 1
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/*
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* CpCLD Secondary (CRm) registers and opcode2 fields for op1==1.
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*/
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#define CpCLDl2 0 /* l2 cache */
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#define CpCLDl2aux 2 /* auxiliary control */
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/*
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* l2 cache aux. control
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*/
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#define CpCl2ecc (1<<28) /* use ecc, not parity */
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#define CpCl2noldforw (1<<27) /* no ld forwarding */
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#define CpCl2nowrcomb (1<<25) /* no write combining */
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#define CpCl2nowralldel (1<<24) /* no write allocate delay */
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#define CpCl2nowrallcomb (1<<23) /* no write allocate combine */
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#define CpCl2nowralloc (1<<22) /* no write allocate */
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#define CpCl2eccparity (1<<21) /* enable ecc or parity */
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#define CpCl2inner (1<<16) /* inner cacheability */
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/* other bits are tag ram & data ram latencies */
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/*
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* CpTLD Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpTLDlock 0 /* TLB lockdown registers */
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#define CpTLDpreload 1 /* TLB preload */
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#define CpTLDi 0 /* TLB instr. lockdown reg. */
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#define CpTLDd 1 /* " data " " */
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/*
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* CpVECS Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpVECSbase 0
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#define CpVECSnorm 0 /* (non-)secure base addr */
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#define CpVECSmon 1 /* secure monitor base addr */
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/*
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* MMU page table entries.
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* memory must be cached, buffered, sharable and wralloc to participate in
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* automatic L1 cache coherency.
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*/
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#define Mbz (0<<4) /* L1 page tables: must be 0 */
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#define Noexecsect (1<<4) /* L1 sections: no execute */
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#define Fault 0x00000000 /* L[12] pte: unmapped */
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#define Coarse (Mbz|1) /* L1: page table */
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#define Section (Mbz|2) /* L1 1MB */
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/*
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* next 2 bits (L1wralloc & L1sharable) and Buffered and Cached must be
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* set in l1 ptes for LDREX/STREX to work.
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*/
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#define L1wralloc (1<<12) /* L1 TEX */
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#define L1sharable (1<<16)
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#define L1nonglobal (1<<17) /* tied to asid */
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#define Nonsecuresect (1<<19) /* L1 sections */
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#define Large 0x00000001 /* L2 64KB */
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#define Noexecsmall 1 /* L2: no execute */
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#define Small 0x00000002 /* L2 4KB */
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/*
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* next 3 bits (Buffered, Cached, L2wralloc) & L2sharable must be set in
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* l2 ptes for memory containing locks because LDREX/STREX require them.
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*/
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#define Buffered 0x00000004 /* L[12]: 0 write-thru, 1 -back */
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#define Cached 0x00000008 /* L[12] */
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#define L2wralloc (1<<6) /* L2 TEX (small pages) */
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#define L2apro (1<<9) /* L2 AP: read only */
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#define L2sharable (1<<10)
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#define L2nonglobal (1<<11) /* tied to asid */
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#define Dom0 0
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/* attributes for memory containing locks */
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#define L1ptedramattrs (Cached | Buffered | L1wralloc | L1sharable)
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#define L2ptedramattrs (Cached | Buffered | L2wralloc | L2sharable)
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#define Noaccess 0 /* AP, DAC */
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#define Krw 1 /* AP */
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/* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */
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#define Uro 2 /* AP */
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#define Urw 3 /* AP */
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#define Client 1 /* DAC */
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#define Manager 3 /* DAC */
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#define AP(n, v) F((v), ((n)*2)+4, 2)
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#define L1AP(ap) (AP(3, (ap)))
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#define L2AP(ap) (AP(0, (ap))) /* armv7 */
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#define DAC(n, v) F((v), (n)*2, 2)
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#define HVECTORS 0xffff0000
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