e4ce6aadac
we might as well handle the per process cycle counter in the portable part instead of duplicating the code in every arch and have inconsistent implementations. we now have a portable kenter() and kexit() function, that is ment to be used in trap/syscall from user, which updates the counters. some kernels missed initializing Mach.cyclefreq.
868 lines
16 KiB
C
868 lines
16 KiB
C
/*
|
||
* nvidia tegra 2 architecture-specific stuff
|
||
*/
|
||
|
||
#include "u.h"
|
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#include "../port/lib.h"
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#include "mem.h"
|
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#include "dat.h"
|
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#include "fns.h"
|
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#include "../port/error.h"
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#include "io.h"
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#include "arm.h"
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|
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#include "../port/netif.h"
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#include "../port/etherif.h"
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#include "../port/flashif.h"
|
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|
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enum {
|
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/* hardware limits imposed by register contents or layouts */
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Maxcpus = 4,
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Maxflowcpus = 2,
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Debug = 0,
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};
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typedef struct Clkrst Clkrst;
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typedef struct Diag Diag;
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typedef struct Flow Flow;
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typedef struct Scu Scu;
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typedef struct Power Power;
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|
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struct Clkrst {
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ulong rstsrc;
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ulong rstdevl;
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ulong rstdevh;
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ulong rstdevu;
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||
|
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ulong clkoutl;
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ulong clkouth;
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ulong clkoutu;
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uchar _pad0[0x24-0x1c];
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ulong supcclkdiv; /* super cclk divider */
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ulong _pad1;
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ulong supsclkdiv; /* super sclk divider */
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uchar _pad4[0x4c-0x30];
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ulong clkcpu;
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uchar _pad1[0xe0-0x50];
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ulong pllxbase; /* pllx controls CPU clock speed */
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ulong pllxmisc;
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ulong pllebase; /* plle is dedicated to pcie */
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ulong pllemisc;
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uchar _pad2[0x340-0xf0];
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ulong cpuset;
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ulong cpuclr;
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};
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enum {
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/* rstsrc bits */
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Wdcpurst = 1<<0,
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Wdcoprst = 1<<1,
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Wdsysrst = 1<<2,
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Wdsel = 1<<4, /* tmr1 or tmr2? */
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Wdena = 1<<5,
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/* devl bits */
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Sysreset = 1<<2,
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/* clkcpu bits */
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Cpu1stop = 1<<9,
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Cpu0stop = 1<<8,
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/* cpu* bits */
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Cpu1dbgreset = 1<<13,
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Cpu0dbgreset = 1<<12,
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Cpu1wdreset = 1<<9,
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Cpu0wdreset = 1<<8,
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Cpu1dereset = 1<<5,
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Cpu0dereset = 1<<4,
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Cpu1reset = 1<<1,
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Cpu0reset = 1<<0,
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};
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struct Power {
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ulong ctl; /* mainly for rtc clock signals */
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ulong secregdis;
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ulong swrst;
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ulong wakevmask;
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ulong waklvl;
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ulong waksts;
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ulong swwaksts;
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ulong dpdpadsovr; /* deep power down pads override */
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ulong dpdsample;
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ulong dpden;
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ulong gatetimroff;
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ulong gatetimron;
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ulong toggle;
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ulong unclamp;
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ulong gatests; /* ro */
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ulong goodtmr;
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ulong blinktmr;
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ulong noiopwr;
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ulong detect;
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ulong detlatch;
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|
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ulong scratch[24];
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ulong secscratch[6];
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|
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ulong cpupwrgoodtmr;
|
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ulong cpupwrofftmr;
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|
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ulong pgmask[2];
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||
|
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ulong autowaklvl;
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ulong autowaklvlmask;
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ulong wakdelay;
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|
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ulong detval;
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ulong ddr;
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ulong usbdebdel; /* usb de-bounce delay */
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ulong usbao;
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ulong cryptoop;
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ulong pllpwb0ovr;
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ulong scratch24[42-24+1];
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ulong boundoutmirr[3];
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ulong sys33ven;
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ulong boundoutmirracc;
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ulong gate;
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};
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enum {
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/* toggle bits */
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Start = 1<<8,
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/* partition ids */
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Partpcie= 3,
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Partl2 = 4,
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};
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struct Scu {
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ulong ctl;
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ulong cfg; /* ro */
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ulong cpupwrsts;
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ulong inval;
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uchar _pad0[0x40-0x10];
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ulong filtstart;
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ulong filtend;
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uchar _pad1[0x50-0x48];
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ulong accctl; /* initially 0 */
|
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ulong nsaccctl;
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};
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enum {
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/* ctl bits */
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Scuenable = 1<<0,
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Filter = 1<<1,
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Scuparity = 1<<2,
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Specfill = 1<<3, /* only for PL310 */
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Allport0 = 1<<4,
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Standby = 1<<5,
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Icstandby = 1<<6,
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};
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struct Flow {
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ulong haltcpu0;
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ulong haltcop;
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ulong cpu0;
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ulong cop;
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ulong xrq;
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ulong haltcpu1;
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ulong cpu1;
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};
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enum {
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/* haltcpu* bits */
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Stop = 2<<29,
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/* cpu* bits */
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Event = 1<<14, /* w1c */
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Waitwfebitsshift = 4,
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Waitwfebitsmask = MASK(2),
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Eventenable = 1<<1,
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Cpuenable = 1<<0,
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};
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struct Diag {
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Cacheline c0;
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Lock;
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Ref cnt;
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Ref sync;
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Cacheline c1;
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};
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extern ulong testmem;
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/*
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* number of cpus available. contrast with conf.nmach, which is number
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* of running cpus.
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*/
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int navailcpus;
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Isolated l1ptstable;
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Soc soc = {
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.clkrst = 0x60006000, /* clock & reset signals */
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.power = 0x7000e400,
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.exceptvec = PHYSEVP, /* undocumented magic */
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.sema = 0x60001000,
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.l2cache= PHYSL2BAG, /* pl310 bag on the side */
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.flow = 0x60007000,
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/* 4 non-gic controllers */
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// .intr = { 0x60004000, 0x60004100, 0x60004200, 0x60004300, },
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/* private memory region */
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.scu = 0x50040000,
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/* we got this address from the `cortex-a series programmer's guide'. */
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.intr = 0x50040100, /* per-cpu interface */
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.glbtmr = 0x50040200,
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.loctmr = 0x50040600,
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.intrdist=0x50041000,
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.uart = { 0x70006000, 0x70006040,
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0x70006200, 0x70006300, 0x70006400, },
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.rtc = 0x7000e000,
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.tmr = { 0x60005000, 0x60005008, 0x60005050, 0x60005058, },
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.µs = 0x60005010,
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.pci = 0x80000000,
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.ether = 0xa0024000,
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.nand = 0x70008000,
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.nor = 0x70009000, /* also VIRTNOR */
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.ehci = P2VAHB(0xc5000000), /* 1st of 3 */
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.ide = P2VAHB(0xc3000000),
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.gpio = { 0x6000d000, 0x6000d080, 0x6000d100, 0x6000d180,
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0x6000d200, 0x6000d280, 0x6000d300, },
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.spi = { 0x7000d400, 0x7000d600, 0x7000d800, 0x7000da00, },
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.twsi = 0x7000c000,
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.mmc = { P2VAHB(0xc8000000), P2VAHB(0xc8000200),
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P2VAHB(0xc8000400), P2VAHB(0xc8000600), },
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};
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static volatile Diag diag;
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static int missed;
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void
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dumpcpuclks(void) /* run CPU at full speed */
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{
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Clkrst *clk = (Clkrst *)soc.clkrst;
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iprint("pllx base %#lux misc %#lux\n", clk->pllxbase, clk->pllxmisc);
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iprint("plle base %#lux misc %#lux\n", clk->pllebase, clk->pllemisc);
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iprint("super cclk divider %#lux\n", clk->supcclkdiv);
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iprint("super sclk divider %#lux\n", clk->supsclkdiv);
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}
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static char *
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devidstr(ulong)
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{
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return "ARM Cortex-A9";
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}
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void
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archtegralink(void)
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{
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}
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/* convert AddrDevid register to a string in buf and return buf */
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char *
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cputype2name(char *buf, int size)
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{
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ulong r;
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r = cpidget(); /* main id register */
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assert((r >> 24) == 'A');
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seprint(buf, buf + size, "Cortex-A9 r%ldp%ld",
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(r >> 20) & MASK(4), r & MASK(4));
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return buf;
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}
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static void
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errata(void)
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{
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ulong reg, r, p;
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/* apply cortex-a9 errata workarounds */
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r = cpidget(); /* main id register */
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assert((r >> 24) == 'A');
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p = r & MASK(4); /* minor revision */
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r >>= 20;
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r &= MASK(4); /* major revision */
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/* this is an undocumented `diagnostic register' that linux knows */
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reg = cprdsc(0, CpDTLB, 0, 1);
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if (r < 2 || r == 2 && p <= 2)
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reg |= 1<<4; /* 742230 */
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if (r == 2 && p <= 2)
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reg |= 1<<6 | 1<<12 | 1<<22; /* 743622, 2×742231 */
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if (r < 3)
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reg |= 1<<11; /* 751472 */
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cpwrsc(0, CpDTLB, 0, 1, reg);
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}
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void
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archconfinit(void)
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{
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char *p;
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ulong hz;
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assert(m != nil);
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m->cpuhz = 1000 * Mhz; /* trimslice speed */
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p = getconf("*cpumhz");
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if (p) {
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hz = atoi(p) * Mhz;
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if (hz >= 100*Mhz && hz <= 3600UL*Mhz)
|
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m->cpuhz = hz;
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}
|
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m->cyclefreq = m->cpuhz;
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m->delayloop = m->cpuhz/2000; /* initial estimate */
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errata();
|
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}
|
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|
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int
|
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archether(unsigned ctlrno, Ether *ether)
|
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{
|
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switch(ctlrno) {
|
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case 0:
|
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ether->type = "rtl8169"; /* pci-e ether */
|
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ether->ctlrno = ctlrno;
|
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ether->irq = Pcieirq; /* non-msi pci-e intr */
|
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ether->nopt = 0;
|
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ether->mbps = 1000;
|
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return 1;
|
||
}
|
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return -1;
|
||
}
|
||
|
||
void
|
||
dumpscustate(void)
|
||
{
|
||
Scu *scu = (Scu *)soc.scu;
|
||
|
||
print("cpu%d scu: accctl %#lux\n", m->machno, scu->accctl);
|
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print("cpu%d scu: smp cpu bit map %#lo for %ld cpus; ", m->machno,
|
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(scu->cfg >> 4) & MASK(4), (scu->cfg & MASK(2)) + 1);
|
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print("cpus' power %#lux\n", scu->cpupwrsts);
|
||
}
|
||
|
||
void
|
||
scuon(void)
|
||
{
|
||
Scu *scu = (Scu *)soc.scu;
|
||
|
||
if (scu->ctl & Scuenable)
|
||
return;
|
||
scu->inval = MASK(16);
|
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coherence();
|
||
scu->ctl = Scuparity | Scuenable | Specfill;
|
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coherence();
|
||
}
|
||
|
||
int
|
||
getncpus(void)
|
||
{
|
||
int n;
|
||
char *p;
|
||
Scu *scu;
|
||
|
||
if (navailcpus == 0) {
|
||
scu = (Scu *)soc.scu;
|
||
navailcpus = (scu->cfg & MASK(2)) + 1;
|
||
if (navailcpus > MAXMACH)
|
||
navailcpus = MAXMACH;
|
||
|
||
p = getconf("*ncpu");
|
||
if (p && *p) {
|
||
n = atoi(p);
|
||
if (n > 0 && n < navailcpus)
|
||
navailcpus = n;
|
||
}
|
||
}
|
||
return navailcpus;
|
||
}
|
||
|
||
void
|
||
cpuidprint(void)
|
||
{
|
||
char name[64];
|
||
|
||
cputype2name(name, sizeof name);
|
||
delay(50); /* let uart catch up */
|
||
iprint("cpu%d: %lldMHz ARM %s %s-endian\n",
|
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m->machno, m->cpuhz / Mhz, name,
|
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getpsr() & PsrBigend? "big": "little");
|
||
}
|
||
|
||
static void
|
||
clockson(void)
|
||
{
|
||
Clkrst *clk = (Clkrst *)soc.clkrst;
|
||
|
||
/* enable all by clearing resets */
|
||
clk->rstdevl = clk->rstdevh = clk->rstdevu = 0;
|
||
coherence();
|
||
clk->clkoutl = clk->clkouth = clk->clkoutu = ~0; /* enable all clocks */
|
||
coherence();
|
||
|
||
clk->rstsrc = Wdcpurst | Wdcoprst | Wdsysrst | Wdena;
|
||
coherence();
|
||
}
|
||
|
||
/* we could be shutting down ourself (if cpu == m->machno), so take care. */
|
||
void
|
||
stopcpu(uint cpu)
|
||
{
|
||
Flow *flow = (Flow *)soc.flow;
|
||
Clkrst *clk = (Clkrst *)soc.clkrst;
|
||
|
||
if (cpu == 0) {
|
||
iprint("stopcpu: may not stop cpu0\n");
|
||
return;
|
||
}
|
||
|
||
machoff(cpu);
|
||
lock(&active);
|
||
active.stopped |= 1 << cpu;
|
||
unlock(&active);
|
||
l1cache->wb();
|
||
|
||
/* shut down arm7 avp coproc so it can't cause mischief. */
|
||
/* could try watchdog without stopping avp. */
|
||
flow->haltcop = Stop;
|
||
coherence();
|
||
flow->cop = 0; /* no Cpuenable */
|
||
coherence();
|
||
delay(10);
|
||
|
||
assert(cpu < Maxflowcpus);
|
||
*(cpu == 0? &flow->haltcpu0: &flow->haltcpu1) = Stop;
|
||
coherence();
|
||
*(cpu == 0? &flow->cpu0: &flow->cpu1) = 0; /* no Cpuenable */
|
||
coherence();
|
||
delay(10);
|
||
|
||
/* cold reset */
|
||
assert(cpu < Maxcpus);
|
||
clk->cpuset = (Cpu0reset | Cpu0dbgreset | Cpu0dereset) << cpu;
|
||
coherence();
|
||
delay(1);
|
||
|
||
l1cache->wb();
|
||
}
|
||
|
||
static void
|
||
synccpus(Ref *cntp, int n)
|
||
{
|
||
incref(cntp);
|
||
while (cntp->ref < n)
|
||
;
|
||
/* all cpus should now be here */
|
||
}
|
||
|
||
static void
|
||
pass1(int pass, volatile Diag *dp)
|
||
{
|
||
int i;
|
||
|
||
if(m->machno == 0)
|
||
iprint(" %d", pass);
|
||
for (i = 1000*1000; --i > 0; ) {
|
||
incref(&dp->cnt);
|
||
incref(&dp->cnt);
|
||
}
|
||
|
||
synccpus(&dp->sync, navailcpus);
|
||
/* all cpus are now here */
|
||
|
||
ilock(dp);
|
||
if(dp->cnt.ref != 0)
|
||
panic("cpu%d: diag: failed w count %ld", m->machno, dp->cnt.ref);
|
||
iunlock(dp);
|
||
|
||
synccpus(&dp->sync, 2 * navailcpus);
|
||
/* all cpus are now here */
|
||
decref(&dp->sync);
|
||
decref(&dp->sync);
|
||
}
|
||
|
||
/*
|
||
* try to confirm coherence of l1 caches.
|
||
* assume that all available cpus will be started.
|
||
*/
|
||
void
|
||
l1diag(void)
|
||
{
|
||
int pass;
|
||
volatile Diag *dp;
|
||
|
||
if (!Debug)
|
||
return;
|
||
|
||
l1cache->wb();
|
||
|
||
/*
|
||
* synchronise and print
|
||
*/
|
||
dp = &diag;
|
||
ilock(dp);
|
||
if (m->machno == 0)
|
||
iprint("l1: waiting for %d cpus... ", navailcpus);
|
||
iunlock(dp);
|
||
|
||
synccpus(&dp->sync, navailcpus);
|
||
|
||
ilock(dp);
|
||
if (m->machno == 0)
|
||
iprint("cache coherency pass");
|
||
iunlock(dp);
|
||
|
||
synccpus(&dp->sync, 2 * navailcpus);
|
||
decref(&dp->sync);
|
||
decref(&dp->sync);
|
||
|
||
/*
|
||
* cpus contend
|
||
*/
|
||
for (pass = 0; pass < 3; pass++)
|
||
pass1(pass, dp);
|
||
|
||
/*
|
||
* synchronise and check sanity
|
||
*/
|
||
synccpus(&dp->sync, navailcpus);
|
||
|
||
if(dp->sync.ref < navailcpus || dp->sync.ref >= 2 * navailcpus)
|
||
panic("cpu%d: diag: failed w dp->sync %ld", m->machno,
|
||
dp->sync.ref);
|
||
if(dp->cnt.ref != 0)
|
||
panic("cpu%d: diag: failed w dp->cnt %ld", m->machno,
|
||
dp->cnt.ref);
|
||
|
||
ilock(dp);
|
||
iprint(" cpu%d ok", m->machno);
|
||
iunlock(dp);
|
||
|
||
synccpus(&dp->sync, 2 * navailcpus);
|
||
decref(&dp->sync);
|
||
decref(&dp->sync);
|
||
l1cache->wb();
|
||
|
||
/*
|
||
* all done, print
|
||
*/
|
||
ilock(dp);
|
||
if (m->machno == 0)
|
||
iprint("\n");
|
||
iunlock(dp);
|
||
}
|
||
|
||
static void
|
||
unfreeze(uint cpu)
|
||
{
|
||
Clkrst *clk = (Clkrst *)soc.clkrst;
|
||
Flow *flow = (Flow *)soc.flow;
|
||
|
||
assert(cpu < Maxcpus);
|
||
|
||
clk->clkcpu &= ~(Cpu0stop << cpu);
|
||
coherence();
|
||
/* out of reset */
|
||
clk->cpuclr = (Cpu0reset | Cpu0wdreset | Cpu0dbgreset | Cpu0dereset) <<
|
||
cpu;
|
||
coherence();
|
||
|
||
assert(cpu < Maxflowcpus);
|
||
*(cpu == 0? &flow->cpu0: &flow->cpu1) = 0;
|
||
coherence();
|
||
*(cpu == 0? &flow->haltcpu0: &flow->haltcpu1) = 0; /* normal operat'n */
|
||
coherence();
|
||
}
|
||
|
||
/*
|
||
* this is all a bit magic. the soc.exceptvec register is effectively
|
||
* undocumented. we had to look at linux and experiment, alas. this is the
|
||
* sort of thing that should be standardised as part of the cortex mpcore spec.
|
||
* even intel document their equivalent procedure.
|
||
*/
|
||
int
|
||
startcpu(uint cpu)
|
||
{
|
||
int i, r;
|
||
ulong oldvec, rstaddr;
|
||
ulong *evp = (ulong *)soc.exceptvec; /* magic */
|
||
|
||
r = 0;
|
||
if (getncpus() < 2 || cpu == m->machno ||
|
||
cpu >= MAXMACH || cpu >= navailcpus)
|
||
return -1;
|
||
|
||
oldvec = *evp;
|
||
l1cache->wb(); /* start next cpu w same view of ram */
|
||
*evp = rstaddr = PADDR(_vrst); /* will start cpu executing at _vrst */
|
||
coherence();
|
||
l1cache->wb();
|
||
unfreeze(cpu);
|
||
|
||
for (i = 2000; i > 0 && *evp == rstaddr; i--)
|
||
delay(1);
|
||
if (i <= 0 || *evp != cpu) {
|
||
iprint("cpu%d: didn't start!\n", cpu);
|
||
stopcpu(cpu); /* make sure it's stopped */
|
||
r = -1;
|
||
}
|
||
*evp = oldvec;
|
||
return r;
|
||
}
|
||
|
||
static void
|
||
cksecure(void)
|
||
{
|
||
ulong db;
|
||
extern ulong getdebug(void);
|
||
|
||
if (getscr() & 1)
|
||
panic("cpu%d: running non-secure", m->machno);
|
||
db = getdebug();
|
||
if (db)
|
||
iprint("cpu%d: debug enable reg %#lux\n", m->machno, db);
|
||
}
|
||
|
||
ulong
|
||
smpon(void)
|
||
{
|
||
ulong aux;
|
||
|
||
/* cortex-a9 model-specific configuration */
|
||
aux = getauxctl();
|
||
putauxctl(aux | CpACsmp | CpACmaintbcast);
|
||
return aux;
|
||
}
|
||
|
||
void
|
||
cortexa9cachecfg(void)
|
||
{
|
||
/* cortex-a9 model-specific configuration */
|
||
putauxctl(getauxctl() | CpACparity | CpAClwr0line | CpACl2pref);
|
||
}
|
||
|
||
/*
|
||
* called on a cpu other than 0 from cpureset in l.s,
|
||
* from _vrst in lexception.s.
|
||
* mmu and l1 (and system-wide l2) caches and coherency (smpon) are on,
|
||
* but interrupts are disabled.
|
||
* our mmu is using an exact copy of cpu0's l1 page table
|
||
* as it was after userinit ran.
|
||
*/
|
||
void
|
||
cpustart(void)
|
||
{
|
||
int ms;
|
||
ulong *evp;
|
||
Power *pwr;
|
||
|
||
up = nil;
|
||
if (active.machs[m->machno]) {
|
||
serialputc('?');
|
||
serialputc('r');
|
||
panic("cpu%d: resetting after start", m->machno);
|
||
}
|
||
assert(m->machno != 0);
|
||
|
||
errata();
|
||
cortexa9cachecfg();
|
||
memdiag(&testmem);
|
||
|
||
machinit(); /* bumps nmach, adds bit to machs */
|
||
machoff(m->machno); /* not ready to go yet */
|
||
|
||
/* clock signals and scu are system-wide and already on */
|
||
clockshutdown(); /* kill any watch-dog timer */
|
||
|
||
trapinit();
|
||
clockinit(); /* sets loop delay */
|
||
timersinit();
|
||
cpuidprint();
|
||
|
||
/*
|
||
* notify cpu0 that we're up so it can proceed to l1diag.
|
||
*/
|
||
evp = (ulong *)soc.exceptvec; /* magic */
|
||
*evp = m->machno;
|
||
coherence();
|
||
|
||
l1diag(); /* contend with other cpus to verify sanity */
|
||
|
||
/*
|
||
* pwr->noiopwr == 0
|
||
* pwr->detect == 0x1ff (default, all disabled)
|
||
*/
|
||
pwr = (Power *)soc.power;
|
||
assert(pwr->gatests == MASK(7)); /* everything has power */
|
||
|
||
/*
|
||
* 8169 has to initialise before we get past this, thus cpu0
|
||
* has to schedule processes first.
|
||
*/
|
||
if (Debug)
|
||
iprint("cpu%d: waiting for 8169\n", m->machno);
|
||
for (ms = 0; !l1ptstable.word && ms < 5000; ms += 10) {
|
||
delay(10);
|
||
cachedinvse(&l1ptstable.word, sizeof l1ptstable.word);
|
||
}
|
||
if (!l1ptstable.word)
|
||
iprint("cpu%d: 8169 unreasonably slow; proceeding\n", m->machno);
|
||
/* now safe to copy cpu0's l1 pt in mmuinit */
|
||
|
||
mmuinit(); /* update our l1 pt from cpu0's */
|
||
fpon();
|
||
machon(m->machno); /* now ready to go and be scheduled */
|
||
|
||
if (Debug)
|
||
iprint("cpu%d: scheding\n", m->machno);
|
||
schedinit();
|
||
panic("cpu%d: schedinit returned", m->machno);
|
||
}
|
||
|
||
/* mainly used to break out of wfi */
|
||
void
|
||
sgintr(Ureg *ureg, void *)
|
||
{
|
||
iprint("cpu%d: got sgi\n", m->machno);
|
||
/* try to prod cpu1 into life when it gets stuck */
|
||
if (m->machno != 0)
|
||
clockprod(ureg);
|
||
}
|
||
|
||
void
|
||
archreset(void)
|
||
{
|
||
static int beenhere;
|
||
|
||
if (beenhere)
|
||
return;
|
||
beenhere = 1;
|
||
|
||
/* conservative temporary values until archconfinit runs */
|
||
m->cpuhz = 1000 * Mhz; /* trimslice speed */
|
||
m->delayloop = m->cpuhz/2000; /* initial estimate */
|
||
|
||
prcachecfg();
|
||
|
||
clockson();
|
||
/* all partitions were powered up by u-boot, so needn't do anything */
|
||
archconfinit();
|
||
// resetusb();
|
||
fpon();
|
||
|
||
if (irqtooearly)
|
||
panic("archreset: too early for irqenable");
|
||
irqenable(Cpu0irq, sgintr, nil, "cpu0");
|
||
irqenable(Cpu1irq, sgintr, nil, "cpu1");
|
||
/* ... */
|
||
}
|
||
|
||
void
|
||
archreboot(void)
|
||
{
|
||
Clkrst *clk = (Clkrst *)soc.clkrst;
|
||
|
||
assert(m->machno == 0);
|
||
iprint("archreboot: reset!\n");
|
||
delay(20);
|
||
|
||
clk->rstdevl |= Sysreset;
|
||
coherence();
|
||
delay(500);
|
||
|
||
/* shouldn't get here */
|
||
splhi();
|
||
iprint("awaiting reset");
|
||
for(;;) {
|
||
delay(1000);
|
||
print(".");
|
||
}
|
||
}
|
||
|
||
void
|
||
kbdinit(void)
|
||
{
|
||
}
|
||
|
||
static void
|
||
missing(ulong addr, char *name)
|
||
{
|
||
static int firstmiss = 1;
|
||
|
||
if (addr == 0) {
|
||
iprint("address zero for %s\n", name);
|
||
return;
|
||
}
|
||
if (probeaddr(addr) >= 0)
|
||
return;
|
||
missed++;
|
||
if (firstmiss) {
|
||
iprint("missing:");
|
||
firstmiss = 0;
|
||
} else
|
||
iprint(",\n\t");
|
||
iprint(" %s at %#lux", name, addr);
|
||
}
|
||
|
||
/* verify that all the necessary device registers are accessible */
|
||
void
|
||
chkmissing(void)
|
||
{
|
||
delay(10);
|
||
missing(KZERO, "dram");
|
||
missing(soc.intr, "intr ctlr");
|
||
missing(soc.intrdist, "intr distrib");
|
||
missing(soc.tmr[0], "tegra timer1");
|
||
missing(soc.uart[0], "console uart");
|
||
missing(soc.pci, "pcie");
|
||
missing(soc.ether, "ether8169");
|
||
missing(soc.µs, "µs counter");
|
||
if (missed)
|
||
iprint("\n");
|
||
delay(10);
|
||
}
|
||
|
||
void
|
||
archflashwp(Flash*, int)
|
||
{
|
||
}
|
||
|
||
/*
|
||
* for ../port/devflash.c:/^flashreset
|
||
* retrieve flash type, virtual base and length and return 0;
|
||
* return -1 on error (no flash)
|
||
*/
|
||
int
|
||
archflashreset(int bank, Flash *f)
|
||
{
|
||
if(bank != 0)
|
||
return -1;
|
||
panic("archflashreset: rewrite for nor & nand flash on ts");
|
||
/*
|
||
* this is set up for the igepv2 board.
|
||
*/
|
||
f->type = "onenand";
|
||
f->addr = (void*)VIRTNOR; /* mapped here by archreset */
|
||
f->size = 0; /* done by probe */
|
||
f->width = 1;
|
||
f->interleave = 0;
|
||
return 0;
|
||
}
|