128ea44a89
a portable SG_NOEXEC segment attribute was added to allow non-executable (physical) segments. which will set the PTENOEXEC bits for putmmu(). in the future, this can be used to make non-executable stack / bss segments. the SG_DEVICE attribute was added to distinguish between mmio regions and uncached memory. only matterns on arm64. on arm, theres the issue that PTEUNCACHED would have no bits set when using the hardware bit definitions. this is the reason bcm, kw, teg2 and omap kernels use arteficial PTE constants. on zynq, the XN bit was used as a hack to give PTEUNCACHED a non-zero value and when the bit is clear then cache attributes where added to the pte. to fix this, PTECACHED constant was added. the portable mmu code in fault.c will now explicitely set PTECACHED bits for cached memory and PTEUNCACHED for uncached memory. that way the hardware bit definitions can be used everywhere.
276 lines
7.6 KiB
C
276 lines
7.6 KiB
C
/*
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* Memory and machine-specific definitions. Used in C and assembler.
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*/
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#define MIN(a, b) ((a) < (b)? (a): (b))
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#define MAX(a, b) ((a) > (b)? (a): (b))
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/*
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* Sizes
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*/
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#define BI2BY 8 /* bits per byte */
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#define BI2WD 32 /* bits per word */
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#define BY2WD 4 /* bytes per word */
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#define BY2V 8 /* bytes per vlong */
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#define ROUND(s, sz) (((s)+((sz)-1))&~((sz)-1))
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#define PGROUND(s) ROUND(s, BY2PG)
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#define MAXBY2PG (16*1024) /* rounding for UTZERO in executables; see mkfile */
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#define UTROUND(t) ROUNDUP((t), MAXBY2PG)
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#ifndef BIGPAGES
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#define BY2PG 4096 /* bytes per page */
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#define PGSHIFT 12 /* log2(BY2PG) */
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#define PGSZ PGSZ4K
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#else
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/* 16K pages work very poorly */
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#define BY2PG (16*1024) /* bytes per page */
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#define PGSHIFT 14 /* log2(BY2PG) */
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#define PGSZ PGSZ16K
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#endif
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#define KSTACK (8*1024) /* Size of kernel stack */
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#define MACHSIZE (BY2PG+KSTACK)
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#define WD2PG (BY2PG/BY2WD) /* words per page */
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#define MAXMACH 1 /* max # cpus system can run; see active.machs */
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#define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
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#define BLOCKALIGN 16
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#define CACHELINESZ 32 /* mips24k */
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#define ICACHESIZE (64*1024) /* rb450g */
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#define DCACHESIZE (32*1024) /* rb450g */
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#define MASK(w) FMASK(0, w)
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/*
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* Time
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*/
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#define HZ 100 /* clock frequency */
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#define MS2HZ (1000/HZ) /* millisec per clock tick */
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#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
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/*
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* CP0 registers
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*/
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#define INDEX 0
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#define RANDOM 1
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#define TLBPHYS0 2 /* aka ENTRYLO0 */
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#define TLBPHYS1 3 /* aka ENTRYLO1 */
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#define CONTEXT 4
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#define PAGEMASK 5
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#define WIRED 6
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#define BADVADDR 8
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#define COUNT 9
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#define TLBVIRT 10 /* aka ENTRYHI */
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#define COMPARE 11
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#define STATUS 12
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#define CAUSE 13
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#define EPC 14
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#define PRID 15
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#define CONFIG 16
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#define LLADDR 17
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#define WATCHLO 18
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#define WATCHHI 19
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#define DEBUGREG 23
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#define DEPC 24
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#define PERFCOUNT 25
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#define CACHEECC 26
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#define CACHEERR 27
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#define TAGLO 28
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#define TAGHI 29
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#define ERROREPC 30
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#define DESAVE 31
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/*
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* M(STATUS) bits
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*/
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#define KMODEMASK 0x0000001f
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#define IE 0x00000001 /* master interrupt enable */
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#define EXL 0x00000002 /* exception level */
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#define ERL 0x00000004 /* error level */
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#define KSUPER 0x00000008
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#define KUSER 0x00000010
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#define KSU 0x00000018
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#define UX 0x00000020
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#define SX 0x00000040
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#define KX 0x00000080
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#define INTMASK 0x0000ff00
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#define SW0 0x00000100
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#define SW1 0x00000200
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#define INTR0 0x00000100 /* interrupt enable bits */
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#define INTR1 0x00000200
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#define INTR2 0x00000400
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#define INTR3 0x00000800
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#define INTR4 0x00001000
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#define INTR5 0x00002000
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#define INTR6 0x00004000
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#define INTR7 0x00008000
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#define DE 0x00010000
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#define TS 0x00200000 /* tlb shutdown; on 24k at least */
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#define BEV 0x00400000 /* bootstrap exception vectors */
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#define RE 0x02000000 /* reverse-endian in user mode */
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#define FR 0x04000000 /* enable 32 FP regs */
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#define CU0 0x10000000
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#define CU1 0x20000000 /* FPU enable */
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/*
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* M(CONFIG) bits
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*/
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#define CFG_K0 7 /* kseg0 cachability */
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#define CFG_MM (1<<18) /* write-through merging enabled */
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/*
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* M(CAUSE) bits
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*/
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#define BD (1<<31) /* last excep'n occurred in branch delay slot */
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/*
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* Exception codes
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*/
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#define EXCMASK 0x1f /* mask of all causes */
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#define CINT 0 /* external interrupt */
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#define CTLBM 1 /* TLB modification: store to unwritable page */
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#define CTLBL 2 /* TLB miss (load or fetch) */
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#define CTLBS 3 /* TLB miss (store) */
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#define CADREL 4 /* address error (load or fetch) */
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#define CADRES 5 /* address error (store) */
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#define CBUSI 6 /* bus error (fetch) */
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#define CBUSD 7 /* bus error (data load or store) */
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#define CSYS 8 /* system call */
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#define CBRK 9 /* breakpoint */
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#define CRES 10 /* reserved instruction */
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#define CCPU 11 /* coprocessor unusable */
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#define COVF 12 /* arithmetic overflow */
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#define CTRAP 13 /* trap */
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#define CVCEI 14 /* virtual coherence exception (instruction) */
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#define CFPE 15 /* floating point exception */
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#define CTLBRI 19 /* tlb read-inhibit */
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#define CTLBXI 20 /* tlb execute-inhibit */
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#define CWATCH 23 /* watch exception */
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#define CMCHK 24 /* machine checkcore */
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#define CCACHERR 30 /* cache error */
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#define CVCED 31 /* virtual coherence exception (data) */
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/*
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* M(CACHEECC) a.k.a. ErrCtl bits
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*/
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#define PE (1<<31)
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#define LBE (1<<25)
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#define WABE (1<<24)
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/*
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* Trap vectors
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*/
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#define UTLBMISS (KSEG0+0x000)
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#define XEXCEPTION (KSEG0+0x080)
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#define CACHETRAP (KSEG0+0x100)
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#define EXCEPTION (KSEG0+0x180)
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/*
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* Magic registers
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*/
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#define USER 24 /* R24 is up-> */
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#define MACH 25 /* R25 is m-> */
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#define UREGSIZE 0xA0 /* sizeof(Ureg)+8 */
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/*
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* MMU
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*/
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#define PGSZ4K (0x00<<13)
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#define PGSZ16K (0x03<<13) /* on 24k */
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#define PGSZ64K (0x0F<<13)
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#define PGSZ256K (0x3F<<13)
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#define PGSZ1M (0xFF<<13)
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#define PGSZ4M (0x3FF<<13)
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#define PGSZ8M (0x7FF<<13) /* not on 24k */
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#define PGSZ16M (0xFFF<<13)
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#define PGSZ64M (0x3FFF<<13) /* on 24k */
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#define PGSZ256M (0xFFFF<<13) /* on 24k */
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/* mips address spaces, tlb-mapped unless marked otherwise */
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#define KUSEG 0x00000000 /* user process */
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#define KSEG0 0x80000000 /* kernel (direct mapped, cached) */
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#define KSEG1 0xA0000000 /* kernel (direct mapped, uncached: i/o) */
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#define KSEG2 0xC0000000 /* kernel, was used for TSTKTOP */
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#define KSEG3 0xE0000000 /* kernel, used by kmap */
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#define KSEGM 0xE0000000 /* mask to check which seg */
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/*
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* Fundamental addresses
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*/
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#define REBOOTADDR KADDR(0x1000) /* just above vectors */
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#define MACHADDR 0x88014000 /* Mach structures */
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#define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE))
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#define KMAPADDR 0xE0000000 /* kmap'd addresses */
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#define SPBADDR 0x80001000
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#define PIDXSHFT 12
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#ifndef BIGPAGES
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#define NCOLOR 8
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#define PIDX ((NCOLOR-1)<<PIDXSHFT)
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#define getpgcolor(a) (((ulong)(a)>>PIDXSHFT) % NCOLOR)
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#else
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/* no cache aliases are possible with pages of 16K or larger */
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#define NCOLOR 1
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#define PIDX 0
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#define getpgcolor(a) 0
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#endif
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#define KMAPSHIFT 15
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#define PTEGLOBL (1<<0)
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#define PTEVALID (1<<1)
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#define PTEWRITE (1<<2)
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#define PTERONLY 0
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#define PTEALGMASK (7<<3)
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#define PTENONCOHERWT (0<<3) /* cached, write-through (slower) */
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#define PTEUNCACHED (2<<3)
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#define PTENONCOHERWB (3<<3) /* cached, write-back */
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#define PTEUNCACHEDACC (7<<3)
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/* rest are reserved on 24k */
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#define PTECOHERXCL (4<<3)
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#define PTECOHERXCLW (5<<3)
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#define PTECOHERUPDW (6<<3)
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/* how much faster is it? mflops goes from about .206 (WT) to .37 (WB) */
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// #define PTECACHED PTENONCOHERWT /* 24k erratum 48 disallows WB */
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#define PTECACHED PTENONCOHERWB
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#define PTEPID(n) (n)
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#define PTEMAPMEM (1024*1024)
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#define PTEPERTAB (PTEMAPMEM/BY2PG)
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#define SEGMAPSIZE 512
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#define SSEGMAPSIZE 16
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#define STLBLOG 15
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#define STLBSIZE (1<<STLBLOG) /* entries in the soft TLB */
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/* page # bits that don't fit in STLBLOG bits */
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#define HIPFNBITS (BI2WD - (PGSHIFT+1) - STLBLOG)
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#define KPTELOG 8
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#define KPTESIZE (1<<KPTELOG) /* entries in the kfault soft TLB */
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#define TLBPID(n) ((n)&0xFF)
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#define NTLBPID 256 /* # of pids (affects size of Mach) */
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#define NTLB 48 /* # of entries (r4k) */
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#define TLBOFF 1 /* first tlb entry (0 used within mmuswitch) */
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#define NKTLB 2 /* # of initial kfault tlb entries */
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#define TLBROFF (TLBOFF+NKTLB) /* first large IO window tlb entry */
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/*
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* Address spaces
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*/
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#define UZERO KUSEG /* base of user address space */
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#define UTZERO (UZERO+MAXBY2PG) /* 1st user text address; see mkfile */
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#define USTKTOP (KZERO-BY2PG) /* byte just beyond user stack */
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#define USTKSIZE (8*1024*1024) /* size of user stack */
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#define KZERO KSEG0 /* base of kernel address space */
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#define KTZERO (KZERO+0x08020000) /* first address in kernel text */
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