e4ce6aadac
we might as well handle the per process cycle counter in the portable part instead of duplicating the code in every arch and have inconsistent implementations. we now have a portable kenter() and kexit() function, that is ment to be used in trap/syscall from user, which updates the counters. some kernels missed initializing Mach.cyclefreq.
787 lines
16 KiB
C
787 lines
16 KiB
C
/*
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* omap3530 traps, exceptions, interrupts, system calls.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "../port/error.h"
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#include "ureg.h"
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#include "arm.h"
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enum {
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Nirqs = 96,
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Nvec = 8, /* # of vectors at start of lexception.s */
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Bi2long = BI2BY * sizeof(long),
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};
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extern int notify(Ureg*);
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extern int ldrexvalid;
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/* omap35x intc (aka mpu_intc) */
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typedef struct Intrregs Intrregs;
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struct Intrregs {
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/*
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* the manual inserts "INTCPS_" before each register name;
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* we'll just assume the prefix.
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*/
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uchar _pad0[4*4];
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ulong sysconfig;
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ulong sysstatus; /* ro */
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uchar _pad1[0x40 - 0x18];
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ulong sir_irq; /* ro */
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ulong sir_fiq; /* ro */
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ulong control;
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ulong protection;
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ulong idle;
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uchar _pad2[0x60 - 0x54];
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ulong irq_priority;
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ulong fiq_priority;
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ulong threshold;
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uchar _pad3[0x80 - 0x6c];
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struct Bits { /* bitmaps */
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ulong itr; /* ro: pending intrs (no mask) */
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ulong mir; /* interrupt mask: 1 means masked */
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ulong mir_clear; /* wo: 1 sets the bit */
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ulong mir_set; /* wo: 1 clears the bit */
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ulong isr_set; /* software interrupts */
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ulong isr_clear; /* wo */
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ulong pending_irq; /* ro */
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ulong pending_fiq; /* ro */
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} bits[3]; /* 3*32 = 96 (Nirqs) */
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ulong ilr[Nirqs];
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};
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enum {
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/* sysconfig bits */
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Softreset = 1<<1,
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/* sysstatus bits */
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Resetdone = 1<<0,
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/* sir_irq/fiq bits */
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Activeirq = MASK(7),
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/* control bits */
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Newirqagr = 1<<0,
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/* protection bits */
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Protection = 1<<0,
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/* irq/fiq_priority bits */
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Irqpriority = MASK(6),
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/* threshold bits */
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Prioritythreshold = MASK(8),
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/* ilr bits */
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Priority = MASK(8) - MASK(2),
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};
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typedef struct Vctl Vctl;
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typedef struct Vctl {
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Vctl* next; /* handlers on this vector */
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char *name; /* of driver, xallocated */
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void (*f)(Ureg*, void*); /* handler to call */
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void* a; /* argument to call it with */
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} Vctl;
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static Lock vctllock;
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static Vctl* vctl[Nirqs];
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/*
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* Layout at virtual address 0.
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*/
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typedef struct Vpage0 {
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void (*vectors[Nvec])(void);
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u32int vtable[Nvec];
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} Vpage0;
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static Vpage0 *vpage0;
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uvlong ninterrupt;
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uvlong ninterruptticks;
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int irqtooearly = 1;
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static volatile int probing, trapped;
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static int
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irqinuse(uint irq)
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{
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Intrregs *ip = (Intrregs *)PHYSINTC;
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/*
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* mir registers are odd: a 0 bit means intr unmasked (i.e.,
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* we've unmasked it because it's in use).
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*/
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return (ip->bits[irq / Bi2long].mir & (1 << (irq % Bi2long))) == 0;
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}
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static void
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intcmask(uint irq)
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{
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Intrregs *ip = (Intrregs *)PHYSINTC;
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ip->bits[irq / Bi2long].mir_set = 1 << (irq % Bi2long);
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coherence();
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}
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static void
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intcunmask(uint irq)
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{
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Intrregs *ip = (Intrregs *)PHYSINTC;
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ip->bits[irq / Bi2long].mir_clear = 1 << (irq % Bi2long);
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coherence();
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}
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static void
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intcmaskall(void)
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{
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int i;
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Intrregs *ip = (Intrregs *)PHYSINTC;
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for (i = 0; i < 3; i++)
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ip->bits[i].mir_set = ~0;
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coherence();
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}
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static void
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intcunmaskall(void)
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{
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int i;
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Intrregs *ip = (Intrregs *)PHYSINTC;
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for (i = 0; i < 3; i++)
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ip->bits[i].mir_clear = ~0;
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coherence();
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}
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static void
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intcinvertall(void)
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{
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int i, s;
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ulong bits;
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Intrregs *ip = (Intrregs *)PHYSINTC;
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s = splhi();
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for (i = 0; i < 3; i++) {
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bits = ip->bits[i].mir;
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ip->bits[i].mir_set = ~0; /* mask all */
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coherence();
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/* clearing enables only those intrs. that were disabled */
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ip->bits[i].mir_clear = bits;
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}
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coherence();
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splx(s);
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}
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static void
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intrsave(ulong buf[3])
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{
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int i;
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Intrregs *ip = (Intrregs *)PHYSINTC;
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for (i = 0; i < nelem(buf); i++)
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buf[i] = ip->bits[i].mir;
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coherence();
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}
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static void
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intrrestore(ulong buf[3])
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{
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int i, s;
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Intrregs *ip = (Intrregs *)PHYSINTC;
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s = splhi();
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for (i = 0; i < nelem(buf); i++) {
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ip->bits[i].mir_clear = ~0; /* unmask all */
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coherence();
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ip->bits[i].mir_set = buf[i]; /* mask previously disabled */
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}
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coherence();
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splx(s);
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}
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/*
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* set up for exceptions
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*/
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void
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trapinit(void)
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{
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int i;
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Intrregs *ip = (Intrregs *)PHYSINTC;
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/* set up the exception vectors */
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vpage0 = (Vpage0*)HVECTORS;
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memmove(vpage0->vectors, vectors, sizeof(vpage0->vectors));
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memmove(vpage0->vtable, vtable, sizeof(vpage0->vtable));
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cacheuwbinv();
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l2cacheuwbinv();
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/* set up the stacks for the interrupt modes */
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setr13(PsrMfiq, m->sfiq);
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setr13(PsrMirq, m->sirq);
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setr13(PsrMabt, m->sabt);
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setr13(PsrMund, m->sund);
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#ifdef HIGH_SECURITY
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setr13(PsrMmon, m->smon);
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#endif
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setr13(PsrMsys, m->ssys);
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intcmaskall();
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ip->control = 0;
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ip->threshold = Prioritythreshold; /* disable threshold */
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for (i = 0; i < Nirqs; i++)
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ip->ilr[i] = 0<<2 | 0; /* all intrs pri 0 & to irq, not fiq */
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irqtooearly = 0;
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coherence();
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}
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void
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intrsoff(void)
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{
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Intrregs *ip = (Intrregs *)PHYSINTC;
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intcmaskall();
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ip->control = Newirqagr; /* dismiss interrupt */
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coherence();
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}
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/*
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* enable an irq interrupt
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*/
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int
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irqenable(int irq, void (*f)(Ureg*, void*), void* a, char *name)
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{
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Vctl *v;
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if(irq >= nelem(vctl) || irq < 0)
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panic("irqenable irq %d", irq);
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if (irqtooearly) {
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iprint("irqenable for %d %s called too early\n", irq, name);
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return -1;
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}
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if(irqinuse(irq))
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print("irqenable: %s: irq %d already in use, chaining\n",
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name, irq);
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v = malloc(sizeof(Vctl));
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if (v == nil)
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panic("irqenable: malloc Vctl");
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v->f = f;
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v->a = a;
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v->name = malloc(strlen(name)+1);
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if (v->name == nil)
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panic("irqenable: malloc name");
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strcpy(v->name, name);
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lock(&vctllock);
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v->next = vctl[irq];
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vctl[irq] = v;
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intcunmask(irq);
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unlock(&vctllock);
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return 0;
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}
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/*
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* disable an irq interrupt
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*/
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int
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irqdisable(int irq, void (*f)(Ureg*, void*), void* a, char *name)
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{
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Vctl **vp, *v;
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if(irq >= nelem(vctl) || irq < 0)
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panic("irqdisable irq %d", irq);
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lock(&vctllock);
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for(vp = &vctl[irq]; v = *vp; vp = &v->next)
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if (v->f == f && v->a == a && strcmp(v->name, name) == 0){
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print("irqdisable: remove %s\n", name);
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*vp = v->next;
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free(v);
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break;
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}
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if(v == nil)
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print("irqdisable: irq %d, name %s not enabled\n", irq, name);
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if(vctl[irq] == nil){
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print("irqdisable: clear icmr bit %d\n", irq);
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intcmask(irq);
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}
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unlock(&vctllock);
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return 0;
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}
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/*
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* called by trap to handle access faults
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*/
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static void
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faultarm(Ureg *ureg, uintptr va, int user, int read)
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{
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int n, insyscall;
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char buf[ERRMAX];
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if(up == nil) {
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dumpregs(ureg);
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panic("fault: nil up in faultarm, accessing %#p", va);
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}
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insyscall = up->insyscall;
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up->insyscall = 1;
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n = fault(va, ureg->pc, read);
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if(n < 0){
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if(!user){
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dumpregs(ureg);
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panic("fault: kernel accessing %#p", va);
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}
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/* don't dump registers; programs suicide all the time */
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snprint(buf, sizeof buf, "sys: trap: fault %s va=%#p",
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read? "read": "write", va);
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postnote(up, 1, buf, NDebug);
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}
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up->insyscall = insyscall;
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}
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/*
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* called by trap to handle interrupts.
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* returns true iff a clock interrupt, thus maybe reschedule.
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*/
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static int
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irq(Ureg* ureg)
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{
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int clockintr;
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uint irqno, handled, t, ticks = perfticks();
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Intrregs *ip = (Intrregs *)PHYSINTC;
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Vctl *v;
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static int nesting, lastirq = -1;
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handled = 0;
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irqno = ip->sir_irq & Activeirq;
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if (irqno >= 37 && irqno <= 47) /* this is a clock intr? */
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m->inclockintr++; /* yes, count nesting */
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lastirq = irqno;
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if (irqno >= nelem(vctl)) {
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iprint("trap: irq %d >= # vectors (%d)\n", irqno, nelem(vctl));
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ip->control = Newirqagr; /* dismiss interrupt */
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return 0;
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}
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++nesting;
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for(v = vctl[irqno]; v != nil; v = v->next)
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if (v->f) {
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if (islo())
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panic("trap: pl0 before trap handler for %s",
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v->name);
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v->f(ureg, v->a);
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if (islo())
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panic("trap: %s lowered pl", v->name);
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// splhi(); /* in case v->f lowered pl */
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handled++;
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}
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if(!handled) {
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iprint("unexpected interrupt: irq %d", irqno);
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switch (irqno) {
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case 56:
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case 57:
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iprint(" (IC)");
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break;
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case 83:
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case 86:
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case 94:
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iprint(" (MMC)");
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break;
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}
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if(irqno < nelem(vctl)) {
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intcmask(irqno);
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iprint(", now masked");
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}
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iprint("\n");
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}
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t = perfticks();
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ninterrupt++;
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if(t < ticks)
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ninterruptticks += ticks-t;
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else
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ninterruptticks += t-ticks;
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ip->control = Newirqagr; /* dismiss interrupt */
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coherence();
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--nesting;
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clockintr = m->inclockintr == 1;
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if (irqno >= 37 && irqno <= 47)
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m->inclockintr--;
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return clockintr;
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}
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/*
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* returns 1 if the instruction writes memory, 0 otherwise
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*/
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int
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writetomem(ulong inst)
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{
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/* swap always write memory */
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if((inst & 0x0FC00000) == 0x01000000)
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return 1;
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|
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/* loads and stores are distinguished by bit 20 */
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if(inst & (1<<20))
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return 0;
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return 1;
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}
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|
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void prgpmcerrs(void);
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|
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/*
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* here on all exceptions other than syscall (SWI)
|
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*/
|
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void
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trap(Ureg *ureg)
|
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{
|
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int clockintr, user, x, rv, rem;
|
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ulong inst, fsr;
|
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uintptr va;
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char buf[ERRMAX];
|
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splhi(); /* paranoia */
|
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if(up != nil)
|
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rem = ((char*)ureg)-up->kstack;
|
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else
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rem = ((char*)ureg)-((char*)m+sizeof(Mach));
|
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if(rem < 1024) {
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iprint("trap: %d stack bytes left, up %#p ureg %#p at pc %#lux\n",
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rem, up, ureg, ureg->pc);
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delay(1000);
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dumpstack();
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panic("trap: %d stack bytes left, up %#p ureg %#p at pc %#lux",
|
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rem, up, ureg, ureg->pc);
|
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}
|
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|
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user = kenter(ureg);
|
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/*
|
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* All interrupts/exceptions should be resumed at ureg->pc-4,
|
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* except for Data Abort which resumes at ureg->pc-8.
|
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*/
|
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if(ureg->type == (PsrMabt+1))
|
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ureg->pc -= 8;
|
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else
|
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ureg->pc -= 4;
|
|
|
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clockintr = 0; /* if set, may call sched() before return */
|
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switch(ureg->type){
|
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default:
|
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panic("unknown trap; type %#lux, psr mode %#lux", ureg->type,
|
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ureg->psr & PsrMask);
|
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break;
|
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case PsrMirq:
|
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ldrexvalid = 0;
|
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clockintr = irq(ureg);
|
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m->intr++;
|
|
break;
|
|
case PsrMabt: /* prefetch fault */
|
|
ldrexvalid = 0;
|
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x = ifsrget();
|
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fsr = (x>>7) & 0x8 | x & 0x7;
|
|
switch(fsr){
|
|
case 0x02: /* instruction debug event (BKPT) */
|
|
if(user){
|
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snprint(buf, sizeof buf, "sys: breakpoint");
|
|
postnote(up, 1, buf, NDebug);
|
|
}else{
|
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iprint("kernel bkpt: pc %#lux inst %#ux\n",
|
|
ureg->pc, *(u32int*)ureg->pc);
|
|
panic("kernel bkpt");
|
|
}
|
|
break;
|
|
default:
|
|
faultarm(ureg, ureg->pc, user, 1);
|
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break;
|
|
}
|
|
break;
|
|
case PsrMabt+1: /* data fault */
|
|
ldrexvalid = 0;
|
|
va = farget();
|
|
inst = *(ulong*)(ureg->pc);
|
|
/* bits 12 and 10 have to be concatenated with status */
|
|
x = fsrget();
|
|
fsr = (x>>7) & 0x20 | (x>>6) & 0x10 | x & 0xf;
|
|
if (probing && !user) {
|
|
if (trapped++ > 0)
|
|
panic("trap: recursive probe %#lux", va);
|
|
ureg->pc += 4; /* continue at next instruction */
|
|
break;
|
|
}
|
|
switch(fsr){
|
|
default:
|
|
case 0xa: /* ? was under external abort */
|
|
panic("unknown data fault, 6b fsr %#lux", fsr);
|
|
break;
|
|
case 0x0:
|
|
panic("vector exception at %#lux", ureg->pc);
|
|
break;
|
|
case 0x1: /* alignment fault */
|
|
case 0x3: /* access flag fault (section) */
|
|
if(user){
|
|
snprint(buf, sizeof buf,
|
|
"sys: alignment: pc %#lux va %#p\n",
|
|
ureg->pc, va);
|
|
postnote(up, 1, buf, NDebug);
|
|
} else
|
|
panic("kernel alignment: pc %#lux va %#p", ureg->pc, va);
|
|
break;
|
|
case 0x2:
|
|
panic("terminal exception at %#lux", ureg->pc);
|
|
break;
|
|
case 0x4: /* icache maint fault */
|
|
case 0x6: /* access flag fault (page) */
|
|
case 0x8: /* precise external abort, non-xlat'n */
|
|
case 0x28:
|
|
case 0xc: /* l1 translation, precise ext. abort */
|
|
case 0x2c:
|
|
case 0xe: /* l2 translation, precise ext. abort */
|
|
case 0x2e:
|
|
case 0x16: /* imprecise ext. abort, non-xlt'n */
|
|
case 0x36:
|
|
panic("external abort %#lux pc %#lux addr %#p",
|
|
fsr, ureg->pc, va);
|
|
break;
|
|
case 0x1c: /* l1 translation, precise parity err */
|
|
case 0x1e: /* l2 translation, precise parity err */
|
|
case 0x18: /* imprecise parity or ecc err */
|
|
panic("translation parity error %#lux pc %#lux addr %#p",
|
|
fsr, ureg->pc, va);
|
|
break;
|
|
case 0x5: /* translation fault, no section entry */
|
|
case 0x7: /* translation fault, no page entry */
|
|
faultarm(ureg, va, user, !writetomem(inst));
|
|
break;
|
|
case 0x9:
|
|
case 0xb:
|
|
/* domain fault, accessing something we shouldn't */
|
|
if(user){
|
|
snprint(buf, sizeof buf,
|
|
"sys: access violation: pc %#lux va %#p\n",
|
|
ureg->pc, va);
|
|
postnote(up, 1, buf, NDebug);
|
|
} else
|
|
panic("kernel access violation: pc %#lux va %#p",
|
|
ureg->pc, va);
|
|
break;
|
|
case 0xd:
|
|
case 0xf:
|
|
/* permission error, copy on write or real permission error */
|
|
faultarm(ureg, va, user, !writetomem(inst));
|
|
break;
|
|
}
|
|
break;
|
|
case PsrMund: /* undefined instruction */
|
|
if(user){
|
|
if(seg(up, ureg->pc, 0) != nil &&
|
|
*(u32int*)ureg->pc == 0xD1200070){
|
|
snprint(buf, sizeof buf, "sys: breakpoint");
|
|
postnote(up, 1, buf, NDebug);
|
|
}else{
|
|
/* look for floating point instructions to interpret */
|
|
x = spllo();
|
|
rv = fpiarm(ureg);
|
|
splx(x);
|
|
if(rv == 0){
|
|
ldrexvalid = 0;
|
|
snprint(buf, sizeof buf,
|
|
"undefined instruction: pc %#lux\n",
|
|
ureg->pc);
|
|
postnote(up, 1, buf, NDebug);
|
|
}
|
|
}
|
|
}else{
|
|
if (ureg->pc & 3) {
|
|
iprint("rounding fault pc %#lux down to word\n",
|
|
ureg->pc);
|
|
ureg->pc &= ~3;
|
|
}
|
|
iprint("undefined instruction: pc %#lux inst %#ux\n",
|
|
ureg->pc, ((u32int*)ureg->pc)[-2]);
|
|
panic("undefined instruction");
|
|
}
|
|
break;
|
|
}
|
|
splhi();
|
|
|
|
/* delaysched set because we held a lock or because our quantum ended */
|
|
if(up && up->delaysched && clockintr){
|
|
ldrexvalid = 0;
|
|
sched(); /* can cause more traps */
|
|
splhi();
|
|
}
|
|
|
|
if(user){
|
|
if(up->procctl || up->nnote)
|
|
notify(ureg);
|
|
kexit(ureg);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Fill in enough of Ureg to get a stack trace, and call a function.
|
|
* Used by debugging interface rdb.
|
|
*/
|
|
void
|
|
callwithureg(void (*fn)(Ureg*))
|
|
{
|
|
Ureg ureg;
|
|
|
|
ureg.pc = getcallerpc(&fn);
|
|
ureg.sp = (uintptr)&fn;
|
|
fn(&ureg);
|
|
}
|
|
|
|
static void
|
|
dumpstackwithureg(Ureg *ureg)
|
|
{
|
|
int x;
|
|
uintptr l, v, i, estack;
|
|
char *s;
|
|
|
|
dumpregs(ureg);
|
|
if((s = getconf("*nodumpstack")) != nil && strcmp(s, "0") != 0){
|
|
iprint("dumpstack disabled\n");
|
|
return;
|
|
}
|
|
iprint("dumpstack\n");
|
|
|
|
x = 0;
|
|
x += iprint("ktrace /kernel/path %#.8lux %#.8lux %#.8lux # pc, sp, link\n",
|
|
ureg->pc, ureg->sp, ureg->r14);
|
|
delay(20);
|
|
i = 0;
|
|
if(up
|
|
&& (uintptr)&l >= (uintptr)up->kstack
|
|
&& (uintptr)&l <= (uintptr)up->kstack+KSTACK)
|
|
estack = (uintptr)up->kstack+KSTACK;
|
|
else if((uintptr)&l >= (uintptr)m->stack
|
|
&& (uintptr)&l <= (uintptr)m+MACHSIZE)
|
|
estack = (uintptr)m+MACHSIZE;
|
|
else
|
|
return;
|
|
x += iprint("estackx %p\n", estack);
|
|
|
|
for(l = (uintptr)&l; l < estack; l += sizeof(uintptr)){
|
|
v = *(uintptr*)l;
|
|
if((KTZERO < v && v < (uintptr)etext) || estack-l < 32){
|
|
x += iprint("%.8p ", v);
|
|
delay(20);
|
|
i++;
|
|
}
|
|
if(i == 8){
|
|
i = 0;
|
|
x += iprint("\n");
|
|
delay(20);
|
|
}
|
|
}
|
|
if(i)
|
|
iprint("\n");
|
|
}
|
|
|
|
void
|
|
dumpstack(void)
|
|
{
|
|
callwithureg(dumpstackwithureg);
|
|
}
|
|
|
|
/*
|
|
* dump system control coprocessor registers
|
|
*/
|
|
static void
|
|
dumpscr(void)
|
|
{
|
|
iprint("0:\t%#8.8ux id\n", cpidget());
|
|
iprint("\t%8.8#ux ct\n", cpctget());
|
|
iprint("1:\t%#8.8ux control\n", controlget());
|
|
iprint("2:\t%#8.8ux ttb\n", ttbget());
|
|
iprint("3:\t%#8.8ux dac\n", dacget());
|
|
iprint("4:\t(reserved)\n");
|
|
iprint("5:\t%#8.8ux fsr\n", fsrget());
|
|
iprint("6:\t%#8.8ux far\n", farget());
|
|
iprint("7:\twrite-only cache\n");
|
|
iprint("8:\twrite-only tlb\n");
|
|
iprint("13:\t%#8.8ux pid\n", pidget());
|
|
delay(10);
|
|
}
|
|
|
|
/*
|
|
* dump general registers
|
|
*/
|
|
static void
|
|
dumpgpr(Ureg* ureg)
|
|
{
|
|
if(up != nil)
|
|
iprint("cpu%d: registers for %s %lud\n",
|
|
m->machno, up->text, up->pid);
|
|
else
|
|
iprint("cpu%d: registers for kernel\n", m->machno);
|
|
|
|
delay(20);
|
|
iprint("%#8.8lux\tr0\n", ureg->r0);
|
|
iprint("%#8.8lux\tr1\n", ureg->r1);
|
|
iprint("%#8.8lux\tr2\n", ureg->r2);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr3\n", ureg->r3);
|
|
iprint("%#8.8lux\tr4\n", ureg->r4);
|
|
iprint("%#8.8lux\tr5\n", ureg->r5);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr6\n", ureg->r6);
|
|
iprint("%#8.8lux\tr7\n", ureg->r7);
|
|
iprint("%#8.8lux\tr8\n", ureg->r8);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr9 (up)\n", ureg->r9);
|
|
iprint("%#8.8lux\tr10 (m)\n", ureg->r10);
|
|
iprint("%#8.8lux\tr11 (loader temporary)\n", ureg->r11);
|
|
iprint("%#8.8lux\tr12 (SB)\n", ureg->r12);
|
|
delay(20);
|
|
iprint("%#8.8lux\tr13 (sp)\n", ureg->r13);
|
|
iprint("%#8.8lux\tr14 (link)\n", ureg->r14);
|
|
iprint("%#8.8lux\tr15 (pc)\n", ureg->pc);
|
|
delay(20);
|
|
iprint("%10.10lud\ttype\n", ureg->type);
|
|
iprint("%#8.8lux\tpsr\n", ureg->psr);
|
|
delay(20);
|
|
}
|
|
|
|
void
|
|
dumpregs(Ureg* ureg)
|
|
{
|
|
dumpgpr(ureg);
|
|
dumpscr();
|
|
}
|
|
|
|
vlong
|
|
probeaddr(uintptr addr)
|
|
{
|
|
vlong v;
|
|
static Lock fltlck;
|
|
|
|
ilock(&fltlck);
|
|
trapped = 0;
|
|
probing = 1;
|
|
coherence();
|
|
|
|
v = *(ulong *)addr; /* this may cause a fault */
|
|
USED(probing);
|
|
coherence();
|
|
|
|
probing = 0;
|
|
coherence();
|
|
if (trapped)
|
|
v = -1;
|
|
iunlock(&fltlck);
|
|
return v;
|
|
}
|