128ea44a89
a portable SG_NOEXEC segment attribute was added to allow non-executable (physical) segments. which will set the PTENOEXEC bits for putmmu(). in the future, this can be used to make non-executable stack / bss segments. the SG_DEVICE attribute was added to distinguish between mmio regions and uncached memory. only matterns on arm64. on arm, theres the issue that PTEUNCACHED would have no bits set when using the hardware bit definitions. this is the reason bcm, kw, teg2 and omap kernels use arteficial PTE constants. on zynq, the XN bit was used as a hack to give PTEUNCACHED a non-zero value and when the bit is clear then cache attributes where added to the pte. to fix this, PTECACHED constant was added. the portable mmu code in fault.c will now explicitely set PTECACHED bits for cached memory and PTEUNCACHED for uncached memory. that way the hardware bit definitions can be used everywhere.
195 lines
5.8 KiB
C
195 lines
5.8 KiB
C
/*
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* Memory and machine-specific definitions. Used in C and assembler.
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*/
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/*
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* Sizes
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*/
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#define BI2BY 8 /* bits per byte */
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#define BI2WD 32 /* bits per word */
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#define BY2WD 4 /* bytes per word */
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#define BY2V 8 /* bytes per vlong */
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#define BY2PG 4096 /* bytes per page */
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#define WD2PG (BY2PG/BY2WD) /* words per page */
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#define PGSHIFT 12 /* log(BY2PG) */
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#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
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#define PGROUND(s) ROUND(s, BY2PG)
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#define CACHELINELOG 4
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#define CACHELINESZ (1<<CACHELINELOG)
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#define BLOCKALIGN CACHELINESZ
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#define MHz 1000000
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#define BY2PTE 8 /* bytes per pte entry */
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#define BY2PTEG 64 /* bytes per pte group */
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#define MAXMACH 1 /* max # cpus system can run */
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#define MACHSIZE BY2PG
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#define KSTACK 4096 /* Size of kernel stack */
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/*
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* Time
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*/
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#define HZ 100 /* clock frequency */
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#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
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/*
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* Standard PPC Special Purpose Registers (OEA and VEA)
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*/
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#define DSISR 18
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#define DAR 19 /* Data Address Register */
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#define DEC 22 /* Decrementer */
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#define SDR1 25
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#define SRR0 26 /* Saved Registers (exception) */
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#define SRR1 27
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#define SPRG0 272 /* Supervisor Private Registers */
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#define SPRG1 273
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#define SPRG2 274
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#define SPRG3 275
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#define ASR 280 /* Address Space Register */
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#define EAR 282 /* External Access Register (optional) */
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#define TBRU 269 /* Time base Upper/Lower (Reading) */
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#define TBRL 268
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#define TBWU 284 /* Time base Upper/Lower (Writing) */
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#define TBWL 285
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#define PVR 287 /* Processor Version */
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#define IABR 1010 /* Instruction Address Breakpoint Register (optional) */
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#define DABR 1013 /* Data Address Breakpoint Register (optional) */
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#define FPECR 1022 /* Floating-Point Exception Cause Register (optional) */
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#define PIR 1023 /* Processor Identification Register (optional) */
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#define IBATU(i) (528+2*(i)) /* Instruction BAT register (upper) */
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#define IBATL(i) (529+2*(i)) /* Instruction BAT register (lower) */
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#define DBATU(i) (536+2*(i)) /* Data BAT register (upper) */
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#define DBATL(i) (537+2*(i)) /* Data BAT register (lower) */
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/*
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* PPC604e-specific Special Purpose Registers (OEA)
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*/
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#define HID0 1008 /* Hardware Implementation Dependant Register 0 */
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#define HID1 1009 /* Hardware Implementation Dependant Register 1 */
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#define PMC1 953 /* Performance Monitor Counter 1 */
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#define PMC2 954 /* Performance Monitor Counter 2 */
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#define PMC3 957 /* Performance Monitor Counter 3 */
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#define PMC4 958 /* Performance Monitor Counter 4 */
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#define MMCR0 952 /* Monitor Control Register 0 */
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#define MMCR1 956 /* Monitor Control Register 0 */
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#define SIA 955 /* Sampled Instruction Address */
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#define SDA 959 /* Sampled Data Address */
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#define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */
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/*
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* Bit encodings for Machine State Register (MSR)
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*/
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#define MSR_POW BIT(13) /* Enable Power Management */
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#define MSR_ILE BIT(15) /* Interrupt Little-Endian enable */
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#define MSR_EE BIT(16) /* External Interrupt enable */
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#define MSR_PR BIT(17) /* Supervisor/User privelege */
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#define MSR_FP BIT(18) /* Floating Point enable */
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#define MSR_ME BIT(19) /* Machine Check enable */
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#define MSR_FE0 BIT(20) /* Floating Exception mode 0 */
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#define MSR_SE BIT(21) /* Single Step (optional) */
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#define MSR_BE BIT(22) /* Branch Trace (optional) */
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#define MSR_FE1 BIT(23) /* Floating Exception mode 1 */
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#define MSR_IP BIT(25) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR BIT(26) /* Instruction MMU enable */
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#define MSR_DR BIT(27) /* Data MMU enable */
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#define MSR_PM BIT(29) /* Performance Monitor marked mode (604e specific) */
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#define MSR_RI BIT(30) /* Recoverable Exception */
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#define MSR_LE BIT(31) /* Little-Endian enable */
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/*
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* Exception codes (trap vectors)
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*/
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#define CRESET 0x01
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#define CMCHECK 0x02
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#define CDSI 0x03
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#define CISI 0x04
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#define CEI 0x05
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#define CALIGN 0x06
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#define CPROG 0x07
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#define CFPU 0x08
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#define CDEC 0x09
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#define CSYSCALL 0x0C
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#define CTRACE 0x0D /* optional */
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#define CFPA 0x0E /* optional */
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/* PPC604e-specific: */
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#define CPERF 0x0F /* performance monitoring */
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#define CIBREAK 0x13
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#define CSMI 0x14
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/*
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* Magic registers
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*/
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#define MACH 30 /* R30 is m-> */
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#define USER 29 /* R29 is up-> */
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/*
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* virtual MMU
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*/
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#define PTEMAPMEM (1024*1024)
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#define PTEPERTAB (PTEMAPMEM/BY2PG)
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#define SEGMAPSIZE 1984
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#define SSEGMAPSIZE 16
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#define PPN(x) ((x)&~(BY2PG-1))
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/*
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* First pte word
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*/
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#define PTE0(v, vsid, h, va) (((v)<<31)|((vsid)<<7)|((h)<<6)|(((va)>>22)&0x3f))
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/*
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* Second pte word; WIMG & PP(RW/RO) common to page table and BATs
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*/
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#define PTE1_W BIT(25)
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#define PTE1_I BIT(26)
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#define PTE1_M BIT(27)
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#define PTE1_G BIT(28)
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#define PTE1_RW BIT(30)
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#define PTE1_RO BIT(31)
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/*
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* PTE bits for fault.c. These belong to the second PTE word. Validity is
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* implied for putmmu(), and we always set PTE0_V. PTEVALID is used
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* here to set cache policy bits on a global basis.
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*/
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#define PTEVALID 0
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#define PTEWRITE PTE1_RW
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#define PTERONLY PTE1_RO
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#define PTEUNCACHED PTE1_I
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#define PTECACHED 0
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/*
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* Address spaces
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*/
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#define UZERO 0 /* base of user address space */
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#define UTZERO (UZERO+BY2PG) /* first address in user text */
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#define KZERO 0x80000000 /* base of kernel address space */
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#define KTZERO (KZERO+0x4000) /* first address in kernel text */
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#define USTKTOP KZERO /* byte just beyond user stack */
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#define USTKSIZE (4*1024*1024) /* size of user stack */
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#define UREGSIZE ((8+32)*4)
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#define PCIMEM0 0xf0000000
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#define PCISIZE0 0x0e000000
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#define PCIMEM1 0xc0000000
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#define PCISIZE1 0x30000000
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#define IOMEM 0xfe000000
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#define IOSIZE 0x00800000
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#define FALCON 0xfef80000
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#define RAVEN 0xfeff0000
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#define FLASHA 0xff000000
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#define FLASHB 0xff800000
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#define FLASHAorB 0xfff00000
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#define isphys(x) (((ulong)x&KZERO)!=0)
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#define getpgcolor(a) 0
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