4f85115526
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
43 lines
806 B
C
43 lines
806 B
C
enum {
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IrqCLOCK = 0,
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IrqKBD = 1,
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IrqUART1 = 3,
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IrqUART0 = 4,
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IrqPCMCIA = 5,
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IrqFLOPPY = 6,
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IrqLPT = 7,
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IrqIRQ7 = 7,
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IrqAUX = 12, /* PS/2 port */
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IrqIRQ13 = 13, /* coprocessor on 386 */
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IrqATA0 = 14,
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IrqATA1 = 15,
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MaxIrqPIC = 15,
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VectorPIC = 32,
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MaxVectorPIC = VectorPIC+MaxIrqPIC,
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};
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typedef struct Vctl {
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Vctl* next; /* handlers on this vector */
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char name[KNAMELEN]; /* of driver */
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int isintr; /* interrupt or fault/trap */
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int irq;
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int tbdf;
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int (*isr)(int); /* get isr bit for this irq */
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int (*eoi)(int); /* eoi */
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void (*f)(Ureg*, void*); /* handler to call */
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void* a; /* argument to call it with */
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} Vctl;
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enum {
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MaxEISA = 16,
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EISAconfig = 0xC80,
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};
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#define PCIWINDOW 0x80000000
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#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
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#define BUSUNKNOWN (-1)
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