775 lines
17 KiB
ArmAsm
775 lines
17 KiB
ArmAsm
/*
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* sheevaplug machine assist
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* arm926ej-s processor at 1.2GHz
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*
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* loader uses R11 as scratch.
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* R9 and R10 are used for `extern register' variables.
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*
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* ARM v7 arch. ref. man. (I know, this is v5) §B1.3.3 that
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* we don't need barriers around moves to CPSR. The ARM v6 manual
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* seems to be silent on the subject.
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*/
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#include "arm.s"
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/*
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* MCR and MRC are counter-intuitively named.
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* MCR coproc, opcode1, Rd, CRn, CRm[, opcode2] # arm -> coproc
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* MRC coproc, opcode1, Rd, CRn, CRm[, opcode2] # coproc -> arm
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*/
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/*
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* Entered here from Das U-Boot with MMU disabled.
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* Until the MMU is enabled it is OK to call functions provided
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* they are within ±32MiB relative and do not require any
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* local variables or more than one argument (i.e. there is
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* no stack).
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*/
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TEXT _start(SB), 1, $-4
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MOVW $setR12(SB), R12 /* load the SB */
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_main:
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/* SVC mode, interrupts disabled */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
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MOVW R1, CPSR
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BARRIERS
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/*
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* disable the MMU & caches,
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* switch to system permission & 32-bit addresses.
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*/
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MOVW $(CpCsystem|CpCd32|CpCi32), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0)
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ISB
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/*
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* disable the Sheevaplug's L2 cache, invalidate all caches
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*/
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/* flush caches. 926ejs manual says we have to do it iteratively. */
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_dwbinv0:
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _dwbinv0
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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/* make the l2 cache pay attention */
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MOVW $(PHYSIO+0x20100), R1 /* CPUCSREG */
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MOVW (4*10)(R1), R2
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ORR $(1<<3), R2 /* cpu->l2cfg |= L2exists */
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MOVW R2, (4*10)(R1)
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ISB
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/* invalidate l2 cache */
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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ISB
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/* disable l2 cache. do this while l1 caches are off */
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MRC CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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/* disabling write allocation is probably for cortex-a8 errata 460075 */
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/* l2 off, no wr alloc, no streaming */
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BIC $(CpTCl2ena | CpTCl2wralloc | CpTCldcstream), R1
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MCR CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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BARRIERS
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/* flush caches. 926ejs manual says we have to do it iteratively. */
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_dwbinv1:
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _dwbinv1
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BARRIERS
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WAVE('\r')
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/* clear Mach */
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MOVW $PADDR(MACHADDR), R4 /* address of Mach */
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_machZ:
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MOVW R0, (R4)
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ADD $4, R4 /* bump PTE address */
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CMP.S $PADDR(L1+L1X(0)), R4
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BNE _machZ
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/*
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* set up the MMU page table
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*/
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/* clear all PTEs first, to provide a default */
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WAVE('\n')
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MOVW $PADDR(L1+L1X(0)), R4 /* address of PTE for 0 */
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_ptenv0:
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ZEROPTE()
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CMP.S $PADDR(L1+16*KiB), R4
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BNE _ptenv0
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/* double map of PHYSDRAM, KZERO to PHYSDRAM for first few MBs */
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3 /* pa */
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MOVW $PADDR(L1+L1X(PHYSDRAM)), R4 /* address of PTE for PHYSDRAM */
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MOVW $16, R5
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_ptdbl:
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FILLPTE()
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SUB.S $1, R5
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BNE _ptdbl
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/*
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* back up and fill in PTEs for memory at KZERO
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* there is 1 bank of 512MB of SDRAM at PHYSDRAM
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*/
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $PHYSDRAM, R3
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MOVW $PADDR(L1+L1X(KZERO)), R4 /* start with PTE for KZERO */
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MOVW $512, R5 /* inner loop count */
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_ptekrw: /* set PTEs for 512MiB */
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FILLPTE()
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SUB.S $1, R5
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BNE _ptekrw
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/*
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* back up and fill in PTE for MMIO
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*/
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MOVW $PTEIO, R2 /* PTE bits */
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MOVW $PHYSIO, R3
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MOVW $PADDR(L1+L1X(VIRTIO)), R4 /* start with PTE for VIRTIO */
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FILLPTE()
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/* mmu.c sets up the vectors later */
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/*
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* set up a temporary stack; avoid data & bss segments
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*/
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MOVW $(PHYSDRAM | (128*1024*1024)), R13
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WAVE('P')
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/* set the domain access control */
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MOVW $Client, R0
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BL dacput(SB)
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/* set the translation table base */
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MOVW $PADDR(L1), R0
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BL ttbput(SB)
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MOVW $0, R0
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BL pidput(SB) /* paranoia */
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/* the little dance to turn the MMU & caches on */
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WAVE('l')
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BL cacheuwbinv(SB)
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BL mmuinvalidate(SB)
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BL mmuenable(SB)
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WAVE('a')
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/* warp the PC into the virtual map */
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MOVW $KZERO, R0
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BL _r15warp(SB)
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/*
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* now running at KZERO+something!
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*/
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MOVW $setR12(SB), R12 /* reload the SB */
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/*
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* set up temporary stack again, in case we've just switched
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* to a new register set.
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*/
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MOVW $(KZERO|(128*1024*1024)), R13
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/* can now execute arbitrary C code */
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BL cacheuwbinv(SB)
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WAVE('n')
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/* undo double map of 0, KZERO */
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MOVW $PADDR(L1+L1X(0)), R4 /* address of PTE for 0 */
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MOVW $0, R0
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MOVW $16, R5
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_ptudbl:
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MOVW R0, (R4)
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ADD $4, R4 /* bump PTE address */
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ADD $MiB, R0 /* bump pa */
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SUB.S $1, R5
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BNE _ptudbl
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BARRIERS
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvd), CpTLBinvse
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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WAVE(' ')
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/* pass Mach to main and set up the stack */
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MOVW $(MACHADDR), R0 /* Mach */
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MOVW R0, R13
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ADD $(MACHSIZE), R13 /* stack pointer */
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SUB $4, R13 /* space for link register */
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BL main(SB) /* void main(Mach*) */
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/* fall through */
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/* not used */
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TEXT _reset(SB), 1, $-4
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/* turn the caches off */
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R0
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MOVW R0, CPSR
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BARRIERS
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BL cacheuwbinv(SB)
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCwb|CpCicache|CpCdcache|CpCalign), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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WAVE('R')
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/* redo double map of 0, KZERO */
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MOVW $(L1+L1X(0)), R4 /* address of PTE for 0 */
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MOVW $PTEDRAM, R2 /* PTE bits */
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MOVW $0, R3
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MOVW $16, R5
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_ptrdbl:
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ORR R3, R2, R1 /* first identity-map 0 to 0, etc. */
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MOVW R1, (R4)
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ADD $4, R4 /* bump PTE address */
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ADD $MiB, R3 /* bump pa */
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SUB.S $1, R5
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BNE _ptrdbl
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BARRIERS
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WAVE('e')
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvd), CpTLBinv
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* back to 29- or 26-bit addressing, mainly for SB */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCd32|CpCi32), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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/* turn the MMU off */
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MOVW $PHYSDRAM, R0
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BL _r15warp(SB)
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BL mmuinvalidate(SB)
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BL mmudisable(SB)
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WAVE('s')
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/* set new reset vector */
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MOVW $0, R2
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MOVW $0xe59ff018, R3 /* MOVW 0x18(R15), R15 */
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MOVW R3, (R2)
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WAVE('e')
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MOVW $PHYSBOOTROM, R3
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MOVW R3, 0x20(R2) /* where $0xe59ff018 jumps to */
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BARRIERS
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WAVE('t')
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WAVE('\r')
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WAVE('\n')
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/* ...and jump to it */
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MOVW R2, R15 /* software reboot */
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_limbo: /* should not get here... */
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B _limbo /* ... and can't get out */
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BL _div(SB) /* hack to load _div, etc. */
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TEXT _r15warp(SB), 1, $-4
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BIC $KSEGM, R14
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ORR R0, R14
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BIC $KSEGM, R13
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ORR R0, R13
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RET
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/* clobbers R1, R6 */
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TEXT myputc(SB), 1, $-4
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MOVW $PHYSCONS, R6
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_busy:
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MOVW 20(R6), R1
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BIC.S $~(1<<5), R1 /* (x->lsr & LSRthre) == 0? */
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BEQ _busy
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MOVW R3, (R6) /* print */
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ISB
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RET
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/*
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* l1 caches
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*/
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TEXT l1cacheson(SB), 1, $-4
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MOVW CPSR, R5
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ORR $(PsrDirq|PsrDfiq), R5, R4
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MOVW R4, CPSR /* splhi */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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ORR $(CpCdcache|CpCicache|CpCwb), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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MOVW R5, CPSR /* splx */
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RET
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TEXT l1cachesoff(SB), 1, $-4
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MOVM.DB.W [R14], (SP) /* save lr on stack */
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MOVW CPSR, R5
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ORR $(PsrDirq|PsrDfiq), R5, R4
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MOVW R4, CPSR /* splhi */
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BL cacheuwbinv(SB)
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpCdcache|CpCicache|CpCwb), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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MOVW R5, CPSR /* splx */
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MOVM.IA.W (SP), [R14] /* restore lr */
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RET
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/*
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* cache* functions affect only the L1 caches, which are VIVT.
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*/
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TEXT cachedwb(SB), 1, $-4 /* D writeback */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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BARRIERS /* force outstanding stores to cache */
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/* keep writing back dirty cache lines until no more exist */
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_dwb:
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwb), CpCACHEtest
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BNE _dwb
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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TEXT cachedwbse(SB), 1, $-4 /* D writeback SE */
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MOVW R0, R2 /* first arg: address */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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BARRIERS /* force outstanding stores to cache */
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MOVW 4(FP), R1 /* second arg: size */
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// CMP.S $(4*1024), R1
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// BGT _dwb
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ADD R2, R1
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BIC $(CACHELINESZ-1), R2
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_dwbse:
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MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEwb), CpCACHEse
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ADD $CACHELINESZ, R2
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CMP.S R2, R1
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BGT _dwbse
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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TEXT cachedwbinv(SB), 1, $-4 /* D writeback+invalidate */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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BARRIERS /* force outstanding stores to cache */
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/* keep writing back dirty cache lines until no more exist */
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_dwbinv:
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _dwbinv
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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TEXT cachedwbinvse(SB), 1, $-4 /* D writeback+invalidate SE */
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MOVW R0, R2 /* first arg: address */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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BARRIERS /* force outstanding stores to cache */
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MOVW 4(FP), R1 /* second arg: size */
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DSB
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// CMP.S $(4*1024), R1
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// BGT _dwbinv
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ADD R2, R1
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BIC $(CACHELINESZ-1), R2
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_dwbinvse:
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MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEwbi), CpCACHEse
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ADD $CACHELINESZ, R2
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CMP.S R2, R1
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BGT _dwbinvse
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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TEXT cachedinvse(SB), 1, $-4 /* D invalidate SE */
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MOVW R0, R2 /* first arg: address */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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MOVW 4(FP), R1 /* second arg: size */
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DSB
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// CMP.S $(4*1024), R1
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// BGT _dinv
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ADD R2, R1
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BIC $(CACHELINESZ-1), R2
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_dinvse:
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MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEinvd), CpCACHEse
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ADD $CACHELINESZ, R2
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CMP.S R2, R1
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BGT _dinvse
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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TEXT cacheuwbinv(SB), 1, $-4 /* D+I writeback+invalidate */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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BARRIERS /* force outstanding stores to cache */
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/* keep writing back dirty cache lines until no more exist */
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_uwbinv: /* D writeback+invalidate */
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MRC CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
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BNE _uwbinv
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW $0, R0 /* I invalidate */
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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MOVW R3, CPSR /* splx */
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RET
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TEXT cacheiinv(SB), 1, $-4 /* I invalidate */
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BARRIERS
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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RET
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TEXT cachedinv(SB), 1, $-4 /* D invalidate */
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_dinv:
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BARRIERS
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEall
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/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
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BARRIERS
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RET
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/*
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* l2 cache
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*
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* these functions assume that the necessary l1 cache operations have been
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* or will be done explicitly by the caller.
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*/
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/* enable l2 cache in config coproc. reg. do this while l1 caches are off. */
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TEXT l2cachecfgon(SB), 1, $-4
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BARRIERS
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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BARRIERS
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MRC CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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ORR $(CpTCl2ena | CpTCl2prefdis), R1 /* l2 on, prefetch off */
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MCR CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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BARRIERS
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RET
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/* disable l2 cache in config coproc. reg. do this while l1 caches are off. */
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TEXT l2cachecfgoff(SB), 1, $-4
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BARRIERS
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MRC CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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BIC $CpTCl2ena, R1
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MCR CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
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BARRIERS
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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BARRIERS
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RET
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TEXT l2cacheuwb(SB), 1, $-4 /* L2 unified writeback */
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
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ISB
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RET
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TEXT l2cacheuwbse(SB), 1, $-4 /* L2 unified writeback SE */
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MOVW R0, R2 /* first arg: address */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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MOVW 4(FP), R1 /* second arg: size */
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ADD R2, R1
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BIC $(CACHELINESZ-1), R2
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_l2wbse:
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MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
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ADD $CACHELINESZ, R2
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CMP.S R2, R1
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BGT _l2wbse
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ISB
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MOVW R3, CPSR /* splx */
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RET
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TEXT l2cacheuwbinv(SB), 1, $-4 /* L2 unified writeback+invalidate */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
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ISB
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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ISB
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MOVW R3, CPSR /* splx */
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RET
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TEXT l2cacheuwbinvse(SB), 1, $-4 /* L2 unified writeback+invalidate SE */
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MOVW R0, R2 /* first arg: address */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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MOVW 4(FP), R1 /* second arg: size */
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ADD R2, R1
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BIC $(CACHELINESZ-1), R2
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_l2wbinvse:
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MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
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ISB
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MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
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ADD $CACHELINESZ, R2
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CMP.S R2, R1
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BGT _l2wbinvse
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ISB
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MOVW R3, CPSR /* splx */
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RET
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TEXT l2cacheuinv(SB), 1, $-4 /* L2 unified invalidate */
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MCR CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
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ISB
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RET
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TEXT l2cacheuinvse(SB), 1, $-4 /* L2 unified invalidate SE */
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MOVW R0, R2 /* first arg: address */
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MOVW CPSR, R3 /* splhi */
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ORR $(PsrDirq), R3, R1
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MOVW R1, CPSR
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MOVW 4(FP), R1 /* second arg: size */
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ADD R2, R1
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BIC $(CACHELINESZ-1), R2
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_l2invse:
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MCR CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
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ADD $CACHELINESZ, R2
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CMP.S R2, R1
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BGT _l2invse
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ISB
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MOVW R3, CPSR /* splx */
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RET
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/*
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* enable mmu, i and d caches, and high vector
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*/
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TEXT mmuenable(SB), 1, $-4
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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ORR $(CpChv|CpCmmu|CpCdcache|CpCicache|CpCwb|CpCsystem), R0
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BIC $(CpCrom), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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RET
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TEXT mmudisable(SB), 1, $-4
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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BIC $(CpChv|CpCmmu|CpCdcache|CpCicache|CpCwb), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0)
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BARRIERS
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RET
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TEXT mmuinvalidate(SB), 1, $-4 /* invalidate all */
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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RET
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TEXT mmuinvalidateaddr(SB), 1, $-4 /* invalidate single entry */
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinvse
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BARRIERS
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RET
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TEXT cpidget(SB), 1, $-4 /* main ID */
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MRC CpSC, 0, R0, C(CpID), C(0), CpIDid
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RET
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TEXT cpctget(SB), 1, $-4 /* cache type */
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MRC CpSC, 0, R0, C(CpID), C(0), CpIDct
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RET
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|
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TEXT controlget(SB), 1, $-4 /* control */
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MRC CpSC, 0, R0, C(CpCONTROL), C(0)
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RET
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|
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TEXT ttbget(SB), 1, $-4 /* translation table base */
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MRC CpSC, 0, R0, C(CpTTB), C(0)
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RET
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|
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TEXT ttbput(SB), 1, $-4 /* translation table base */
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MCR CpSC, 0, R0, C(CpTTB), C(0)
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ISB
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RET
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|
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TEXT dacget(SB), 1, $-4 /* domain access control */
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MRC CpSC, 0, R0, C(CpDAC), C(0)
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RET
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|
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TEXT dacput(SB), 1, $-4 /* domain access control */
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MCR CpSC, 0, R0, C(CpDAC), C(0)
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ISB
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RET
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|
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TEXT fsrget(SB), 1, $-4 /* fault status */
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MRC CpSC, 0, R0, C(CpFSR), C(0)
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RET
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|
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TEXT farget(SB), 1, $-4 /* fault address */
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MRC CpSC, 0, R0, C(CpFAR), C(0x0)
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RET
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|
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TEXT pidget(SB), 1, $-4 /* address translation pid */
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MRC CpSC, 0, R0, C(CpPID), C(0x0)
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RET
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|
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TEXT pidput(SB), 1, $-4 /* address translation pid */
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MCR CpSC, 0, R0, C(CpPID), C(0x0)
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ISB
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RET
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TEXT splhi(SB), 1, $-4
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MOVW $(MACHADDR+4), R2 /* save caller pc in Mach */
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MOVW R14, 0(R2)
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|
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MOVW CPSR, R0 /* turn off interrupts */
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ORR $(PsrDirq), R0, R1
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MOVW R1, CPSR
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RET
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|
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|
TEXT spllo(SB), 1, $-4
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|
MOVW CPSR, R0
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|
BIC $(PsrDirq), R0, R1
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|
MOVW R1, CPSR
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|
RET
|
|
|
|
TEXT splx(SB), 1, $-4
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|
MOVW $(MACHADDR+0x04), R2 /* save caller pc in Mach */
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|
MOVW R14, 0(R2)
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|
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|
MOVW R0, R1 /* reset interrupt level */
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|
MOVW CPSR, R0
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|
MOVW R1, CPSR
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|
RET
|
|
|
|
TEXT splxpc(SB), 1, $-4 /* for iunlock */
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|
MOVW R0, R1
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|
MOVW CPSR, R0
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|
MOVW R1, CPSR
|
|
RET
|
|
|
|
TEXT spldone(SB), 1, $0
|
|
RET
|
|
|
|
TEXT islo(SB), 1, $-4
|
|
MOVW CPSR, R0
|
|
AND $(PsrDirq), R0
|
|
EOR $(PsrDirq), R0
|
|
RET
|
|
|
|
TEXT splfhi(SB), $-4
|
|
MOVW CPSR, R0
|
|
ORR $(PsrDfiq|PsrDirq), R0, R1
|
|
MOVW R1, CPSR
|
|
RET
|
|
|
|
//TEXT splflo(SB), $-4
|
|
// MOVW CPSR, R0
|
|
// BIC $(PsrDfiq), R0, R1
|
|
// MOVW R1, CPSR
|
|
// RET
|
|
|
|
TEXT tas(SB), $-4
|
|
TEXT _tas(SB), $-4
|
|
MOVW R0,R1
|
|
MOVW $1,R0
|
|
SWPW R0,(R1) /* fix: deprecated in armv7 */
|
|
RET
|
|
|
|
//TEXT tas32(SB), 1, $-4
|
|
// MOVW R0, R1
|
|
// MOVW $0xDEADDEAD, R0
|
|
// MOVW R0, R3
|
|
// SWPW R0, (R1)
|
|
// CMP.S R0, R3
|
|
// BEQ _tasout
|
|
// EOR R3, R3 /* R3 = 0 */
|
|
// CMP.S R0, R3
|
|
// BEQ _tasout
|
|
// MOVW $1, R15 /* abort: lock != 0 && lock != $0xDEADDEAD */
|
|
//_tasout:
|
|
// RET
|
|
|
|
TEXT clz(SB), 1, $-4
|
|
CLZ(0, 0) /* 0 is R0 */
|
|
RET
|
|
|
|
TEXT setlabel(SB), 1, $-4
|
|
MOVW R13, 0(R0) /* sp */
|
|
MOVW R14, 4(R0) /* pc */
|
|
BARRIERS
|
|
MOVW $0, R0
|
|
RET
|
|
|
|
TEXT gotolabel(SB), 1, $-4
|
|
MOVW 0(R0), R13 /* sp */
|
|
MOVW 4(R0), R14 /* pc */
|
|
BARRIERS
|
|
MOVW $1, R0
|
|
RET
|
|
|
|
TEXT getcallerpc(SB), 1, $-4
|
|
MOVW 0(R13), R0
|
|
RET
|
|
|
|
TEXT _idlehands(SB), 1, $-4
|
|
MOVW CPSR, R3
|
|
// ORR $PsrDirq, R3, R1 /* splhi */
|
|
BIC $PsrDirq, R3, R1 /* spllo */
|
|
MOVW R1, CPSR
|
|
|
|
MOVW $0, R0 /* wait for interrupt */
|
|
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
|
|
ISB
|
|
|
|
MOVW R3, CPSR /* splx */
|
|
RET
|
|
|
|
TEXT barriers(SB), 1, $-4
|
|
BARRIERS
|
|
RET
|