24057fd4f4
introducing the PFPU structue which allows the machine specific code some flexibility on how to handle the FPU process state. for example, in the pc and pc64 kernel, the FPsave structure is arround 512 bytes. with avx512, it could grow up to 2K. instead of embedding that into the Proc strucutre, it is more effective to allocate it on first use of the fpu, as most processes do not use simd or floating point in the first place. also, the FPsave structure has special 16 byte alignment constraint, which further favours dynamic allocation. this gets rid of the memmoves in pc/pc64 kernels for the aligment. there is also devproc, which is now checking if the fpsave area is actually valid before reading it, avoiding debuggers to see garbage data. the Notsave structure is gone now, as it was not used on any machine.
473 lines
8.9 KiB
C
473 lines
8.9 KiB
C
/*
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* Time.
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*
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* HZ should divide 1000 evenly, ideally.
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* 100, 125, 200, 250 and 333 are okay.
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*/
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#define HZ 100 /* clock frequency */
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#define MS2HZ (1000/HZ) /* millisec per clock tick */
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#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
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enum {
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Mhz = 1000 * 1000,
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Dogsectimeout = 4, /* must be ≤ 34 s. to fit in a ulong */
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};
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/*
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* More accurate time
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*/
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#define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000))
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#define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000))
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#define CONSOLE 0
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typedef struct Conf Conf;
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typedef struct Confmem Confmem;
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typedef struct FPsave FPsave;
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typedef struct PFPU PFPU;
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typedef struct ISAConf ISAConf;
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typedef struct Isolated Isolated;
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typedef struct Label Label;
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typedef struct Lock Lock;
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typedef struct Lowmemcache Lowmemcache;
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typedef struct Memcache Memcache;
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typedef struct MMMU MMMU;
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typedef struct Mach Mach;
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typedef u32int Mreg; /* Msr - bloody UART */
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typedef struct Page Page;
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typedef struct Pcisiz Pcisiz;
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typedef struct Pcidev Pcidev;
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typedef struct PhysUart PhysUart;
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typedef struct PMMU PMMU;
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typedef struct Proc Proc;
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typedef u32int PTE;
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typedef struct Soc Soc;
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typedef struct Uart Uart;
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typedef struct Ureg Ureg;
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typedef uvlong Tval;
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#pragma incomplete Pcidev
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#pragma incomplete Ureg
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#define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */
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/*
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* parameters for sysproc.c
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*/
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#define AOUT_MAGIC (E_MAGIC)
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struct Lock
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{
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ulong key;
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u32int sr;
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uintptr pc;
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Proc* p;
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Mach* m;
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int isilock;
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};
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struct Label
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{
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uintptr sp;
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uintptr pc;
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};
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/*
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* emulated or vfp3 floating point
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*/
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enum {
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Maxfpregs = 32, /* could be 16 or 32, see Mach.fpnregs */
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Nfpctlregs = 16,
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};
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struct FPsave
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{
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ulong status;
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ulong control;
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/*
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* vfp3 with ieee fp regs; uvlong is sufficient for hardware but
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* each must be able to hold an Internal from fpi.h for sw emulation.
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*/
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ulong regs[Maxfpregs][3];
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int fpstate;
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uintptr pc; /* of failed fp instr. */
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};
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struct PFPU
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{
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int fpstate;
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FPsave fpsave[1];
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};
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enum
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{
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FPinit,
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FPactive,
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FPinactive,
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FPemu,
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/* bit or'd with the state */
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FPillegal= 0x100,
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};
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struct Confmem
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{
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uintptr base;
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usize npage;
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uintptr limit;
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uintptr kbase;
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uintptr klimit;
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};
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struct Conf
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{
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ulong nmach; /* processors */
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ulong nproc; /* processes */
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Confmem mem[1]; /* physical memory */
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ulong npage; /* total physical pages of memory */
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usize upages; /* user page pool */
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ulong copymode; /* 0 is copy on write, 1 is copy on reference */
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ulong ialloc; /* max interrupt time allocation in bytes */
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ulong pipeqsize; /* size in bytes of pipe queues */
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ulong nimage; /* number of page cache image headers */
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ulong nswap; /* number of swap pages */
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int nswppo; /* max # of pageouts per segment pass */
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ulong hz; /* processor cycle freq */
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ulong mhz;
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int monitor; /* flag */
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};
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/*
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* MMU stuff in Mach.
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*/
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struct MMMU
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{
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PTE* mmul1; /* l1 for this processor */
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int mmul1lo;
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int mmul1hi;
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int mmupid;
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};
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/*
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* MMU stuff in proc
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*/
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#define NCOLOR 1 /* 1 level cache, don't worry about VCE's */
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struct PMMU
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{
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Page* mmul2;
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Page* mmul2cache; /* free mmu pages */
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};
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#include "../port/portdat.h"
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struct Mach
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{
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/* offsets known to asm */
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int machno; /* physical id of processor */
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uintptr splpc; /* pc of last caller to splhi */
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Proc* proc; /* current process */
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MMMU;
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/* end of offsets known to asm */
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int flushmmu; /* flush current proc mmu state */
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ulong ticks; /* of the clock since boot time */
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Label sched; /* scheduler wakeup */
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Lock alarmlock; /* access to alarm list */
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void* alarm; /* alarms bound to this clock */
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int inclockintr;
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Proc* readied; /* for runproc */
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ulong schedticks; /* next forced context switch */
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int cputype;
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ulong delayloop;
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/* stats */
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int tlbfault;
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int tlbpurge;
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int pfault;
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int cs;
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int syscall;
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int load;
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int intr;
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uvlong fastclock; /* last sampled value */
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uvlong inidle; /* time spent in idlehands() */
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ulong spuriousintr;
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int lastintr;
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int ilockdepth;
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Perf perf; /* performance counters */
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int probing; /* probeaddr() state */
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int trapped;
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Lock probelock;
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int inidlehands;
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int cpumhz;
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uvlong cpuhz; /* speed of cpu */
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uvlong cyclefreq; /* Frequency of user readable cycle counter */
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/* vfp3 fpu */
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int havefp;
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int havefpvalid;
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int fpon;
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int fpconfiged;
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int fpnregs;
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ulong fpscr; /* sw copy */
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int fppid; /* pid of last fault */
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uintptr fppc; /* addr of last fault */
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int fpcnt; /* how many consecutive at that addr */
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/* save areas for exceptions, hold R0-R4 */
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u32int sfiq[5];
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u32int sirq[5];
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u32int sund[5];
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u32int sabt[5];
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u32int smon[5]; /* probably not needed */
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u32int ssys[5];
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int stack[1];
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};
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/*
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* Fake kmap.
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*/
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typedef void KMap;
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#define VA(k) ((uintptr)(k))
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#define kmap(p) (KMap*)((p)->pa|kseg0)
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#define kunmap(k)
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struct
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{
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Lock;
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char machs[MAXMACH]; /* active CPUs */
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int wfi; /* bitmap of CPUs in WFI state */
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int stopped; /* bitmap of CPUs stopped */
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int exiting; /* shutdown */
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}active;
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extern register Mach* m; /* R10 */
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extern register Proc* up; /* R9 */
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/* an object guaranteed to be in its own cache line */
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typedef uchar Cacheline[CACHELINESZ];
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struct Isolated {
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Cacheline c0;
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ulong word;
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Cacheline c1;
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};
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extern Memcache cachel[]; /* arm arch v7 supports 1-7 */
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extern ulong intrcount[MAXMACH];
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extern int irqtooearly;
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extern uintptr kseg0;
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extern Isolated l1ptstable;
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extern uchar *l2pages;
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extern Mach* machaddr[MAXMACH];
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extern ulong memsize;
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extern int navailcpus;
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extern int normalprint;
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/*
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* a parsed plan9.ini line
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*/
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#define NISAOPT 8
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struct ISAConf {
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char *type;
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ulong port;
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int irq;
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ulong dma;
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ulong mem;
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ulong size;
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ulong freq;
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int nopt;
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char *opt[NISAOPT];
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};
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#define MACHP(n) machaddr[n]
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/*
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* Horrid. But the alternative is 'defined'.
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*/
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#ifdef _DBGC_
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#define DBGFLG (dbgflg[_DBGC_])
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#else
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#define DBGFLG (0)
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#endif /* _DBGC_ */
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int vflag;
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extern char dbgflg[256];
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#define dbgprint print /* for now */
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/*
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* hardware info about a device
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*/
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typedef struct {
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ulong port;
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int size;
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} Devport;
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struct DevConf
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{
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ulong intnum; /* interrupt number */
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char *type; /* card type, malloced */
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int nports; /* Number of ports */
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Devport *ports; /* The ports themselves */
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};
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/* characteristics of a given arm cache level */
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struct Memcache {
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uint waysh; /* shifts for set/way register */
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uint setsh;
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uint log2linelen;
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uint level; /* 1 is nearest processor, 2 further away */
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uint type;
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uint external; /* flag */
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uint l1ip; /* l1 I policy */
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uint nways; /* associativity */
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uint nsets;
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uint linelen; /* bytes per cache line */
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uint setsways;
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};
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enum Cachetype {
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Nocache,
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Ionly,
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Donly,
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Splitid,
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Unified,
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};
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enum {
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Intcache,
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Extcache,
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};
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/*
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* characteristics of cache level, kept at low, fixed address (CACHECONF).
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* all offsets are known to cache.v7.s.
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*/
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struct Lowmemcache {
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uint l1waysh; /* shifts for set/way register */
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uint l1setsh;
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uint l2waysh;
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uint l2setsh;
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};
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/*
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* cache capabilities. write-back vs write-through is controlled
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* by the Buffered bit in PTEs.
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*
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* see cache.v7.s and Memcache in dat.h
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*/
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enum {
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Cawt = 1 << 31,
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Cawb = 1 << 30,
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Cara = 1 << 29,
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Cawa = 1 << 28,
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};
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/* non-architectural L2 cache */
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typedef struct Cacheimpl Cacheimpl;
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struct Cacheimpl {
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void (*info)(Memcache *);
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void (*on)(void);
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void (*off)(void);
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void (*inv)(void);
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void (*wb)(void);
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void (*wbinv)(void);
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void (*invse)(void *, int);
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void (*wbse)(void *, int);
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void (*wbinvse)(void *, int);
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};
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/* extern */ Cacheimpl *l2cache, *allcache, *nocache, *l1cache;
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enum Dmamode {
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Const,
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Postincr,
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Index,
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Index2,
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};
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/* pmu = power management unit */
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enum Irqs {
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/*
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* 1st 32 gic irqs reserved for cpu; private interrupts.
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* 0—15 are software-generated by other cpus;
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* 16—31 are private peripheral intrs.
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*/
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Cpu0irq = 0,
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Cpu1irq,
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/* ... */
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Cpu15irq = 15,
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Glbtmrirq = 27,
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Loctmrirq = 29,
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Wdtmrirq = 30,
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/* shared interrupts */
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Ctlr0base = (1+0)*32, /* primary ctlr */
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Tn0irq = Ctlr0base + 0, /* tegra timers */
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Tn1irq = Ctlr0base + 1,
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Rtcirq = Ctlr0base + 2,
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Ctlr1base = (1+1)*32, /* secondary ctlr */
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Uartirq = Ctlr1base + 4,
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Tn2irq = Ctlr1base + 9, /* tegra timers */
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Tn3irq = Ctlr1base + 10,
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/* +24 is cpu0_pmu_intr, +25 is cpu1_pum_intr */
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Ctlr2base = (1+2)*32, /* ternary ctlr */
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Extpmuirq = Ctlr2base + 22,
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Ctlr3base = (1+3)*32, /* quad ctlr */
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Pcieirq = Ctlr3base + 2,
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};
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struct Soc { /* addr's of SoC controllers */
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uintptr clkrst;
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uintptr power;
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uintptr exceptvec;
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uintptr sema;
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uintptr l2cache;
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uintptr flow;
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/* private memory region */
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uintptr scu;
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uintptr intr; /* `cpu interface' */
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/* private-peripheral-interrupt cortex-a clocks */
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uintptr glbtmr;
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uintptr loctmr;
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uintptr intrdist;
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uintptr uart[5];
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/* shared-peripheral-interrupt tegra2 clocks */
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uintptr rtc; /* real-time clock */
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uintptr tmr[4];
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uintptr µs;
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uintptr pci;
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uintptr ether;
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uintptr ehci;
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uintptr ide;
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uintptr nand;
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uintptr nor;
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uintptr spi[4];
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uintptr twsi;
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uintptr mmc[4];
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uintptr gpio[7];
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} soc;
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extern Soc soc;
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