281 lines
5.4 KiB
C
281 lines
5.4 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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typedef struct DMAport DMAport;
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typedef struct DMA DMA;
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typedef struct DMAxfer DMAxfer;
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/*
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* state of a dma transfer
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*/
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struct DMAxfer
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{
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ulong bpa; /* bounce buffer physical address */
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void* bva; /* bounce buffer virtual address */
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int blen; /* bounce buffer length */
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void* va; /* virtual address destination/src */
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long len; /* bytes to be transferred */
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int flags;
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};
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/*
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* the dma controllers. the first half of this structure specifies
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* the I/O ports used by the DMA controllers.
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*/
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struct DMAport
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{
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uchar addr[4]; /* current address (4 channels) */
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uchar count[4]; /* current count (4 channels) */
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uchar page[4]; /* page registers (4 channels) */
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uchar cmd; /* command status register */
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uchar req; /* request registers */
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uchar sbm; /* single bit mask register */
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uchar mode; /* mode register */
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uchar cbp; /* clear byte pointer */
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uchar mc; /* master clear */
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uchar cmask; /* clear mask register */
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uchar wam; /* write all mask register bit */
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};
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struct DMA
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{
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DMAport;
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int shift;
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Lock;
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DMAxfer x[4];
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};
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DMA dma[2] = {
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{ 0x00, 0x02, 0x04, 0x06,
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0x01, 0x03, 0x05, 0x07,
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0x87, 0x83, 0x81, 0x82,
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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0 },
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{ 0xc0, 0xc4, 0xc8, 0xcc,
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0xc2, 0xc6, 0xca, 0xce,
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0x8f, 0x8b, 0x89, 0x8a,
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0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
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1 },
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};
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extern int i8237dma;
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static void* i8237bva[2];
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static int i8237used;
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/*
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* DMA must be in the first 16MB. This gets called early by the
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* initialisation routines of any devices which require DMA to ensure
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* the allocated bounce buffers are below the 16MB limit.
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*/
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void
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_i8237alloc(void)
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{
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void* bva;
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if(i8237dma <= 0)
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return;
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if(i8237dma > 2)
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i8237dma = 2;
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bva = xspanalloc(64*1024*i8237dma, 0, 64*1024);
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if(bva == nil || PADDR(bva)+64*1024*i8237dma > 16*MB){
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/*
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* This will panic with the current
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* implementation of xspanalloc().
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if(bva != nil)
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xfree(bva);
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*/
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return;
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}
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i8237bva[0] = bva;
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if(i8237dma == 2)
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i8237bva[1] = ((uchar*)i8237bva[0])+64*1024;
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}
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/*
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* DMA must be in the first 16MB. This gets called early by the
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* initialisation routines of any devices which require DMA to ensure
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* the allocated bounce buffers are below the 16MB limit.
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*/
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int
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dmainit(int chan, int maxtransfer)
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{
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DMA *dp;
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DMAxfer *xp;
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static int once;
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if(once == 0){
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if(ioalloc(0x00, 0x10, 0, "dma") < 0
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|| ioalloc(0x80, 0x10, 0, "dma") < 0
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|| ioalloc(0xd0, 0x10, 0, "dma") < 0)
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panic("dmainit");
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once = 1;
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}
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if(maxtransfer > 64*1024)
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maxtransfer = 64*1024;
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dp = &dma[(chan>>2)&1];
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chan = chan & 3;
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xp = &dp->x[chan];
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if(xp->bva != nil){
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if(xp->blen < maxtransfer)
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return 1;
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return 0;
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}
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if(i8237used >= i8237dma || i8237bva[i8237used] == nil){
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print("no i8237 DMA bounce buffer < 16MB\n");
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return 1;
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}
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xp->bva = i8237bva[i8237used++];
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xp->bpa = PADDR(xp->bva);
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xp->blen = maxtransfer;
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xp->len = 0;
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xp->flags = 0;
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return 0;
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}
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void*
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dmabva(int chan)
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{
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DMA *dp;
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DMAxfer *xp;
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dp = &dma[(chan>>2)&1];
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chan = chan & 3;
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xp = &dp->x[chan];
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return xp->bva;
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}
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int
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dmacount(int chan)
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{
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int retval;
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DMA *dp;
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dp = &dma[(chan>>2)&1];
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chan = chan & 3;
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ilock(dp);
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retval = inb(dp->count[chan]);
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retval |= inb(dp->count[chan]) << 8;
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iunlock(dp);
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return ((retval<<dp->shift)+1) & 0xFFFF;
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}
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/*
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* setup a dma transfer. if the destination is not in kernel
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* memory, allocate a page for the transfer.
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*
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* we assume BIOS has set up the command register before we
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* are booted.
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*
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* return the updated transfer length (we can't transfer across 64k
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* boundaries)
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*/
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long
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dmasetup(int chan, void *va, long len, int flags)
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{
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DMA *dp;
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ulong pa;
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uchar mode;
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DMAxfer *xp;
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dp = &dma[(chan>>2)&1];
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chan = chan & 3;
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xp = &dp->x[chan];
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/*
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* if this isn't kernel memory or crossing 64k boundary or above 16 meg
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* use the bounce buffer.
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*/
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if((uintptr)va < KZERO
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|| ((pa=PADDR(va))&0xFFFF0000) != ((pa+len)&0xFFFF0000)
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|| pa >= 16*MB){
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if(xp->bva == nil)
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return -1;
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if(len > xp->blen)
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len = xp->blen;
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if(!(flags & DMAREAD))
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memmove(xp->bva, va, len);
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xp->va = va;
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xp->len = len;
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xp->flags = flags;
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pa = xp->bpa;
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}
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else
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xp->len = 0;
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mode = ((flags & DMAREAD) ? 0x44 : 0x48) | /* read or write */
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((flags & DMALOOP) ? 0x10 : 0) | /* auto init mode */
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chan;
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/*
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* this setup must be atomic
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*/
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ilock(dp);
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outb(dp->mode, mode);
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outb(dp->page[chan], pa>>16);
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outb(dp->cbp, 0); /* set count & address to their first byte */
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outb(dp->addr[chan], pa>>dp->shift); /* set address */
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outb(dp->addr[chan], pa>>(8+dp->shift));
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outb(dp->count[chan], (len>>dp->shift)-1); /* set count */
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outb(dp->count[chan], ((len>>dp->shift)-1)>>8);
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outb(dp->sbm, chan); /* enable the channel */
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iunlock(dp);
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return len;
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}
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int
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dmadone(int chan)
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{
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DMA *dp;
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dp = &dma[(chan>>2)&1];
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chan = chan & 3;
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return inb(dp->cmd) & (1<<chan);
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}
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/*
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* this must be called after a dma has been completed.
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*
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* if a page has been allocated for the dma,
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* copy the data into the actual destination
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* and free the page.
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*/
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void
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dmaend(int chan)
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{
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DMA *dp;
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DMAxfer *xp;
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dp = &dma[(chan>>2)&1];
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chan = chan & 3;
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/*
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* disable the channel
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*/
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ilock(dp);
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outb(dp->sbm, 4|chan);
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iunlock(dp);
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xp = &dp->x[chan];
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if(xp->len == 0 || !(xp->flags & DMAREAD))
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return;
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/*
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* copy out of temporary page
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*/
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memmove(xp->va, xp->bva, xp->len);
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xp->len = 0;
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}
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