1054 lines
20 KiB
C
1054 lines
20 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "../port/error.h"
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#include "io.h"
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/*
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* Intel 82365SL PCIC controller and compatibles.
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*/
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enum
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{
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/*
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* registers indices
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*/
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Rid= 0x0, /* identification and revision */
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Ris= 0x1, /* interface status */
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Rpc= 0x2, /* power control */
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Foutena= (1<<7), /* output enable */
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Fautopower= (1<<5), /* automatic power switching */
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Fcardena= (1<<4), /* PC card enable */
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Rigc= 0x3, /* interrupt and general control */
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Fiocard= (1<<5), /* I/O card (vs memory) */
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Fnotreset= (1<<6), /* reset if not set */
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FSMIena= (1<<4), /* enable change interrupt on SMI */
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Rcsc= 0x4, /* card status change */
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Rcscic= 0x5, /* card status change interrupt config */
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Fchangeena= (1<<3), /* card changed */
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Fbwarnena= (1<<1), /* card battery warning */
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Fbdeadena= (1<<0), /* card battery dead */
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Rwe= 0x6, /* address window enable */
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Fmem16= (1<<5), /* use A23-A12 to decode address */
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Rio= 0x7, /* I/O control */
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Fwidth16= (1<<0), /* 16 bit data width */
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Fiocs16= (1<<1), /* IOCS16 determines data width */
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Fzerows= (1<<2), /* zero wait state */
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Ftiming= (1<<3), /* timing register to use */
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Riobtm0lo= 0x8, /* I/O address 0 start low byte */
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Riobtm0hi= 0x9, /* I/O address 0 start high byte */
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Riotop0lo= 0xa, /* I/O address 0 stop low byte */
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Riotop0hi= 0xb, /* I/O address 0 stop high byte */
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Riobtm1lo= 0xc, /* I/O address 1 start low byte */
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Riobtm1hi= 0xd, /* I/O address 1 start high byte */
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Riotop1lo= 0xe, /* I/O address 1 stop low byte */
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Riotop1hi= 0xf, /* I/O address 1 stop high byte */
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Rmap= 0x10, /* map 0 */
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/*
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* CL-PD67xx extension registers
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*/
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Rmisc1= 0x16, /* misc control 1 */
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F5Vdetect= (1<<0),
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Fvcc3V= (1<<1),
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Fpmint= (1<<2),
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Fpsirq= (1<<3),
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Fspeaker= (1<<4),
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Finpack= (1<<7),
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Rfifo= 0x17, /* fifo control */
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Fflush= (1<<7), /* flush fifo */
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Rmisc2= 0x1E, /* misc control 2 */
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Flowpow= (1<<1), /* low power mode */
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Rchipinfo= 0x1F, /* chip information */
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Ratactl= 0x26, /* ATA control */
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/*
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* offsets into the system memory address maps
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*/
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Mbtmlo= 0x0, /* System mem addr mapping start low byte */
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Mbtmhi= 0x1, /* System mem addr mapping start high byte */
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F16bit= (1<<7), /* 16-bit wide data path */
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Mtoplo= 0x2, /* System mem addr mapping stop low byte */
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Mtophi= 0x3, /* System mem addr mapping stop high byte */
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Ftimer1= (1<<6), /* timer set 1 */
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Mofflo= 0x4, /* Card memory offset address low byte */
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Moffhi= 0x5, /* Card memory offset address high byte */
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Fregactive= (1<<6), /* attribute memory */
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/*
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* configuration registers - they start at an offset in attribute
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* memory found in the CIS.
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*/
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Rconfig= 0,
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Creset= (1<<7), /* reset device */
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Clevel= (1<<6), /* level sensitive interrupt line */
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Cirq= (1<<2), /* IRQ enable */
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Cdecode= (1<<1), /* address decode */
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Cfunc= (1<<0), /* function enable */
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Riobase0= 5,
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Riobase1= 6,
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Riosize= 9,
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};
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#define MAP(x,o) (Rmap + (x)*0x8 + o)
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typedef struct I82365 I82365;
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/* a controller */
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enum
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{
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Ti82365,
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Tpd6710,
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Tpd6720,
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Tvg46x,
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};
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struct I82365
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{
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int type;
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int dev;
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int nslot;
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int xreg; /* index register address */
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int dreg; /* data register address */
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int irq;
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};
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static I82365 *controller[4];
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static int ncontroller;
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static PCMslot *slot;
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static PCMslot *lastslot;
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static nslot;
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static void i82365intr(Ureg*, void*);
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static int pcmio(int, ISAConf*);
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static long pcmread(int, int, void*, long, vlong);
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static long pcmwrite(int, int, void*, long, vlong);
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static void i82365dump(PCMslot*);
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/*
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* reading and writing card registers
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*/
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static uchar
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rdreg(PCMslot *pp, int index)
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{
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outb(((I82365*)pp->cp)->xreg, pp->base + index);
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return inb(((I82365*)pp->cp)->dreg);
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}
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static void
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wrreg(PCMslot *pp, int index, uchar val)
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{
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outb(((I82365*)pp->cp)->xreg, pp->base + index);
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outb(((I82365*)pp->cp)->dreg, val);
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}
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/*
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* get info about card
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*/
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static void
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slotinfo(PCMslot *pp)
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{
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uchar isr;
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isr = rdreg(pp, Ris);
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pp->occupied = (isr & (3<<2)) == (3<<2);
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pp->powered = isr & (1<<6);
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pp->battery = (isr & 3) == 3;
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pp->wrprot = isr & (1<<4);
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pp->busy = isr & (1<<5);
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pp->msec = TK2MS(MACHP(0)->ticks);
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}
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static int
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vcode(int volt)
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{
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switch(volt){
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case 5:
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return 1;
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case 12:
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return 2;
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default:
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return 0;
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}
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}
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/*
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* enable the slot card
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*/
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static void
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slotena(PCMslot *pp)
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{
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if(pp->enabled)
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return;
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/* power up and unreset, wait's are empirical (???) */
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wrreg(pp, Rpc, Fautopower|Foutena|Fcardena);
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delay(300);
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wrreg(pp, Rigc, 0);
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delay(100);
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wrreg(pp, Rigc, Fnotreset);
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delay(500);
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/* get configuration */
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slotinfo(pp);
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if(pp->occupied){
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pcmcisread(pp);
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pp->enabled = 1;
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} else
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wrreg(pp, Rpc, Fautopower);
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}
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/*
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* disable the slot card
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*/
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static void
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slotdis(PCMslot *pp)
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{
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wrreg(pp, Rpc, 0); /* turn off card power */
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wrreg(pp, Rwe, 0); /* no windows */
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pp->enabled = 0;
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}
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/*
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* status change interrupt
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*/
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static void
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i82365intr(Ureg *, void *)
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{
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uchar csc, was;
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PCMslot *pp;
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if(slot == 0)
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return;
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for(pp = slot; pp < lastslot; pp++){
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csc = rdreg(pp, Rcsc);
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was = pp->occupied;
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slotinfo(pp);
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if(csc & (1<<3) && was != pp->occupied){
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if(!pp->occupied)
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slotdis(pp);
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}
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}
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}
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enum
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{
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Mshift= 12,
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Mgran= (1<<Mshift), /* granularity of maps */
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Mmask= ~(Mgran-1), /* mask for address bits important to the chip */
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};
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/*
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* get a map for pc card region, return corrected len
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*/
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PCMmap*
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pcmmap(int slotno, ulong offset, int len, int attr)
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{
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PCMslot *pp;
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uchar we, bit;
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PCMmap *m, *nm;
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int i;
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ulong e;
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pp = slot + slotno;
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lock(&pp->mlock);
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/* convert offset to granularity */
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if(len <= 0)
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len = 1;
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e = ROUND(offset+len, Mgran);
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offset &= Mmask;
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len = e - offset;
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/* look for a map that covers the right area */
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we = rdreg(pp, Rwe);
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bit = 1;
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nm = 0;
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for(m = pp->mmap; m < &pp->mmap[nelem(pp->mmap)]; m++){
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if((we & bit))
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if(m->attr == attr)
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if(offset >= m->ca && e <= m->cea){
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m->ref++;
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unlock(&pp->mlock);
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return m;
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}
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bit <<= 1;
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if(nm == 0 && m->ref == 0)
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nm = m;
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}
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m = nm;
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if(m == 0){
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unlock(&pp->mlock);
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return 0;
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}
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/* if isa space isn't big enough, free it and get more */
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if(m->len < len){
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if(m->isa){
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umbfree(m->isa, m->len);
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m->len = 0;
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}
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m->isa = PADDR(umbmalloc(0, len, Mgran));
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if(m->isa == 0){
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print("pcmmap: out of isa space\n");
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unlock(&pp->mlock);
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return 0;
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}
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m->len = len;
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}
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/* set up new map */
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m->ca = offset;
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m->cea = m->ca + m->len;
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m->attr = attr;
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i = m-pp->mmap;
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bit = 1<<i;
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wrreg(pp, Rwe, we & ~bit); /* disable map before changing it */
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wrreg(pp, MAP(i, Mbtmlo), m->isa>>Mshift);
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wrreg(pp, MAP(i, Mbtmhi), (m->isa>>(Mshift+8)) | F16bit);
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wrreg(pp, MAP(i, Mtoplo), (m->isa+m->len-1)>>Mshift);
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wrreg(pp, MAP(i, Mtophi), ((m->isa+m->len-1)>>(Mshift+8)));
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offset -= m->isa;
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offset &= (1<<25)-1;
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offset >>= Mshift;
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wrreg(pp, MAP(i, Mofflo), offset);
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wrreg(pp, MAP(i, Moffhi), (offset>>8) | (attr ? Fregactive : 0));
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wrreg(pp, Rwe, we | bit); /* enable map */
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m->ref = 1;
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unlock(&pp->mlock);
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return m;
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}
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void
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pcmunmap(int slotno, PCMmap* m)
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{
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PCMslot *pp;
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pp = slot + slotno;
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lock(&pp->mlock);
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m->ref--;
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unlock(&pp->mlock);
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}
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static void
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increfp(PCMslot *pp)
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{
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lock(pp);
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if(pp->ref++ == 0)
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slotena(pp);
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unlock(pp);
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}
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static void
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decrefp(PCMslot *pp)
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{
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lock(pp);
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if(pp->ref-- == 1)
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slotdis(pp);
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unlock(pp);
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}
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/*
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* look for a card whose version contains 'idstr'
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*/
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static int
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pcmcia_pcmspecial(char *idstr, ISAConf *isa)
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{
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PCMslot *pp;
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extern char *strstr(char*, char*);
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int enabled;
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for(pp = slot; pp < lastslot; pp++){
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if(pp->special)
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continue; /* already taken */
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/*
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* make sure we don't power on cards when we already know what's
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* in them. We'll reread every two minutes if necessary
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*/
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enabled = 0;
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if (pp->msec == ~0 || TK2MS(MACHP(0)->ticks) - pp->msec > 120000){
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increfp(pp);
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enabled++;
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}
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if(pp->occupied) {
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if(strstr(pp->verstr, idstr)){
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if (!enabled){
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enabled = 1;
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increfp(pp);
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}
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if(isa == 0 || pcmio(pp->slotno, isa) == 0){
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pp->special = 1;
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return pp->slotno;
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}
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}
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} else
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pp->special = 1;
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if (enabled)
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decrefp(pp);
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}
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return -1;
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}
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static void
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pcmcia_pcmspecialclose(int slotno)
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{
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PCMslot *pp;
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if(slotno >= nslot)
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panic("pcmspecialclose");
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pp = slot + slotno;
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pp->special = 0;
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decrefp(pp);
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}
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enum
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{
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Qdir,
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Qmem,
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Qattr,
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Qctl,
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Nents = 3,
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};
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#define SLOTNO(c) ((ulong)((c->qid.path>>8)&0xff))
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#define TYPE(c) ((ulong)(c->qid.path&0xff))
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#define QID(s,t) (((s)<<8)|(t))
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static int
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pcmgen(Chan *c, char*, Dirtab *, int , int i, Dir *dp)
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{
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int slotno;
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Qid qid;
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long len;
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PCMslot *pp;
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if(i == DEVDOTDOT){
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mkqid(&qid, Qdir, 0, QTDIR);
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devdir(c, qid, "#y", 0, eve, 0555, dp);
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return 1;
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}
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if(i >= Nents*nslot)
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return -1;
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slotno = i/Nents;
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pp = slot + slotno;
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len = 0;
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switch(i%Nents){
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case 0:
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qid.path = QID(slotno, Qmem);
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snprint(up->genbuf, sizeof up->genbuf, "pcm%dmem", slotno);
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len = pp->memlen;
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break;
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case 1:
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qid.path = QID(slotno, Qattr);
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snprint(up->genbuf, sizeof up->genbuf, "pcm%dattr", slotno);
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len = pp->memlen;
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break;
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case 2:
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qid.path = QID(slotno, Qctl);
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snprint(up->genbuf, sizeof up->genbuf, "pcm%dctl", slotno);
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break;
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}
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qid.vers = 0;
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qid.type = QTFILE;
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devdir(c, qid, up->genbuf, len, eve, 0660, dp);
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return 1;
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}
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static char *chipname[] =
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{
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[Ti82365] "Intel 82365SL",
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[Tpd6710] "Cirrus Logic CL-PD6710",
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[Tpd6720] "Cirrus Logic CL-PD6720",
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[Tvg46x] "Vadem VG-46x",
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};
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static I82365*
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i82365probe(int x, int d, int dev)
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{
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uchar c, id;
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I82365 *cp;
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ISAConf isa;
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int i, nslot;
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outb(x, Rid + (dev<<7));
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id = inb(d);
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if((id & 0xf0) != 0x80)
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return 0; /* not a memory & I/O card */
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if((id & 0x0f) == 0x00)
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return 0; /* no revision number, not possible */
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cp = xalloc(sizeof(I82365));
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if(cp == nil){
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print("i82365probe: out of memory\n");
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return 0;
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}
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cp->xreg = x;
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cp->dreg = d;
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cp->dev = dev;
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cp->type = Ti82365;
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cp->nslot = 2;
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switch(id){
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case 0x82:
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case 0x83:
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case 0x84:
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/* could be a cirrus */
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outb(x, Rchipinfo + (dev<<7));
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outb(d, 0);
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c = inb(d);
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if((c & 0xc0) != 0xc0)
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break;
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c = inb(d);
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if((c & 0xc0) != 0x00)
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break;
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if(c & 0x20){
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cp->type = Tpd6720;
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} else {
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cp->type = Tpd6710;
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cp->nslot = 1;
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}
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/* low power mode */
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outb(x, Rmisc2 + (dev<<7));
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c = inb(d);
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outb(d, c & ~Flowpow);
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break;
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}
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/* if it's not a Cirrus, it could be a Vadem... */
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if(cp->type == Ti82365){
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/* unlock the Vadem extended regs */
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outb(x, 0x0E + (dev<<7));
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outb(x, 0x37 + (dev<<7));
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/* make the id register show the Vadem id */
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outb(x, 0x3A + (dev<<7));
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c = inb(d);
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outb(d, c|0xC0);
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outb(x, Rid + (dev<<7));
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c = inb(d);
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if(c & 0x08)
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cp->type = Tvg46x;
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/* go back to Intel compatible id */
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outb(x, 0x3A + (dev<<7));
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c = inb(d);
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outb(d, c & ~0xC0);
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}
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|
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memset(&isa, 0, sizeof(ISAConf));
|
|
if(isaconfig("pcmcia", ncontroller, &isa) && isa.irq)
|
|
cp->irq = isa.irq;
|
|
else
|
|
cp->irq = IrqPCMCIA;
|
|
|
|
for(i = 0; i < isa.nopt; i++){
|
|
if(cistrncmp(isa.opt[i], "nslot=", 6))
|
|
continue;
|
|
nslot = strtol(&isa.opt[i][6], nil, 0);
|
|
if(nslot > 0 && nslot <= 2)
|
|
cp->nslot = nslot;
|
|
}
|
|
|
|
controller[ncontroller++] = cp;
|
|
return cp;
|
|
}
|
|
|
|
static void
|
|
i82365dump(PCMslot *pp)
|
|
{
|
|
int i;
|
|
|
|
for(i = 0; i < 0x40; i++){
|
|
if((i&0x0F) == 0)
|
|
print("\n%2.2uX: ", i);
|
|
print("%2.2uX ", rdreg(pp, i));
|
|
if(((i+1) & 0x0F) == 0x08)
|
|
print(" - ");
|
|
}
|
|
print("\n");
|
|
}
|
|
|
|
/*
|
|
* set up for slot cards
|
|
*/
|
|
void
|
|
devi82365link(void)
|
|
{
|
|
static int already;
|
|
int i, j;
|
|
I82365 *cp;
|
|
PCMslot *pp;
|
|
char buf[32], *p;
|
|
|
|
if(already)
|
|
return;
|
|
already = 1;
|
|
|
|
if((p=getconf("pcmcia0")) && strncmp(p, "disabled", 8)==0)
|
|
return;
|
|
|
|
if(_pcmspecial)
|
|
return;
|
|
|
|
/* look for controllers if the ports aren't already taken */
|
|
if(ioalloc(0x3E0, 2, 0, "i82365.0") >= 0){
|
|
i82365probe(0x3E0, 0x3E1, 0);
|
|
i82365probe(0x3E0, 0x3E1, 1);
|
|
if(ncontroller == 0)
|
|
iofree(0x3E0);
|
|
}
|
|
if(ioalloc(0x3E2, 2, 0, "i82365.1") >= 0){
|
|
i = ncontroller;
|
|
i82365probe(0x3E2, 0x3E3, 0);
|
|
i82365probe(0x3E2, 0x3E3, 1);
|
|
if(ncontroller == i)
|
|
iofree(0x3E2);
|
|
}
|
|
|
|
if(ncontroller == 0)
|
|
return;
|
|
|
|
for(i = 0; i < ncontroller; i++)
|
|
nslot += controller[i]->nslot;
|
|
slot = xalloc(nslot * sizeof(PCMslot));
|
|
if(slot == nil){
|
|
print("i82365link: out of memory\n");
|
|
nslot = 0;
|
|
return;
|
|
}
|
|
|
|
_pcmspecial = pcmcia_pcmspecial;
|
|
_pcmspecialclose = pcmcia_pcmspecialclose;
|
|
|
|
lastslot = slot;
|
|
for(i = 0; i < ncontroller; i++){
|
|
cp = controller[i];
|
|
print("#y%d: %d slot %s: port 0x%uX irq %d\n",
|
|
i, cp->nslot, chipname[cp->type], cp->xreg, cp->irq);
|
|
for(j = 0; j < cp->nslot; j++){
|
|
pp = lastslot++;
|
|
pp->slotno = pp - slot;
|
|
pp->memlen = 64*MB;
|
|
pp->base = (cp->dev<<7) | (j<<6);
|
|
pp->cp = cp;
|
|
pp->msec = ~0;
|
|
pp->verstr[0] = 0;
|
|
slotdis(pp);
|
|
|
|
/* interrupt on status change */
|
|
wrreg(pp, Rcscic, (cp->irq<<4) | Fchangeena);
|
|
rdreg(pp, Rcsc);
|
|
}
|
|
|
|
/* for card management interrupts */
|
|
snprint(buf, sizeof buf, "i82365.%d", i);
|
|
intrenable(cp->irq, i82365intr, 0, BUSUNKNOWN, buf);
|
|
}
|
|
}
|
|
|
|
static Chan*
|
|
i82365attach(char *spec)
|
|
{
|
|
return devattach('y', spec);
|
|
}
|
|
|
|
static Walkqid*
|
|
i82365walk(Chan *c, Chan *nc, char **name, int nname)
|
|
{
|
|
return devwalk(c, nc, name, nname, 0, 0, pcmgen);
|
|
}
|
|
|
|
static int
|
|
i82365stat(Chan *c, uchar *db, int n)
|
|
{
|
|
return devstat(c, db, n, 0, 0, pcmgen);
|
|
}
|
|
|
|
static Chan*
|
|
i82365open(Chan *c, int omode)
|
|
{
|
|
if(c->qid.type & QTDIR){
|
|
if(omode != OREAD)
|
|
error(Eperm);
|
|
} else
|
|
increfp(slot + SLOTNO(c));
|
|
c->mode = openmode(omode);
|
|
c->flag |= COPEN;
|
|
c->offset = 0;
|
|
return c;
|
|
}
|
|
|
|
static void
|
|
i82365close(Chan *c)
|
|
{
|
|
if(c->flag & COPEN)
|
|
if((c->qid.type & QTDIR) == 0)
|
|
decrefp(slot+SLOTNO(c));
|
|
}
|
|
|
|
/* a memmove using only bytes */
|
|
static void
|
|
memmoveb(uchar *to, uchar *from, int n)
|
|
{
|
|
while(n-- > 0)
|
|
*to++ = *from++;
|
|
}
|
|
|
|
/* a memmove using only shorts & bytes */
|
|
static void
|
|
memmoves(uchar *to, uchar *from, int n)
|
|
{
|
|
ushort *t, *f;
|
|
|
|
if((((ulong)to) & 1) || (((ulong)from) & 1) || (n & 1)){
|
|
while(n-- > 0)
|
|
*to++ = *from++;
|
|
} else {
|
|
n = n/2;
|
|
t = (ushort*)to;
|
|
f = (ushort*)from;
|
|
while(n-- > 0)
|
|
*t++ = *f++;
|
|
}
|
|
}
|
|
|
|
static long
|
|
pcmread(int slotno, int attr, void *a, long n, vlong off)
|
|
{
|
|
int i, len;
|
|
PCMmap *m;
|
|
uchar *ac;
|
|
PCMslot *pp;
|
|
ulong offset = off;
|
|
|
|
pp = slot + slotno;
|
|
if(pp->memlen < offset)
|
|
return 0;
|
|
if(pp->memlen < offset + n)
|
|
n = pp->memlen - offset;
|
|
|
|
m = 0;
|
|
if(waserror()){
|
|
if(m)
|
|
pcmunmap(pp->slotno, m);
|
|
nexterror();
|
|
}
|
|
|
|
ac = a;
|
|
for(len = n; len > 0; len -= i){
|
|
m = pcmmap(pp->slotno, offset, 0, attr);
|
|
if(m == 0)
|
|
error("cannot map PCMCIA card");
|
|
if(offset + len > m->cea)
|
|
i = m->cea - offset;
|
|
else
|
|
i = len;
|
|
memmoveb(ac, KADDR(m->isa + offset - m->ca), i);
|
|
pcmunmap(pp->slotno, m);
|
|
offset += i;
|
|
ac += i;
|
|
}
|
|
|
|
poperror();
|
|
return n;
|
|
}
|
|
|
|
static long
|
|
i82365read(Chan *c, void *a, long n, vlong off)
|
|
{
|
|
char *p, *buf, *e;
|
|
PCMslot *pp;
|
|
ulong offset = off;
|
|
|
|
switch(TYPE(c)){
|
|
case Qdir:
|
|
return devdirread(c, a, n, 0, 0, pcmgen);
|
|
case Qmem:
|
|
case Qattr:
|
|
return pcmread(SLOTNO(c), TYPE(c) == Qattr, a, n, off);
|
|
case Qctl:
|
|
buf = p = smalloc(READSTR);
|
|
e = p + READSTR;
|
|
pp = slot + SLOTNO(c);
|
|
|
|
buf[0] = 0;
|
|
if(pp->occupied){
|
|
p = seprint(p, e, "occupied\n");
|
|
if(pp->verstr[0])
|
|
p = seprint(p, e, "version %s\n", pp->verstr);
|
|
}
|
|
if(pp->enabled)
|
|
p = seprint(p, e, "enabled\n");
|
|
if(pp->powered)
|
|
p = seprint(p, e, "powered\n");
|
|
if(pp->configed)
|
|
p = seprint(p, e, "configed\n");
|
|
if(pp->wrprot)
|
|
p = seprint(p, e, "write protected\n");
|
|
if(pp->busy)
|
|
p = seprint(p, e, "busy\n");
|
|
seprint(p, e, "battery lvl %d\n", pp->battery);
|
|
|
|
n = readstr(offset, a, n, buf);
|
|
free(buf);
|
|
|
|
return n;
|
|
}
|
|
error(Ebadarg);
|
|
return -1; /* not reached */
|
|
}
|
|
|
|
static long
|
|
pcmwrite(int dev, int attr, void *a, long n, vlong off)
|
|
{
|
|
int i, len;
|
|
PCMmap *m;
|
|
uchar *ac;
|
|
PCMslot *pp;
|
|
ulong offset = off;
|
|
|
|
pp = slot + dev;
|
|
if(pp->memlen < offset)
|
|
return 0;
|
|
if(pp->memlen < offset + n)
|
|
n = pp->memlen - offset;
|
|
|
|
m = 0;
|
|
if(waserror()){
|
|
if(m)
|
|
pcmunmap(pp->slotno, m);
|
|
nexterror();
|
|
}
|
|
|
|
ac = a;
|
|
for(len = n; len > 0; len -= i){
|
|
m = pcmmap(pp->slotno, offset, 0, attr);
|
|
if(m == 0)
|
|
error("cannot map PCMCIA card");
|
|
if(offset + len > m->cea)
|
|
i = m->cea - offset;
|
|
else
|
|
i = len;
|
|
memmoveb(KADDR(m->isa + offset - m->ca), ac, i);
|
|
pcmunmap(pp->slotno, m);
|
|
offset += i;
|
|
ac += i;
|
|
}
|
|
|
|
poperror();
|
|
return n;
|
|
}
|
|
|
|
static long
|
|
i82365write(Chan *c, void *a, long n, vlong off)
|
|
{
|
|
PCMslot *pp;
|
|
char buf[32];
|
|
|
|
switch(TYPE(c)){
|
|
case Qctl:
|
|
if(n >= sizeof(buf))
|
|
n = sizeof(buf) - 1;
|
|
strncpy(buf, a, n);
|
|
buf[n] = 0;
|
|
pp = slot + SLOTNO(c);
|
|
if(!pp->occupied)
|
|
error(Eio);
|
|
|
|
/* set vpp on card */
|
|
if(strncmp(buf, "vpp", 3) == 0)
|
|
wrreg(pp, Rpc, vcode(strtol(buf+3, 0, 0))|Fautopower|Foutena|Fcardena);
|
|
return n;
|
|
case Qmem:
|
|
case Qattr:
|
|
pp = slot + SLOTNO(c);
|
|
if(pp->occupied == 0 || pp->enabled == 0)
|
|
error(Eio);
|
|
n = pcmwrite(pp->slotno, TYPE(c) == Qattr, a, n, off);
|
|
if(n < 0)
|
|
error(Eio);
|
|
return n;
|
|
}
|
|
error(Ebadarg);
|
|
return -1; /* not reached */
|
|
}
|
|
|
|
Dev i82365devtab = {
|
|
'y',
|
|
"i82365",
|
|
|
|
devreset,
|
|
devinit,
|
|
devshutdown,
|
|
i82365attach,
|
|
i82365walk,
|
|
i82365stat,
|
|
i82365open,
|
|
devcreate,
|
|
i82365close,
|
|
i82365read,
|
|
devbread,
|
|
i82365write,
|
|
devbwrite,
|
|
devremove,
|
|
devwstat,
|
|
};
|
|
|
|
/*
|
|
* configure the PCMslot for IO. We assume very heavily that we can read
|
|
* configuration info from the CIS. If not, we won't set up correctly.
|
|
*/
|
|
static int
|
|
pcmio(int slotno, ISAConf *isa)
|
|
{
|
|
uchar we, x, *p;
|
|
PCMslot *pp;
|
|
PCMconftab *ct, *et, *t;
|
|
PCMmap *m;
|
|
int i, index, irq;
|
|
char *cp;
|
|
|
|
irq = isa->irq;
|
|
if(irq == 2)
|
|
irq = 9;
|
|
|
|
if(slotno > nslot)
|
|
return -1;
|
|
pp = slot + slotno;
|
|
|
|
if(!pp->occupied)
|
|
return -1;
|
|
|
|
et = &pp->ctab[pp->nctab];
|
|
|
|
ct = 0;
|
|
for(i = 0; i < isa->nopt; i++){
|
|
if(strncmp(isa->opt[i], "index=", 6))
|
|
continue;
|
|
index = strtol(&isa->opt[i][6], &cp, 0);
|
|
if(cp == &isa->opt[i][6] || index >= pp->nctab)
|
|
return -1;
|
|
ct = &pp->ctab[index];
|
|
}
|
|
|
|
if(ct == 0){
|
|
/* assume default is right */
|
|
if(pp->def)
|
|
ct = pp->def;
|
|
else
|
|
ct = pp->ctab;
|
|
|
|
/* try for best match */
|
|
if(ct->nio == 0
|
|
|| ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){
|
|
for(t = pp->ctab; t < et; t++)
|
|
if(t->nio
|
|
&& t->io[0].start == isa->port
|
|
&& ((1<<irq) & t->irqs)){
|
|
ct = t;
|
|
break;
|
|
}
|
|
}
|
|
if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){
|
|
for(t = pp->ctab; t < et; t++)
|
|
if(t->nio && ((1<<irq) & t->irqs)){
|
|
ct = t;
|
|
break;
|
|
}
|
|
}
|
|
if(ct->nio == 0){
|
|
for(t = pp->ctab; t < et; t++)
|
|
if(t->nio){
|
|
ct = t;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ct == et || ct->nio == 0)
|
|
return -1;
|
|
if(isa->port == 0 && ct->io[0].start == 0)
|
|
return -1;
|
|
|
|
/* route interrupts */
|
|
isa->irq = irq;
|
|
wrreg(pp, Rigc, irq | Fnotreset | Fiocard);
|
|
|
|
/* set power and enable device */
|
|
x = vcode(ct->vpp1);
|
|
wrreg(pp, Rpc, x|Fautopower|Foutena|Fcardena);
|
|
|
|
/* 16-bit data path */
|
|
if(ct->bit16)
|
|
x = Ftiming|Fiocs16|Fwidth16;
|
|
else
|
|
x = Ftiming;
|
|
if(ct->nio == 2 && ct->io[1].start)
|
|
x |= x<<4;
|
|
wrreg(pp, Rio, x);
|
|
|
|
/*
|
|
* enable io port map 0
|
|
* the 'top' register value includes the last valid address
|
|
*/
|
|
if(isa->port == 0)
|
|
isa->port = ct->io[0].start;
|
|
we = rdreg(pp, Rwe);
|
|
wrreg(pp, Riobtm0lo, isa->port);
|
|
wrreg(pp, Riobtm0hi, isa->port>>8);
|
|
i = isa->port+ct->io[0].len-1;
|
|
wrreg(pp, Riotop0lo, i);
|
|
wrreg(pp, Riotop0hi, i>>8);
|
|
we |= 1<<6;
|
|
if(ct->nio >= 2 && ct->io[1].start){
|
|
wrreg(pp, Riobtm1lo, ct->io[1].start);
|
|
wrreg(pp, Riobtm1hi, ct->io[1].start>>8);
|
|
i = ct->io[1].start+ct->io[1].len-1;
|
|
wrreg(pp, Riotop1lo, i);
|
|
wrreg(pp, Riotop1hi, i>>8);
|
|
we |= 1<<7;
|
|
}
|
|
wrreg(pp, Rwe, we);
|
|
|
|
/* only touch Rconfig if it is present */
|
|
m = pcmmap(slotno, pp->cfg[0].caddr + Rconfig, 0x20, 1);
|
|
p = KADDR(m->isa + pp->cfg[0].caddr - m->ca);
|
|
if(pp->cfg[0].cpresent & (1<<Rconfig)){
|
|
/* Reset adapter */
|
|
|
|
/* set configuration and interrupt type.
|
|
* if level is possible on the card, use it.
|
|
*/
|
|
x = ct->index;
|
|
if(ct->irqtype & 0x20)
|
|
x |= Clevel;
|
|
|
|
/* enable the device, enable address decode and
|
|
* irq enable.
|
|
*/
|
|
x |= Cfunc|Cdecode|Cirq;
|
|
|
|
p[0] = x;
|
|
//delay(5);
|
|
microdelay(40);
|
|
}
|
|
|
|
if(pp->cfg[0].cpresent & (1<<Riobase0)){
|
|
/* set up the iobase 0 */
|
|
p[Riobase0 << 1] = isa->port;
|
|
p[Riobase1 << 1] = isa->port >> 8;
|
|
}
|
|
|
|
if(pp->cfg[0].cpresent & (1<<Riosize))
|
|
p[Riosize << 1] = ct->io[0].len;
|
|
pcmunmap(slotno, m);
|
|
return 0;
|
|
}
|