a269ced358
From richard: A couple of patches applied yesterday should make debugging on ARM a bit more reliable. Using db or acid on ARM, you may have noticed that a program being debugged would sometimes execute through a breakpoint without stopping, or run away while being single stepped. It turns out, as often happens, that one symptom had two separate causes. For details: /n/sources/patch/applied/5db-condcode/readme /n/sources/patch/applied/arm-bkpt-cond/readme To take advantage of the patches, rebuild libmach.a, then acid and db. On machines with a kw kernel (sheevaplug et al), you'll also want to rebuild /arm/9plug; otherwise breakpoints will stop working at all. The new 9plug will, however, still work with the old libmach; and the bcm and teg2 kernels are already compatible with the new libmach.
680 lines
13 KiB
C
680 lines
13 KiB
C
/*
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* sheevaplug traps, exceptions, interrupts, system calls.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/error.h"
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#include "arm.h"
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enum {
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Ntimevec = 20, /* # of time buckets for each intr */
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Nvecs = 256,
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};
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extern int notify(Ureg*);
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extern int ldrexvalid;
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typedef struct Vctl Vctl;
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typedef struct Vctl {
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Vctl* next; /* handlers on this vector */
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char *name; /* of driver, xallocated */
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void (*f)(Ureg*, void*); /* handler to call */
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void* a; /* argument to call it with */
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} Vctl;
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static Lock vctllock;
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static Vctl* vctl[32];
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uvlong ninterrupt;
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uvlong ninterruptticks;
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ulong intrtimes[Nvecs][Ntimevec];
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typedef struct Handler Handler;
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struct Handler {
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void (*r)(Ureg*, void*);
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void *a;
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char name[KNAMELEN];
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};
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static Handler irqlo[32];
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static Handler irqhi[32];
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static Handler irqbridge[32];
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static Lock irqlock;
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static int probing, trapped;
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typedef struct Irq Irq;
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struct Irq {
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ulong *irq;
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ulong *irqmask;
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Handler *irqvec;
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int nirqvec;
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char *name;
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};
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/* irq and irqmask are filled in by trapinit */
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static Irq irqs[] = {
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[Irqlo] {nil, nil, irqlo, nelem(irqlo), "lo"},
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[Irqhi] {nil, nil, irqhi, nelem(irqhi), "hi"},
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[Irqbridge] {nil, nil, irqbridge, nelem(irqbridge), "bridge"},
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};
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/*
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* keep histogram of interrupt service times
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*/
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void
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intrtime(Mach*, int vno)
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{
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ulong diff, x;
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if (m == nil)
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return;
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x = perfticks();
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diff = x - m->perf.intrts;
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m->perf.intrts = x;
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m->perf.inintr += diff;
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if(up == nil && m->perf.inidle > diff)
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m->perf.inidle -= diff;
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if (m->cpuhz == 0) /* not set yet? */
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return;
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diff /= (m->cpuhz/1000000)*100; /* quantum = 100µsec */
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if(diff >= Ntimevec)
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diff = Ntimevec-1;
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assert(vno >= 0 && vno < Nvecs);
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intrtimes[vno][diff]++;
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}
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void
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intrfmtcounts(char *s, char *se)
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{
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USED(s, se);
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}
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static void
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dumpcounts(void)
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{
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}
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void
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intrclear(int sort, int v)
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{
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*irqs[sort].irq = ~(1 << v);
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}
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void
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intrmask(int sort, int v)
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{
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*irqs[sort].irqmask &= ~(1 << v);
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}
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void
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intrunmask(int sort, int v)
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{
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*irqs[sort].irqmask |= 1 << v;
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}
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static void
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maskallints(void)
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{
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CpucsReg *cpu = (CpucsReg *)soc.cpu;
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IntrReg *intr;
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/* no fiq or ep in use */
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intr = (IntrReg *)soc.intr;
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intr->lo.irqmask = 0;
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intr->hi.irqmask = 0;
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cpu->irqmask = 0;
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coherence();
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}
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void
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intrset(Handler *h, void (*f)(Ureg*, void*), void *a, char *name)
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{
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if(h->r != nil) {
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// iprint("duplicate irq: %s (%#p)\n", h->name, h->r);
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return;
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}
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h->r = f;
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h->a = a;
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strncpy(h->name, name, KNAMELEN-1);
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h->name[KNAMELEN-1] = 0;
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}
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void
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intrunset(Handler *h)
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{
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h->r = nil;
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h->a = nil;
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h->name[0] = 0;
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}
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void
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intrdel(Handler *h, void (*f)(Ureg*, void*), void *a, char *name)
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{
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if(h->r != f || h->a != a || strcmp(h->name, name) != 0)
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return;
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intrunset(h);
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}
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void
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intrenable(int sort, int v, void (*f)(Ureg*, void*), void *a, char *name)
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{
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//iprint("enabling intr %d vec %d for %s\n", sort, v, name);
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ilock(&irqlock);
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intrset(&irqs[sort].irqvec[v], f, a, name);
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intrunmask(sort, v);
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iunlock(&irqlock);
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}
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void
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intrdisable(int sort, int v, void (*f)(Ureg*, void*), void* a, char *name)
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{
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ilock(&irqlock);
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intrdel(&irqs[sort].irqvec[v], f, a, name);
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intrmask(sort, v);
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iunlock(&irqlock);
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}
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/*
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* called by trap to handle interrupts
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*/
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static void
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intrs(Ureg *ur, int sort)
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{
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int i, s;
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ulong ibits;
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Handler *h;
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Irq irq;
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assert(sort >= 0 && sort < nelem(irqs));
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irq = irqs[sort];
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ibits = *irq.irq;
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ibits &= *irq.irqmask;
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for(i = 0; i < irq.nirqvec && ibits; i++)
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if(ibits & (1<<i)){
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h = &irq.irqvec[i];
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if(h->r != nil){
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h->r(ur, h->a);
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splhi();
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intrtime(m, sort*32 + i);
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if (sort == Irqbridge && i == IRQcputimer0)
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m->inclockintr = 1;
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ibits &= ~(1<<i);
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}
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}
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if(ibits != 0) {
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iprint("spurious irq%s interrupt: %8.8lux\n", irq.name, ibits);
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s = splfhi();
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*irq.irq &= ibits;
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*irq.irqmask &= ~ibits;
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splx(s);
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}
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}
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void
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intrhi(Ureg *ureg, void*)
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{
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intrs(ureg, Irqhi);
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}
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void
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intrbridge(Ureg *ureg, void*)
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{
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intrs(ureg, Irqbridge);
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intrclear(Irqlo, IRQ0bridge);
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}
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void
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trapinit(void)
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{
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int i;
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CpucsReg *cpu;
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IntrReg *intr;
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Vectorpage *page0 = (Vectorpage*)HVECTORS;
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intr = (IntrReg *)soc.intr;
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cpu = (CpucsReg *)soc.cpu;
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irqs[Irqlo].irq = &intr->lo.irq;
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irqs[Irqlo].irqmask = &intr->lo.irqmask;
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irqs[Irqhi].irq = &intr->hi.irq;
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irqs[Irqhi].irqmask = &intr->hi.irqmask;
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irqs[Irqbridge].irq = &cpu->irq;
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irqs[Irqbridge].irqmask = &cpu->irqmask;
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coherence();
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setr13(PsrMfiq, m->fiqstack + nelem(m->fiqstack));
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setr13(PsrMirq, m->irqstack + nelem(m->irqstack));
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setr13(PsrMabt, m->abtstack + nelem(m->abtstack));
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setr13(PsrMund, m->undstack + nelem(m->undstack));
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memmove(page0->vectors, vectors, sizeof page0->vectors);
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memmove(page0->vtable, vtable, sizeof page0->vtable);
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cacheuwbinv();
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l2cacheuwbinv();
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cpu->cpucfg &= ~Cfgvecinithi;
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for(i = 0; i < nelem(irqlo); i++)
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intrunset(&irqlo[i]);
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for(i = 0; i < nelem(irqhi); i++)
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intrunset(&irqhi[i]);
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for(i = 0; i < nelem(irqbridge); i++)
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intrunset(&irqbridge[i]);
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/* disable all interrupts */
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intr->lo.fiqmask = intr->hi.fiqmask = 0;
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intr->lo.irqmask = intr->hi.irqmask = 0;
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intr->lo.epmask = intr->hi.epmask = 0;
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cpu->irqmask = 0;
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coherence();
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/* clear interrupts */
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intr->lo.irq = intr->hi.irq = ~0;
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cpu->irq = ~0;
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coherence();
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intrenable(Irqlo, IRQ0hisum, intrhi, nil, "hi");
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intrenable(Irqlo, IRQ0bridge, intrbridge, nil, "bridge");
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/* enable watchdog & access-error interrupts */
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cpu->irqmask |= 1 << IRQcputimerwd | 1 << IRQaccesserr;
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coherence();
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}
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static char *trapnames[PsrMask+1] = {
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[ PsrMusr ] "user mode",
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[ PsrMfiq ] "fiq interrupt",
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[ PsrMirq ] "irq interrupt",
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[ PsrMsvc ] "svc/swi exception",
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[ PsrMabt ] "prefetch abort/data abort",
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[ PsrMabt+1 ] "data abort",
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[ PsrMund ] "undefined instruction",
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[ PsrMsys ] "sys trap",
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};
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static char *
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trapname(int psr)
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{
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char *s;
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s = trapnames[psr & PsrMask];
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if(s == nil)
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s = "unknown trap number in psr";
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return s;
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}
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/*
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* called by trap to handle access faults
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*/
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static void
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faultarm(Ureg *ureg, uintptr va, int user, int read)
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{
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int n, insyscall;
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char buf[ERRMAX];
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static int cnt, lastpid;
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static ulong lastva;
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if(up == nil) {
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dumpregs(ureg);
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panic("fault: nil up in faultarm, accessing %#p", va);
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}
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insyscall = up->insyscall;
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up->insyscall = 1;
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/* this is quite helpful during mmu and cache debugging */
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if(va == lastva && up->pid == lastpid) {
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++cnt;
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if (cnt >= 2)
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/* fault() isn't fixing the underlying cause */
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panic("fault: %d consecutive faults for va %#lux",
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cnt+1, va);
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} else {
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cnt = 0;
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lastva = va;
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lastpid = up->pid;
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}
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n = fault(va, read);
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if(n < 0){
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if(!user){
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dumpregs(ureg);
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panic("fault: kernel accessing %#p", va);
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}
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/* don't dump registers; programs suicide all the time */
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snprint(buf, sizeof buf, "sys: trap: fault %s va=%#p",
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read? "read": "write", va);
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postnote(up, 1, buf, NDebug);
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}
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up->insyscall = insyscall;
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}
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/*
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* returns 1 if the instruction writes memory, 0 otherwise
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*/
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int
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writetomem(ulong inst)
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{
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/* swap always write memory */
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if((inst & 0x0FC00000) == 0x01000000)
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return 1;
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/* loads and stores are distinguished by bit 20 */
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if(inst & (1<<20))
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return 0;
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return 1;
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}
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void
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trap(Ureg *ureg)
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{
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int user, x, rv, rem;
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ulong inst;
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u32int fsr;
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uintptr va;
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char buf[ERRMAX];
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if(up != nil)
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rem = (char*)ureg - up->kstack;
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else
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rem = (char*)ureg - ((char*)m + sizeof(Mach));
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if(rem < 256) {
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dumpstack();
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panic("trap %d bytes remaining, up %#p ureg %#p at pc %#lux",
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rem, up, ureg, ureg->pc);
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}
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user = (ureg->psr & PsrMask) == PsrMusr;
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if(user){
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up->dbgreg = ureg;
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cycles(&up->kentry);
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}
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if(ureg->type == PsrMabt+1)
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ureg->pc -= 8;
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else
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ureg->pc -= 4;
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m->inclockintr = 0;
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switch(ureg->type) {
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default:
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panic("unknown trap %ld", ureg->type);
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break;
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case PsrMirq:
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ldrexvalid = 0;
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// splflo(); /* allow fast interrupts */
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intrs(ureg, Irqlo);
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m->intr++;
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break;
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case PsrMabt: /* prefetch fault */
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ldrexvalid = 0;
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faultarm(ureg, ureg->pc, user, 1);
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if(up->nnote == 0 &&
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(*(u32int*)ureg->pc & ~(0xF<<28)) == 0x01200070)
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postnote(up, 1, "sys: breakpoint", NDebug);
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break;
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case PsrMabt+1: /* data fault */
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ldrexvalid = 0;
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va = farget();
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inst = *(ulong*)(ureg->pc);
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fsr = fsrget() & 0xf;
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if (probing && !user) {
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if (trapped++ > 0)
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panic("trap: recursive probe %#lux", va);
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ureg->pc += 4; /* continue at next instruction */
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break;
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}
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switch(fsr){
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case 0x0:
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panic("vector exception at %#lux", ureg->pc);
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break;
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case 0x1:
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case 0x3:
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if(user){
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snprint(buf, sizeof buf,
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"sys: alignment: pc %#lux va %#p\n",
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ureg->pc, va);
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postnote(up, 1, buf, NDebug);
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} else
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panic("kernel alignment: pc %#lux va %#p", ureg->pc, va);
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break;
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case 0x2:
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panic("terminal exception at %#lux", ureg->pc);
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break;
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case 0x4:
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case 0x6:
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case 0x8:
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case 0xa:
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case 0xc:
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case 0xe:
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panic("external abort %#ux pc %#lux addr %#px",
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fsr, ureg->pc, va);
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break;
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case 0x5: /* translation fault, no section entry */
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case 0x7: /* translation fault, no page entry */
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faultarm(ureg, va, user, !writetomem(inst));
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break;
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case 0x9:
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case 0xb:
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/* domain fault, accessing something we shouldn't */
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if(user){
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snprint(buf, sizeof buf,
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"sys: access violation: pc %#lux va %#p\n",
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ureg->pc, va);
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postnote(up, 1, buf, NDebug);
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} else
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panic("kernel access violation: pc %#lux va %#p",
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ureg->pc, va);
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break;
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case 0xd:
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case 0xf:
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/* permission error, copy on write or real permission error */
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faultarm(ureg, va, user, !writetomem(inst));
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break;
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}
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break;
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case PsrMund: /* undefined instruction */
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if(user){
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if(seg(up, ureg->pc, 0) != nil &&
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(*(u32int*)ureg->pc & ~(0xF<<28)) == 0x01200070)
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postnote(up, 1, "sys: breakpoint", NDebug);
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else{
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/* look for floating point instructions to interpret */
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x = spllo();
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rv = fpiarm(ureg);
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splx(x);
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if(rv == 0){
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ldrexvalid = 0;
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snprint(buf, sizeof buf,
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"undefined instruction: pc %#lux",
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ureg->pc);
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postnote(up, 1, buf, NDebug);
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}
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}
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}else{
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iprint("undefined instruction: pc %#lux inst %#ux\n",
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ureg->pc, ((u32int*)ureg->pc)[-2]);
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panic("undefined instruction");
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}
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break;
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}
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splhi();
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/* delaysched set because we held a lock or because our quantum ended */
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if(up && up->delaysched && m->inclockintr){
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ldrexvalid = 0;
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sched();
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splhi();
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}
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if(user){
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if(up->procctl || up->nnote)
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notify(ureg);
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kexit(ureg);
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}
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}
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int
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isvalidaddr(void *v)
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{
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return (uintptr)v >= KZERO;
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}
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void
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dumplongs(char *msg, ulong *v, int n)
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{
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int i, l;
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l = 0;
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iprint("%s at %.8p: ", msg, v);
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for(i=0; i<n; i++){
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if(l >= 4){
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iprint("\n %.8p: ", v);
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l = 0;
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}
|
|
if(isvalidaddr(v)){
|
|
iprint(" %.8lux", *v++);
|
|
l++;
|
|
}else{
|
|
iprint(" invalid");
|
|
break;
|
|
}
|
|
}
|
|
iprint("\n");
|
|
}
|
|
|
|
static void
|
|
dumpstackwithureg(Ureg *ureg)
|
|
{
|
|
uintptr l, i, v, estack;
|
|
u32int *p;
|
|
|
|
iprint("ktrace /kernel/path %#.8lux %#.8lux %#.8lux # pc, sp, link\n",
|
|
ureg->pc, ureg->sp, ureg->r14);
|
|
delay(2000);
|
|
i = 0;
|
|
if(up != nil && (uintptr)&l <= (uintptr)up->kstack+KSTACK)
|
|
estack = (uintptr)up->kstack+KSTACK;
|
|
else if((uintptr)&l >= (uintptr)m->stack
|
|
&& (uintptr)&l <= (uintptr)m+MACHSIZE)
|
|
estack = (uintptr)m+MACHSIZE;
|
|
else{
|
|
if(up != nil)
|
|
iprint("&up->kstack %#p &l %#p\n", up->kstack, &l);
|
|
else
|
|
iprint("&m %#p &l %#p\n", m, &l);
|
|
return;
|
|
}
|
|
for(l = (uintptr)&l; l < estack; l += sizeof(uintptr)){
|
|
v = *(uintptr*)l;
|
|
if(KTZERO < v && v < (uintptr)etext && !(v & 3)){
|
|
v -= sizeof(u32int); /* back up an instr */
|
|
p = (u32int*)v;
|
|
if((*p & 0x0f000000) == 0x0b000000){ /* BL instr? */
|
|
iprint("%#8.8lux=%#8.8lux ", l, v);
|
|
i++;
|
|
}
|
|
}
|
|
if(i == 4){
|
|
i = 0;
|
|
iprint("\n");
|
|
}
|
|
}
|
|
if(i)
|
|
iprint("\n");
|
|
}
|
|
|
|
/*
|
|
* Fill in enough of Ureg to get a stack trace, and call a function.
|
|
* Used by debugging interface rdb.
|
|
*/
|
|
void
|
|
callwithureg(void (*fn)(Ureg*))
|
|
{
|
|
Ureg ureg;
|
|
|
|
ureg.pc = getcallerpc(&fn);
|
|
ureg.sp = PTR2UINT(&fn);
|
|
fn(&ureg);
|
|
}
|
|
|
|
void
|
|
dumpstack(void)
|
|
{
|
|
callwithureg(dumpstackwithureg);
|
|
}
|
|
|
|
void
|
|
dumpregs(Ureg* ureg)
|
|
{
|
|
int s;
|
|
|
|
if (ureg == nil) {
|
|
iprint("trap: no user process\n");
|
|
return;
|
|
}
|
|
s = splhi();
|
|
iprint("trap: %s", trapname(ureg->type));
|
|
if(ureg != nil && (ureg->psr & PsrMask) != PsrMsvc)
|
|
iprint(" in %s", trapname(ureg->psr));
|
|
iprint("\n");
|
|
iprint("psr %8.8lux type %2.2lux pc %8.8lux link %8.8lux\n",
|
|
ureg->psr, ureg->type, ureg->pc, ureg->link);
|
|
iprint("R14 %8.8lux R13 %8.8lux R12 %8.8lux R11 %8.8lux R10 %8.8lux\n",
|
|
ureg->r14, ureg->r13, ureg->r12, ureg->r11, ureg->r10);
|
|
iprint("R9 %8.8lux R8 %8.8lux R7 %8.8lux R6 %8.8lux R5 %8.8lux\n",
|
|
ureg->r9, ureg->r8, ureg->r7, ureg->r6, ureg->r5);
|
|
iprint("R4 %8.8lux R3 %8.8lux R2 %8.8lux R1 %8.8lux R0 %8.8lux\n",
|
|
ureg->r4, ureg->r3, ureg->r2, ureg->r1, ureg->r0);
|
|
iprint("stack is at %#p\n", ureg);
|
|
iprint("pc %#lux link %#lux\n", ureg->pc, ureg->link);
|
|
|
|
if(up)
|
|
iprint("user stack: %#p-%#p\n", up->kstack, up->kstack+KSTACK-4);
|
|
else
|
|
iprint("kernel stack: %8.8lux-%8.8lux\n",
|
|
(ulong)(m+1), (ulong)m+BY2PG-4);
|
|
dumplongs("stack", (ulong *)(ureg + 1), 16);
|
|
delay(2000);
|
|
dumpstack();
|
|
splx(s);
|
|
}
|
|
|
|
void
|
|
idlehands(void)
|
|
{
|
|
extern void _idlehands(void);
|
|
|
|
_idlehands();
|
|
}
|
|
|
|
vlong
|
|
probeaddr(uintptr addr)
|
|
{
|
|
vlong v;
|
|
static Lock fltlck;
|
|
|
|
ilock(&fltlck);
|
|
trapped = 0;
|
|
probing = 1;
|
|
coherence();
|
|
|
|
v = *(ulong *)addr; /* this may cause a fault */
|
|
USED(probing);
|
|
coherence();
|
|
|
|
probing = 0;
|
|
coherence();
|
|
if (trapped)
|
|
v = -1;
|
|
iunlock(&fltlck);
|
|
return v;
|
|
}
|