811b80cae1
the raspberry pi 4 has a new interrupt controller and pci support, so get rid of intrenable() macro and properly make intrenable function with tbdf argument.
172 lines
3.1 KiB
C
172 lines
3.1 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/error.h"
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#define INTREGS (VIRTIO+0xB200)
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enum {
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Fiqenable = 1<<7,
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Localtimerint = 0x40,
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Localmboxint = 0x50,
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Localintpending = 0x60,
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};
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/*
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* interrupt control registers
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*/
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typedef struct Intregs Intregs;
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struct Intregs {
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u32int ARMpending;
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u32int GPUpending[2];
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u32int FIQctl;
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u32int GPUenable[2];
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u32int ARMenable;
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u32int GPUdisable[2];
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u32int ARMdisable;
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};
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typedef struct Vctl Vctl;
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struct Vctl {
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Vctl *next;
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int irq;
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u32int *reg;
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u32int mask;
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void (*f)(Ureg*, void*);
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void *a;
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};
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static Lock vctllock;
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static Vctl *vctl[MAXMACH], *vfiq;
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void
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intrcpushutdown(void)
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{
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u32int *enable;
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if(soc.armlocal == 0)
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return;
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enable = (u32int*)(ARMLOCAL + Localtimerint) + m->machno;
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*enable = 0;
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if(m->machno){
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enable = (u32int*)(ARMLOCAL + Localmboxint) + m->machno;
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*enable = 1;
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}
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}
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void
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intrsoff(void)
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{
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Intregs *ip;
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int disable;
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ip = (Intregs*)INTREGS;
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disable = ~0;
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ip->GPUdisable[0] = disable;
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ip->GPUdisable[1] = disable;
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ip->ARMdisable = disable;
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ip->FIQctl = 0;
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}
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/*
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* called by trap to handle irq interrupts.
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* returns true iff a clock interrupt, thus maybe reschedule.
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*/
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int
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irq(Ureg* ureg)
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{
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Vctl *v;
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int clockintr;
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m->intr++;
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clockintr = 0;
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for(v = vctl[m->machno]; v != nil; v = v->next)
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if((*v->reg & v->mask) != 0){
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coherence();
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v->f(ureg, v->a);
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coherence();
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if(v->irq == IRQclock || v->irq == IRQcntps || v->irq == IRQcntpns)
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clockintr = 1;
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}
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return clockintr;
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}
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/*
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* called direct from lexception.s to handle fiq interrupt.
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*/
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void
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fiq(Ureg *ureg)
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{
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Vctl *v;
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m->intr++;
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v = vfiq;
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if(v == nil || m->machno)
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panic("cpu%d: unexpected item in bagging area", m->machno);
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coherence();
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v->f(ureg, v->a);
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coherence();
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}
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void
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intrenable(int irq, void (*f)(Ureg*, void*), void* a, int, char*)
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{
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Vctl *v;
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Intregs *ip;
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u32int *enable;
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int cpu;
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ip = (Intregs*)INTREGS;
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if((v = xalloc(sizeof(Vctl))) == nil)
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panic("irqenable: no mem");
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cpu = 0;
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v->irq = irq;
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if(irq >= IRQlocal){
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cpu = m->machno;
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v->reg = (u32int*)(ARMLOCAL + Localintpending) + cpu;
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if(irq >= IRQmbox0)
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enable = (u32int*)(ARMLOCAL + Localmboxint) + cpu;
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else
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enable = (u32int*)(ARMLOCAL + Localtimerint) + cpu;
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v->mask = 1 << (irq - IRQlocal);
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}else if(irq >= IRQbasic){
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enable = &ip->ARMenable;
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v->reg = &ip->ARMpending;
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v->mask = 1 << (irq - IRQbasic);
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}else{
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enable = &ip->GPUenable[irq/32];
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v->reg = &ip->GPUpending[irq/32];
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v->mask = 1 << (irq % 32);
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}
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v->f = f;
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v->a = a;
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lock(&vctllock);
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if(irq == IRQfiq){
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assert((ip->FIQctl & Fiqenable) == 0);
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assert((*enable & v->mask) == 0);
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assert(cpu == 0);
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vfiq = v;
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ip->FIQctl = Fiqenable | irq;
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}else{
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v->next = vctl[cpu];
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vctl[cpu] = v;
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if(irq >= IRQmbox0){
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if(irq <= IRQmbox3)
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*enable |= 1 << (irq - IRQmbox0);
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}else if(irq >= IRQlocal)
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*enable |= 1 << (irq - IRQlocal);
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else
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*enable = v->mask;
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}
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unlock(&vctllock);
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}
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void
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intrdisable(int, void (*)(Ureg*, void*), void*, int, char*)
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{
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}
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