b0d226705c
coproc.c generated the instrucitons anew each time, requiering a i+d cache flush for each operation. instead, we can speed this up like this: given that the coprocessor registers are per cpu, we can assume that interrupts have already been disabled by the caller to prevent a process switch to another cpu. we cache the instructions generated in a static append only buffer and maintain separate end pointers for each cpu. the cache flushes only need to be done when new operations have been added to the buffer.
164 lines
3.1 KiB
C
164 lines
3.1 KiB
C
/*
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* arm co-processors
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* mainly to cope with arm hard-wiring register numbers into instructions.
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*
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* CP15 (system control) is the one that gets used the most in practice.
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*
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* these routines must be callable from KZERO.
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*
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* on a multiprocessor, process switching to another cpu is assumed
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* to be inhibited by the caller as these registers are local to the cpu.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "arm.h"
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enum {
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/* alternates: 0xe12fff1e BX (R14); last e is R14 */
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/* 0xe28ef000 B 0(R14); second e is R14 (ken) */
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Retinst = 0xe1a0f00e, /* MOV R14, R15 */
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Opmask = MASK(3),
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Regmask = MASK(4),
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};
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static void*
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mkinstr(ulong wd)
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{
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static ulong ib[256], *ep[MAXMACH+1];
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static Lock lk;
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ulong *ip, *ie;
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ie = ep[m->machno];
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for(ip = ib; ip < ie; ip += 2)
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if(*ip == wd)
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return ip;
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ilock(&lk);
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ie = ep[MAXMACH];
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for(; ip < ie; ip += 2)
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if(*ip == wd)
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goto Found;
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if(ip >= &ib[nelem(ib)])
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panic("mkinstr: out of instrucuction buffer");
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ip[0] = wd;
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ip[1] = Retinst;
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ep[MAXMACH] = ie = ip + 2;
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cachedwbse(ip, 2*sizeof(*ip));
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Found:
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iunlock(&lk);
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cacheiinv();
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ep[m->machno] = ie;
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return ip;
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}
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static void*
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setupcpop(ulong opcode, int cp, int op1, int crn, int crm,
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int op2)
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{
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op1 &= Opmask;
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op2 &= Opmask;
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crn &= Regmask;
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crm &= Regmask;
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cp &= Regmask;
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return mkinstr(opcode | op1 << 21 | crn << 16 | cp << 8 | op2 << 5 | crm);
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}
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ulong
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cprd(int cp, int op1, int crn, int crm, int op2)
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{
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/*
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* MRC. return value will be in R0, which is convenient.
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* Rt will be R0.
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*/
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ulong (*fp)(void) = setupcpop(0xee100010, cp, op1, crn, crm, op2);
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return fp();
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}
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void
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cpwr(int cp, int op1, int crn, int crm, int op2, ulong val)
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{
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/* MCR, Rt is R0 */
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void (*fp)(ulong) = setupcpop(0xee000010, cp, op1, crn, crm, op2);
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fp(val);
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}
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ulong
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cprdsc(int op1, int crn, int crm, int op2)
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{
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return cprd(CpSC, op1, crn, crm, op2);
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}
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void
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cpwrsc(int op1, int crn, int crm, int op2, ulong val)
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{
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cpwr(CpSC, op1, crn, crm, op2, val);
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}
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/* floating point */
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/* fp coproc control */
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static void*
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setupfpctlop(int opcode, int fpctlreg)
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{
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fpctlreg &= Nfpctlregs - 1;
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return mkinstr(opcode | fpctlreg << 16 | 0 << 12 | CpFP << 8);
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}
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ulong
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fprd(int fpreg)
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{
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/*
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* VMRS. return value will be in R0, which is convenient.
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* Rt will be R0.
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*/
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ulong (*fp)(void) = setupfpctlop(0xeef00010, fpreg);
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return fp();
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}
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void
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fpwr(int fpreg, ulong val)
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{
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/*
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* fpu might be off and this VMSR might enable it
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* VMSR, Rt is R0
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*/
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void (*fp)(ulong) = setupfpctlop(0xeee00010, fpreg);
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fp(val);
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}
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/* fp register access; don't bother with single precision */
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static void*
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setupfpop(int opcode, int fpreg)
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{
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ulong wd = opcode | 0 << 16 | (fpreg & (16 - 1)) << 12;
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if (fpreg >= 16)
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wd |= 1 << 22; /* high bit of dfp reg # */
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return mkinstr(wd);
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}
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ulong
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fpsavereg(int fpreg, uvlong *fpp)
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{
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/*
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* VSTR. pointer will be in R0, which is convenient.
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* Rt will be R0.
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*/
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ulong (*fp)(uvlong *) = setupfpop(0xed000000 | CpDFP << 8, fpreg);
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return fp(fpp);
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}
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void
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fprestreg(int fpreg, uvlong val)
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{
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/* VLDR, Rt is R0 */
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void (*fp)(uvlong *) = setupfpop(0xed100000 | CpDFP << 8, fpreg);
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fp(&val);
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}
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