486 lines
11 KiB
Plaintext
486 lines
11 KiB
Plaintext
.TH VGADB 6
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.SH NAME
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vgadb \- VGA controller and monitor database
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.SH DESCRIPTION
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.PP
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The VGA database,
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.BR /lib/vgadb ,
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consists of two parts,
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the first describing how to identify and program a VGA controller
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and the second describing the timing parameters for known
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monitors to be loaded into a VGA controller to give a particular
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resolution and refresh rate.
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Conventionally, at system boot, the program
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.B aux/vga
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(see
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.IR vga (8))
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uses the monitor type in
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.BR /env/monitor ,
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the display resolution in
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.BR /env/vgasize ,
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and the VGA controller information in the database to
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find a matching monitor entry and initialize the VGA controller accordingly.
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.PP
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The file comprises multi-line entries made up of
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attribute/value pairs of the form
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.IB attr = value
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or sometimes just
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.IR attr .
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Each line starting without white space starts a new entry.
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Lines starting with
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.B #
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are comments.
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.PP
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The first part of the database, the VGA controller identification and
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programming information,
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consists of a number of entries with attribute
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.B ctlr
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and no value.
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Within one of these entries the following attributes are
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meaningful:
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.TF 0xC0000
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.TP
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.I nnnnn
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an offset into the VGA BIOS area.
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The value is a string expected to be found there that will
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identify the controller.
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For example,
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.B 0xC0068="#9GXE64 Pro"
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would identify a #9GXEpro VGA controller if the string
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.B "#9GXE64 Pro"
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was found in the BIOS at address 0xC0068.
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There may be more than one identifier attribute per controller.
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If a match cannot be found, the first few bytes of the BIOS
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are printed to help identify the card and create a controller
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entry.
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.TP
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.IB nnnnn - mmmmm
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A range of the VGA BIOS area.
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The value is a string as above, but the entire range
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is searched for that string.
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The string must begin at or after
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.I nnnnn
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and not contain any characters at or after
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.IR mmmmm .
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For example,
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.B 0xC0000-0xC0200="MACH64LP"
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identifies a Mach 64 controller with the
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string
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.B MACH64LP
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occurring anywhere in the first 512 bytes of BIOS memory.
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.TP
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.B ctlr
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VGA controller chip type.
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This must match one of the VGA controller types
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known to
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.B /dev/vgactl
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(see
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.IR vga (3))
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and internally to
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.BR aux/vga .
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Currently,
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.BR ark2000pv ,
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.BR clgd542x ,
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.BR ct65540 ,
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.BR ct65545 ,
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.BR cyber938x ,
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.BR et4000 ,
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.BR hiqvideo ,
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.BR ibm8514 ,
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.BR mach32 ,
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.BR mach64 ,
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.BR mach64xx ,
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.BR mga2164w ,
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.BR neomagic ,
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.BR s3801 ,
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.BR s3805 ,
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.BR s3928 ,
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.BR t2r4 ,
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.BR trio64 ,
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.BR virge ,
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.BR vision864 ,
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.BR vision964 ,
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.BR vision968 ,
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and
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.B w30c516
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are recognized.
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.TP
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.B ramdac
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RAMDAC controller type.
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This must match one of the types
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known internally to
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.BR aux/vga .
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Currently
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.BR att20c490 ,
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.BR att20c491 ,
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.BR att20c492 ,
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.BR att21c498 ,
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.BR bt485 ,
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.BR rgb524mn ,
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.BR sc15025 ,
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.BR stg1702 ,
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.BR tvp3020 ,
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.BR tvp3025 ,
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and
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.B tvp3026
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are recognized.
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.TP
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.B clock
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clock generator type.
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This must match one of the types
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known internally to
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.BR aux/vga .
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Currently
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.BR ch9294 ,
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.BR icd2061a ,
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.BR ics2494 ,
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.BR ics2494a ,
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.BR s3clock ,
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.BR tvp3025clock ,
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and
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.B tvp3026clock
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are recognized.
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.TP
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.B hwgc
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hardware graphics cursor type.
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This must match one of the types
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known to
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.B /dev/vgactl
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and internally to
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.BR aux/vga .
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Currently
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.BR ark200pvhwgc ,
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.BR bt485hwgc ,
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.BR clgd542xhwgc ,
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.BR clgd546xhwgc ,
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.BR ct65545hwgc ,
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.BR cyber938xhwgc ,
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.BR hiqvideohwgc ,
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.BR mach64xxhwgc ,
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.BR mga2164whwgc ,
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.BR neomagichwgc ,
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.BR rgb524hwgc ,
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.BR s3hwgc ,
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.BR t2r4hwgc ,
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.BR tvp3020hwgc ,
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and
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.B tvp3026hwgc
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are recognized.
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.TP
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.B membw
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Memory bandwidth in megabytes per second.
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.I Vga
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chooses the highest refresh rate possible within the constraints
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of the monitor (explained below) and the
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card's memory bandwidth.
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.TP
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.B linear
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Whether the card supports a large (>64kb) linear memory
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window. The value is either
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.B 1
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or
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.B 0
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(equivalent to unspecified).
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The current kernel graphics subsystem
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requires a linear window; entries without
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.B linear=1
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are of historic value only.
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.TP
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.B link
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This must match one of the types
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known internally to
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.BR aux/vga .
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Currently
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.B vga
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and
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.B ibm8514
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are recognized.
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The type
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.B vga
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handles generic VGA functions and should almost always be included.
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The type
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.B Ibm8514
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handles basic graphics accelerator initialization on controllers
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such as the early S3 family of GUI chips.
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.PD
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.PP
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The
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.BR clock ,
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.BR ctlr ,
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.BR link ,
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and
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.B ramdac
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values can all take an extension following a
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.B '-'
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that can be used as a speed-grade
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or subtype; matching is done without the extension.
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For example,
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.B ramdac=stg1702-135
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indicates the STG1702 RAMDAC has a maximum clock frequency of 135MHz,
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and
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.B clock=ics2494a-324
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indicates that the frequency table numbered
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324
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should be used for the ICS2494A clock generator.
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.PP
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The functions internal to
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.B aux/vga
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corresponding to the
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.BR clock ,
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.BR ctlr ,
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.BR link ,
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and
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.B ramdac
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values will be called in the order given for initialization.
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Sometimes the clock should be set before the RAMDAC is initialized,
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for example, depending on the components used.
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In general,
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.BR link=vga
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will always be first and,
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if appropriate,
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.BR link=ibm8514
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will be last.
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.PP
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The entries in the second part of
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.B /lib/vgadb
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have as attribute the name of a monitor type
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and the value is conventionally a resolution in the form
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.IB X x Y\f1,
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where
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.I X
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and
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.I Y
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are numbers representing width and height in pixels.
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The monitor type (i.e. entry)
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.B include
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has special properties, described below and shown in the examples.
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The remainder of the entry contains timing information for
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the desired resolution.
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Within one of these entries the following attributes are
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meaningful:
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.TF interlace
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.TP
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.B clock
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the video dot-clock frequency in MHz required for this resolution.
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The value 25.175 is known internally to
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.IR vga (8)
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as the baseline VGA clock rate.
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.B defaultclock
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the default video dot-clock frequency in MHz used
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for this resolution when no
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memory bandwidth is specified for the card
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or when
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.I vga
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cannot determine the maximum clock frequency of the card.
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.TP
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.B shb
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start horizontal blanking, in character clocks.
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.TP
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.B ehb
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end horizontal blanking, in character clocks.
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.TP
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.B ht
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horizontal total, in character clocks.
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.TP
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.B vrs
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vertical refresh start, in character clocks.
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.TP
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.B vre
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vertical refresh end, in character clocks.
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.TP
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.B vt
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vertical total, in character clocks.
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.TP
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.B hsync
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horizontal sync polarity.
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Value must be
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.B +
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or
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.BR - .
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.TP
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.B vsync
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vertical sync polarity.
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Value must be
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.B +
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or
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.BR - .
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.TP
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.B interlace
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interlaced mode.
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Only value
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.B v
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is recognized.
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.TP
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.B alias
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continue, replacing the
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.B alias
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line by the contents of the entry whose attribute is given as
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.IR value .
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.TP
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.B include
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continue, replacing this
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.B include
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line by the contents of the previously defined
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.B include
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monitor type with matching
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.IR value .
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(See the examples.)
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Any non-zero attributes already set will not be overwritten.
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This is used to save duplication of timing information.
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Note that
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.I value
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is not parsed, it is only used as a string
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to identify the previous
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.BI include= value
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monitor type entry.
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.PD
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.PP
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The values given for
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.BR shb ,
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.BR ehb ,
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.BR ht ,
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.BR vrs ,
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.BR vre ,
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.BR vt ,
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.BR hsync ,
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and
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.B vsync
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are beyond the
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scope of this manual page.
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See the book by
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Ferraro
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for details.
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.SH EXAMPLES
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Basic
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.B ctlr
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entry for a laptop with a Chips and Technology 65550
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controller:
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.EX
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ctlr # NEC Versa 6030X/6200MX
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0xC0090="CHIPS 65550 PCI & VL Accelerated VGA BIOS"
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link=vga
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ctlr=hiqvideo linear=1
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hwgc=hiqvideohwgc
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.EE
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A more complex entry. Note the extensions on the
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.BR clock ,
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.BR ctlr ,
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and
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.B ramdac
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attributes. The order here is important: the RAMDAC clock input must be
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initialized before the RAMDAC itself. The clock frequency is selected by
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the
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.B ET4000
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chip.
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.EX
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ctlr # Hercules Dynamite Power
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0xC0076="Tseng Laboratories, Inc. 03/04/94 V8.00N"
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link=vga
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clock=ics2494a-324
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ctlr=et4000-w32p
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ramdac=stg1702-135
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.EE
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Monitor entry for type
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.B vga
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(the default monitor type used by
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.IR vga (8))
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and resolution 640x480x[18].
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.EX
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include = 640x480@60Hz # 60Hz, 31.5KHz
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clock=25.175
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shb=664 ehb=760 ht=800
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vrs=491 vre=493 vt=525
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vga = 640x480 # 60Hz, 31.5KHz
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include=640x480@60Hz
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.EE
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Entries for multisync monitors with video bandwidth up to 65MHz.
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.EX
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#
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# Multisync monitors with video bandwidth up to 65MHz.
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#
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multisync65 = 1024x768 # 60Hz, 48.4KHz
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include=1024x768@60Hz
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multisync65 = 1024x768i # 87Hz, 35.5KHz (interlaced)
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include=1024x768i@87Hz
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multisync65
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alias=vga
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.EE
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Note how this builds on the existing
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.B vga
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entries.
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.SH FILES
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.TP
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.B /lib/vgadb
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.SH "SEE ALSO"
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.IR ndb (2),
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.IR vga (3),
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.IR ndb (6),
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.IR vga (8)
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.br
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Richard E. Ferraro,
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.I
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Programming Guide to the EGA, VGA and Super VGA Cards,
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Third Edition
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.SH BUGS
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The database should provide a way
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to use the PCI bus
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as well as BIOS memory to identify cards.
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.SH "ADDING A NEW MONITOR"
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Adding a new monitor is usually fairly straightforward, as most modern monitors
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are multisync and the only interesting parameter is the
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maximum video bandwidth.
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Once the timing parameters are worked out for a particular maximum
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video bandwidth as in the example above, an entry for a new monitor
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with that limit is simply
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.EX
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#
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# Sony CPD-1304
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# Horizontal timing:
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# Allowable frequency range: 28-50KHz
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# Vertical timing:
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# Allowable frequency range: 50-87Hz
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#
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cpd-1304
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alias=multisync65
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.EE
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Even this is not necessary, as the monitor type could simply be
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given as
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.BR multisync65 .
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.SH "ADDING A NEW VGA CONTROLLER"
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While the use of this database formalizes the steps needed to
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program a VGA controller,
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unless you are lucky and all the important components on
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a new VGA controller card are interconnected in the same way as an
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existing entry, adding a new entry requires adding new internal
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types to
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.IR vga (8).
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Fortunately, the unit of variety
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has, for the most part, shifted from
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individual components to entire
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video chipsets.
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Thus in lucky cases all that is necessary
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is the addition of another
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.B 0xNNNNN=
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line to the entry for the controller.
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This is particularly true in the case
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of the ATI Mach 64 and the S3 Virge.
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.PP
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If you need to actually add support
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for a controller with a different chipset,
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you will need the data sheets for the VGA controller
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as well as any RAMDAC or clock generator
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(these are commonly integrated into the controller).
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You will also need to know how these components interact.
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For example, a common combination is an S3 86C928 VGA chip with
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an ICD2061A clock generator. The ICD2061A is usually loaded by clocking
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a serial bit-stream out of one of the 86C928 registers.
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Similarly, the RAMDAC may have an internal clock-doubler and/or
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pixel-multiplexing modes, in which case both the clock generator and
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VGA chip must be programmed accordingly.
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Hardware acceleration for rectangle fills
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and block copies is provided in the kernel;
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writing code to handle this is necessary
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to achieve reasonable performance at high
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pixel depths.
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