20ea113790
This makes vmap()/vunmap() take a vlong size argument, and change the type of Pci.mem[].size to vlong as well. Even if vmap() wont support large mappings, it is nice to get the original unruncated value for error checking. pc64 needs a bigger VMAP window, as system76 pangolin puts the framebuffer at a physical address > 512GB.
184 lines
5.5 KiB
C
184 lines
5.5 KiB
C
/*
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* Memory and machine-specific definitions. Used in C and assembler.
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*/
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#define KiB 1024u /* Kibi 0x0000000000000400 */
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#define MiB 1048576u /* Mebi 0x0000000000100000 */
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#define GiB 1073741824u /* Gibi 000000000040000000 */
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#define TiB 1099511627776ull /* Tebi 0x0000010000000000 */
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#define PiB 1125899906842624ull /* Pebi 0x0004000000000000 */
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#define EiB 1152921504606846976ull /* Exbi 0x1000000000000000 */
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#define MIN(a, b) ((a) < (b)? (a): (b))
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#define MAX(a, b) ((a) > (b)? (a): (b))
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#define ALIGNED(p, a) (!(((uintptr)(p)) & ((a)-1)))
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/*
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* Sizes
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*/
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#define BI2BY 8 /* bits per byte */
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#define BI2WD 32 /* bits per word */
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#define BY2WD 8 /* bytes per word */
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#define BY2V 8 /* bytes per double word */
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#define BY2PG (0x1000ull) /* bytes per page */
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#define WD2PG (BY2PG/BY2WD) /* words per page */
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#define PGSHIFT 12 /* log(BY2PG) */
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#define ROUND(s, sz) (((s)+((sz)-1))&~((sz)-1))
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#define PGROUND(s) ROUND(s, BY2PG)
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#define BLOCKALIGN 8
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#define FPalign 64
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#define MAXMACH 128 /* max # cpus system can run */
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#define KSTACK (16*KiB) /* Size of Proc kernel stack */
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/*
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* Time
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*/
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#define HZ (100) /* clock frequency */
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#define MS2HZ (1000/HZ) /* millisec per clock tick */
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#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
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/*
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* Address spaces. User:
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*/
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#define UTZERO (0x0000000000200000ull) /* first address in user text */
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#define UADDRMASK (0x00007fffffffffffull) /* canonical address mask */
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#define USTKTOP (0x00007ffffffff000ull)
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#define USTKSIZE (16*MiB) /* size of user stack */
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/*
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* Address spaces. Kernel, sorted by address.
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*/
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#define KZERO (0xffffffff80000000ull)
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#define KTZERO (KZERO+1*MiB+64*KiB)
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#define VMAP (0xfffffe8000000000ull)
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#define VMAPSIZE (1024ull*GiB)
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#define KMAP (0xfffffe0000000000ull)
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#define KMAPSIZE (2*MiB)
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/*
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* Fundamental addresses
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*/
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#define CONFADDR (KZERO+0x1200ull) /* info passed from boot loader */
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#define APBOOTSTRAP (KZERO+0x7000ull) /* AP bootstrap code */
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#define IDTADDR (KZERO+0x10000ull) /* idt */
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#define REBOOTADDR (0x11000) /* reboot code - physical address */
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#define CPU0PML4 (KZERO+0x13000ull)
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#define CPU0PDP (KZERO+0x14000ull)
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#define CPU0PD0 (KZERO+0x15000ull) /* KZERO */
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#define CPU0PD1 (KZERO+0x16000ull) /* KZERO+1GB */
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#define CPU0GDT (KZERO+0x17000ull) /* bootstrap processor GDT */
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#define CPU0MACH (KZERO+0x18000ull) /* Mach for bootstrap processor */
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#define CPU0END (CPU0MACH+MACHSIZE)
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#define MACHSIZE (2*KSTACK)
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/*
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* Where configuration info is left for the loaded programme.
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* There are 24064 bytes available at CONFADDR.
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*/
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#define BOOTLINE ((char*)CONFADDR)
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#define BOOTLINELEN 64
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#define BOOTARGS ((char*)(CONFADDR+BOOTLINELEN))
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#define BOOTARGSLEN (0x6000-0x200-BOOTLINELEN)
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/*
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* known x86 segments (in GDT) and their selectors
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*/
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#define NULLSEG 0 /* null segment */
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#define KESEG 1 /* kernel executable */
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#define KDSEG 2 /* kernel data */
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#define UE32SEG 3 /* user executable 32bit */
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#define UDSEG 4 /* user data/stack */
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#define UESEG 5 /* user executable 64bit */
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#define TSSSEG 8 /* task segment (two descriptors) */
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#define NGDT 10 /* number of GDT entries required */
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#define SELGDT (0<<2) /* selector is in gdt */
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#define SELLDT (1<<2) /* selector is in ldt */
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#define SELECTOR(i, t, p) (((i)<<3) | (t) | (p))
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#define NULLSEL SELECTOR(NULLSEG, SELGDT, 0)
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#define KDSEL NULLSEL
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#define KESEL SELECTOR(KESEG, SELGDT, 0)
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#define UE32SEL SELECTOR(UE32SEG, SELGDT, 3)
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#define UDSEL SELECTOR(UDSEG, SELGDT, 3)
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#define UESEL SELECTOR(UESEG, SELGDT, 3)
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#define TSSSEL SELECTOR(TSSSEG, SELGDT, 0)
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/*
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* fields in segment descriptors
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*/
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#define SEGDATA (0x10<<8) /* data/stack segment */
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#define SEGEXEC (0x18<<8) /* executable segment */
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#define SEGTSS (0x9<<8) /* TSS segment */
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#define SEGCG (0x0C<<8) /* call gate */
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#define SEGIG (0x0E<<8) /* interrupt gate */
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#define SEGTG (0x0F<<8) /* trap gate */
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#define SEGLDT (0x02<<8) /* local descriptor table */
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#define SEGTYPE (0x1F<<8)
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#define SEGP (1<<15) /* segment present */
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#define SEGPL(x) ((x)<<13) /* priority level */
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#define SEGB (1<<22) /* granularity 1==4k (for expand-down) */
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#define SEGD (1<<22) /* default 1==32bit (for code) */
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#define SEGE (1<<10) /* expand down */
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#define SEGW (1<<9) /* writable (for data/stack) */
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#define SEGR (1<<9) /* readable (for code) */
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#define SEGL (1<<21) /* 64 bit */
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#define SEGG (1<<23) /* granularity 1==4k (for other) */
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/*
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* virtual MMU
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*/
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#define PTEMAPMEM (1ull*MiB)
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#define PTEPERTAB (PTEMAPMEM/BY2PG)
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#define SEGMAPSIZE 65536
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#define SSEGMAPSIZE 16
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#define PPN(x) ((x)&~(1ull<<63 | BY2PG-1))
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/*
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* physical MMU
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*/
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#define PTEVALID (1ull<<0)
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#define PTEWT (1ull<<3)
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#define PTEUNCACHED (1ull<<4)
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#define PTECACHED (0ull<<4)
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#define PTEWRITE (1ull<<1)
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#define PTERONLY (0ull<<1)
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#define PTEKERNEL (0ull<<2)
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#define PTEUSER (1ull<<2)
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#define PTESIZE (1ull<<7)
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#define PTEGLOBAL (1ull<<8)
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#define PTENOEXEC ((uvlong)m->havenx<<63)
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/*
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* Hierarchical Page Tables.
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* For example, traditional IA-32 paging structures have 2 levels,
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* level 1 is the PD, and level 0 the PT pages; with IA-32e paging,
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* level 3 is the PML4(!), level 2 the PDP, level 1 the PD,
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* and level 0 the PT pages. The PTLX macro gives an index into the
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* page-table page at level 'l' for the virtual address 'v'.
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*/
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#define PTSZ (4*KiB) /* page table page size */
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#define PTSHIFT 9 /* */
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#define PTLX(v, l) (((v)>>(((l)*PTSHIFT)+PGSHIFT)) & ((1<<PTSHIFT)-1))
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#define PGLSZ(l) (1ull<<(((l)*PTSHIFT)+PGSHIFT))
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#define getpgcolor(a) 0
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/* PAT entry used for write combining */
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#define PATWC 7
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#define RMACH R15 /* m-> */
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#define RUSER R14 /* up-> */
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