672 lines
13 KiB
C
672 lines
13 KiB
C
/*
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* sheevaplug nand flash driver
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*
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* for now separate from (inferno's) os/port/flashnand.c because the flash
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* seems newer, and has different commands, but that is nand-chip specific,
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* not sheevaplug-specific. they should be merged in future.
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*
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* the sheevaplug has a hynix 4gbit flash chip: hy27uf084g2m.
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* 2048 byte pages, with 64 spare bytes each; erase block size is 128k.
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*
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* it has a "glueless" interface, at 0xf9000000. that's the address
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* of the data register. the command and address registers are those
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* or'ed with 1 and 2 respectively.
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*
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* linux uses this layout for the nand flash (from address 0 onwards):
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* 1mb for u-boot
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* 4mb for kernel
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* 507mb for file system
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*
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* this is not so relevant here except for ecc. the first two areas
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* (u-boot and kernel) are expected to have 4-bit ecc per 512 bytes
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* (but calculated from last byte to first), bad erase blocks skipped.
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* the file system area has 1-bit ecc per 256 bytes.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/flashif.h"
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#include "../port/nandecc.h"
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enum {
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Debug = 0,
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Nopage = ~0ul, /* cache is empty */
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/* vendors */
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Hynix = 0xad,
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Samsung = 0xec,
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/* chips */
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Hy27UF084G2M = 0xdc,
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NandActCEBoot = 1<<1,
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};
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typedef struct Nandreg Nandreg;
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typedef struct Nandtab Nandtab;
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typedef struct Cache Cache;
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struct Nandreg { /* hw registers */
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ulong rdparms;
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ulong wrparms;
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uchar _pad0[0x70 - 0x20];
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ulong ctl;
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};
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struct Nandtab {
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int vid;
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int did;
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vlong size;
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char* name;
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};
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struct Cache {
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Flash *flif;
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ulong pageno;
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ulong pgsize; /* r->pagesize */
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char *page; /* of pgsize bytes */
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};
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enum {
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/* commands */
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Readstatus = 0x70,
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Readid = 0x90, /* needs 1 0-address write */
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Resetf = 0xff,
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/*
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* needs 5 address writes followed by Readstart,
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* Readstartcache or Restartcopy.
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*/
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Read = 0x00,
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Readstart = 0x30,
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Readstartcache = 0x31,
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Readstartcopy = 0x35,
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/* after Readstartcache, to stop reading next pages */
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Readstopcache = 0x34,
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/* needs 5 address writes, the data, and -start or -cache */
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Program = 0x80,
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Programstart = 0x10,
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Programcache = 0x15,
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Copyback = 0x85, /* followed by Programstart */
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/* 3 address writes for block followed by Erasestart */
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Erase = 0x60,
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Erasestart = 0xd0,
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Randomread = 0x85,
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Randomwrite = 0x05,
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Randomwritestart= 0xe0,
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/* status bits */
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SFail = 1<<0,
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SCachefail = 1<<1,
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SIdle = 1<<5, /* doesn't seem to come on ever */
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SReady = 1<<6,
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SNotprotected = 1<<7,
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Srdymask = SReady, /* was SIdle|SReady */
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};
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Nandtab nandtab[] = {
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{Hynix, Hy27UF084G2M, 512*MB, "Hy27UF084G2M"},
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{Samsung, 0xdc, 512*MB, "Samsung 2Gb"},
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};
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static Cache cache;
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static void
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nandcmd(Flash *f, uchar b)
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{
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uchar *p = (uchar *)((ulong)f->addr|1);
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*p = b;
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coherence();
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}
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static void
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nandaddr(Flash *f, uchar b)
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{
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uchar *p = (uchar *)((ulong)f->addr|2);
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*p = b;
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coherence();
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}
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static uchar
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nandread(Flash *f)
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{
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return *(uchar *)f->addr;
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}
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static void
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nandreadn(Flash *f, uchar *buf, long n)
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{
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uchar *p = f->addr;
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while(n-- > 0)
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*buf++ = *p;
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}
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static void
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nandwrite(Flash *f, uchar b)
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{
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*(uchar *)f->addr = b;
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coherence();
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}
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static void
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nandwriten(Flash *f, uchar *buf, long n)
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{
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uchar *p = f->addr;
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while(n-- > 0)
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*p = *buf++;
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coherence();
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}
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static void
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nandclaim(Flash*)
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{
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Nandreg *nand = (Nandreg*)soc.nand;
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nand->ctl |= NandActCEBoot;
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coherence();
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}
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static void
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nandunclaim(Flash*)
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{
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Nandreg *nand = (Nandreg*)soc.nand;
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nand->ctl &= ~NandActCEBoot;
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coherence();
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}
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void mmuidmap(uintptr phys, int mbs);
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Nandtab *
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findflash(Flash *f, uintptr pa, uchar *id4p)
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{
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int i;
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ulong sts;
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uchar maker, device, id3, id4;
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Nandtab *chip;
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mmuidmap(pa, 16);
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f->addr = (void *)pa;
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/* make sure controller is idle */
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nandclaim(f);
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nandcmd(f, Resetf);
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nandunclaim(f);
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nandclaim(f);
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nandcmd(f, Readstatus);
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sts = nandread(f);
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nandunclaim(f);
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for (i = 10; i > 0 && !(sts & SReady); i--) {
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delay(50);
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nandclaim(f);
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nandcmd(f, Readstatus);
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sts = nandread(f);
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nandunclaim(f);
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}
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if(!(sts & SReady))
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return nil;
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nandclaim(f);
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nandcmd(f, Readid);
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nandaddr(f, 0);
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maker = nandread(f);
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device = nandread(f);
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id3 = nandread(f);
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USED(id3);
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id4 = nandread(f);
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nandunclaim(f);
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if (id4p)
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*id4p = id4;
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for(i = 0; i < nelem(nandtab); i++) {
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chip = &nandtab[i];
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if(chip->vid == maker && chip->did == device)
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return chip;
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}
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return nil;
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}
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int
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flashat(Flash *f, uintptr pa)
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{
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return findflash(f, pa, nil) != nil;
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}
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static int
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idchip(Flash *f)
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{
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uchar id4;
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Flashregion *r;
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Nandtab *chip;
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static int blocksizes[4] = { 64*1024, 128*1024, 256*1024, 0 };
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static int pagesizes[4] = { 1024, 2*1024, 0, 0 };
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static int spares[2] = { 8, 16 }; /* per 512 bytes */
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f->id = 0;
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f->devid = 0;
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f->width = 1;
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chip = findflash(f, (uintptr)f->addr, &id4);
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if (chip == nil)
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return -1;
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f->id = chip->vid;
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f->devid = chip->did;
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f->size = chip->size;
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f->width = 1;
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f->nr = 1;
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r = &f->regions[0];
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r->pagesize = pagesizes[id4 & MASK(2)];
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r->erasesize = blocksizes[(id4 >> 4) & MASK(2)];
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if (r->pagesize == 0 || r->erasesize == 0) {
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iprint("flashkw: bogus flash sizes\n");
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return -1;
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}
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r->n = f->size / r->erasesize;
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r->start = 0;
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r->end = f->size;
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assert(ispow2(r->pagesize));
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r->pageshift = log2(r->pagesize);
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assert(ispow2(r->erasesize));
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r->eraseshift = log2(r->erasesize);
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assert(r->eraseshift >= r->pageshift);
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if (cache.page == nil) {
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cache.pgsize = r->pagesize;
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cache.page = smalloc(r->pagesize);
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}
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r->spares = r->pagesize / 512 * spares[(id4 >> 2) & 1];
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print("#F0: kwnand: %s %,lud bytes pagesize %lud erasesize %,lud"
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" spares per page %lud\n", chip->name, f->size, r->pagesize,
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r->erasesize, r->spares);
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return 0;
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}
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static int
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ctlrwait(Flash *f)
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{
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int sts, cnt;
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nandclaim(f);
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for (;;) {
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nandcmd(f, Readstatus);
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for(cnt = 100; cnt > 0 && (nandread(f) & Srdymask) != Srdymask;
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cnt--)
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microdelay(50);
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nandcmd(f, Readstatus);
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sts = nandread(f);
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if((sts & Srdymask) == Srdymask)
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break;
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print("flashkw: flash ctlr busy, sts %#ux: resetting\n", sts);
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nandcmd(f, Resetf);
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}
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nandunclaim(f);
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return 0;
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}
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static int
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erasezone(Flash *f, Flashregion *r, ulong offset)
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{
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int i;
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ulong page, block;
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uchar s;
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if (Debug) {
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print("flashkw: erasezone: offset %#lux, region nblocks %d,"
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" start %#lux, end %#lux\n", offset, r->n, r->start,
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r->end);
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print(" erasesize %lud, pagesize %lud\n",
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r->erasesize, r->pagesize);
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}
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assert(r->erasesize != 0);
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if(offset & (r->erasesize - 1)) {
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print("flashkw: erase offset %lud not block aligned\n", offset);
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return -1;
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}
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page = offset >> r->pageshift;
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block = page >> (r->eraseshift - r->pageshift);
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if (Debug)
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print("flashkw: erase: block %#lux\n", block);
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/* make sure controller is idle */
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if(ctlrwait(f) < 0) {
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print("flashkw: erase: flash busy\n");
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return -1;
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}
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/* start erasing */
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nandclaim(f);
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nandcmd(f, Erase);
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nandaddr(f, page>>0);
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nandaddr(f, page>>8);
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nandaddr(f, page>>16);
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nandcmd(f, Erasestart);
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/* invalidate cache on any erasure (slight overkill) */
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cache.pageno = Nopage;
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/* have to wait until flash is done. typically ~2ms */
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delay(1);
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nandcmd(f, Readstatus);
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for(i = 0; i < 100; i++) {
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s = nandread(f);
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if(s & SReady) {
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nandunclaim(f);
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if(s & SFail) {
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print("flashkw: erase: failed, block %#lux\n",
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block);
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return -1;
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}
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return 0;
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}
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microdelay(50);
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}
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print("flashkw: erase timeout, block %#lux\n", block);
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nandunclaim(f);
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return -1;
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}
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static void
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flcachepage(Flash *f, ulong page, uchar *buf)
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{
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Flashregion *r = &f->regions[0];
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assert(cache.pgsize == r->pagesize);
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cache.flif = f;
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cache.pageno = page;
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/* permit i/o directly to or from the cache */
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if (buf != (uchar *)cache.page)
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memmove(cache.page, buf, cache.pgsize);
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}
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static int
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write1page(Flash *f, ulong offset, void *buf)
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{
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int i;
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ulong page, v;
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uchar s;
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uchar *eccp, *p;
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Flashregion *r = &f->regions[0];
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static uchar *oob;
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if (oob == nil)
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oob = smalloc(r->spares);
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page = offset >> r->pageshift;
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if (Debug)
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print("flashkw: write nand offset %#lux page %#lux\n",
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offset, page);
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if(offset & (r->pagesize - 1)) {
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print("flashkw: write offset %lud not page aligned\n", offset);
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return -1;
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}
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p = buf;
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memset(oob, 0xff, r->spares);
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assert(r->spares >= 24);
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eccp = oob + r->spares - 24;
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for(i = 0; i < r->pagesize / 256; i++) {
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v = nandecc(p);
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*eccp++ = v>>8;
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*eccp++ = v>>0;
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*eccp++ = v>>16;
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p += 256;
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}
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if(ctlrwait(f) < 0) {
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print("flashkw: write: nand not ready & idle\n");
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return -1;
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}
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/* write, only whole pages for now, no sub-pages */
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nandclaim(f);
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nandcmd(f, Program);
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nandaddr(f, 0);
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nandaddr(f, 0);
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nandaddr(f, page>>0);
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nandaddr(f, page>>8);
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nandaddr(f, page>>16);
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nandwriten(f, buf, r->pagesize);
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nandwriten(f, oob, r->spares);
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nandcmd(f, Programstart);
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microdelay(100);
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nandcmd(f, Readstatus);
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for(i = 0; i < 100; i++) {
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s = nandread(f);
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if(s & SReady) {
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nandunclaim(f);
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if(s & SFail) {
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print("flashkw: write failed, page %#lux\n",
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page);
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return -1;
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}
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return 0;
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}
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microdelay(10);
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}
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nandunclaim(f);
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flcachepage(f, page, buf);
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print("flashkw: write timeout for page %#lux\n", page);
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return -1;
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}
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static int
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read1page(Flash *f, ulong offset, void *buf)
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{
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int i;
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ulong addr, page, w;
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uchar *eccp, *p;
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Flashregion *r = &f->regions[0];
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static uchar *oob;
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if (oob == nil)
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oob = smalloc(r->spares);
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assert(r->pagesize != 0);
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addr = offset & (r->pagesize - 1);
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page = offset >> r->pageshift;
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if(addr != 0) {
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print("flashkw: read1page: read addr %#lux:"
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" must read aligned page\n", addr);
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return -1;
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}
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/* satisfy request from cache if possible */
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if (f == cache.flif && page == cache.pageno &&
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r->pagesize == cache.pgsize) {
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memmove(buf, cache.page, r->pagesize);
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return 0;
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}
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if (Debug)
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print("flashkw: read offset %#lux addr %#lux page %#lux\n",
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offset, addr, page);
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nandclaim(f);
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nandcmd(f, Read);
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nandaddr(f, addr>>0);
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nandaddr(f, addr>>8);
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nandaddr(f, page>>0);
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nandaddr(f, page>>8);
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nandaddr(f, page>>16);
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nandcmd(f, Readstart);
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microdelay(50);
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nandreadn(f, buf, r->pagesize);
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nandreadn(f, oob, r->spares);
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nandunclaim(f);
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/* verify/correct data. last 8*3 bytes is ecc, per 256 bytes. */
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p = buf;
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assert(r->spares >= 24);
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eccp = oob + r->spares - 24;
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for(i = 0; i < r->pagesize / 256; i++) {
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w = eccp[0] << 8 | eccp[1] << 0 | eccp[2] << 16;
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eccp += 3;
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switch(nandecccorrect(p, nandecc(p), &w, 1)) {
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case NandEccErrorBad:
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print("(page %d)\n", i);
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return -1;
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case NandEccErrorOneBit:
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case NandEccErrorOneBitInEcc:
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print("(page %d)\n", i);
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/* fall through */
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case NandEccErrorGood:
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break;
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}
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p += 256;
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}
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flcachepage(f, page, buf);
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return 0;
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}
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/*
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* read a page at offset into cache, copy fragment from buf into it
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* at pagoff, and rewrite that page.
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*/
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static int
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rewrite(Flash *f, ulong offset, ulong pagoff, void *buf, ulong size)
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{
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if (read1page(f, offset, cache.page) < 0)
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return -1;
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memmove(&cache.page[pagoff], buf, size);
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return write1page(f, offset, cache.page);
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}
|
|
|
|
/* there are no alignment constraints on offset, buf, nor n */
|
|
static int
|
|
write(Flash *f, ulong offset, void *buf, long n)
|
|
{
|
|
uint un, frag, pagoff;
|
|
ulong pgsize;
|
|
uchar *p;
|
|
Flashregion *r = &f->regions[0];
|
|
|
|
if(n <= 0)
|
|
panic("flashkw: write: non-positive count %ld", n);
|
|
un = n;
|
|
assert(r->pagesize != 0);
|
|
pgsize = r->pagesize;
|
|
|
|
/* if a partial first page exists, update the first page with it. */
|
|
p = buf;
|
|
pagoff = offset % pgsize;
|
|
if (pagoff != 0) {
|
|
frag = pgsize - pagoff;
|
|
if (frag > un) /* might not extend to end of page */
|
|
frag = un;
|
|
if (rewrite(f, offset - pagoff, pagoff, p, frag) < 0)
|
|
return -1;
|
|
offset += frag;
|
|
p += frag;
|
|
un -= frag;
|
|
}
|
|
|
|
/* copy whole pages */
|
|
while (un >= pgsize) {
|
|
if (write1page(f, offset, p) < 0)
|
|
return -1;
|
|
offset += pgsize;
|
|
p += pgsize;
|
|
un -= pgsize;
|
|
}
|
|
|
|
/* if a partial last page exists, update the last page with it. */
|
|
if (un > 0)
|
|
return rewrite(f, offset, 0, p, un);
|
|
return 0;
|
|
}
|
|
|
|
/* there are no alignment constraints on offset, buf, nor n */
|
|
static int
|
|
read(Flash *f, ulong offset, void *buf, long n)
|
|
{
|
|
uint un, frag, pagoff;
|
|
ulong pgsize;
|
|
uchar *p;
|
|
Flashregion *r = &f->regions[0];
|
|
|
|
if(n <= 0)
|
|
panic("flashkw: read: non-positive count %ld", n);
|
|
un = n;
|
|
assert(r->pagesize != 0);
|
|
pgsize = r->pagesize;
|
|
|
|
/* if partial 1st page, read it into cache & copy fragment to buf */
|
|
p = buf;
|
|
pagoff = offset % pgsize;
|
|
if (pagoff != 0) {
|
|
frag = pgsize - pagoff;
|
|
if (frag > un) /* might not extend to end of page */
|
|
frag = un;
|
|
if (read1page(f, offset - pagoff, cache.page) < 0)
|
|
return -1;
|
|
offset += frag;
|
|
memmove(p, &cache.page[pagoff], frag);
|
|
p += frag;
|
|
un -= frag;
|
|
}
|
|
|
|
/* copy whole pages */
|
|
while (un >= pgsize) {
|
|
if (read1page(f, offset, p) < 0)
|
|
return -1;
|
|
offset += pgsize;
|
|
p += pgsize;
|
|
un -= pgsize;
|
|
}
|
|
|
|
/* if partial last page, read into cache & copy initial fragment to buf */
|
|
if (un > 0) {
|
|
if (read1page(f, offset, cache.page) < 0)
|
|
return -1;
|
|
memmove(p, cache.page, un);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
reset(Flash *f)
|
|
{
|
|
if(f->data != nil)
|
|
return 1;
|
|
f->write = write;
|
|
f->read = read;
|
|
f->eraseall = nil;
|
|
f->erasezone = erasezone;
|
|
f->suspend = nil;
|
|
f->resume = nil;
|
|
f->sort = "nand";
|
|
cache.pageno = Nopage;
|
|
return idchip(f);
|
|
}
|
|
|
|
void
|
|
flashkwlink(void)
|
|
{
|
|
addflashcard("nand", reset);
|
|
}
|