b29d5ac7b1
this is the the initial sync of charles forsyths plan9 c compiler suite from http://bitbucket.org/plan9-from-bell-labs/9-cc at changeset version 54:65fb8bb56c59
518 lines
6.4 KiB
C
518 lines
6.4 KiB
C
/*
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* arm64
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*/
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#define NSNAME 8
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#define NSYM 50
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#define NREG 32
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#define NOPROF (1<<0)
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#define DUPOK (1<<1)
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#define REGRET 0
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#define REGARG 0
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/* R1 to R7 are potential parameter/return registers */
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#define REGIRL 8 /* indirect result location (TO DO) */
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/* compiler allocates R9 up as temps */
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/* compiler allocates register variables R10 up */
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#define REGMIN 9
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#define REGMAX 15
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#define REGIP0 16
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#define REGIP1 17
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#define REGTMP REGIP1
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/* compiler allocates external registers R27 down */
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#define REGEXT 27
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#define REGSB 28
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#define REGFP 29
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#define REGLINK 30
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#define REGSP 31
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#define REGZERO 31
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#define NFREG 32
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#define FREGRET 0
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#define FREGMIN 7
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#define FREGEXT 15
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/* compiler allocates register variables F0 up */
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/* compiler allocates external registers F15 down */
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enum as
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{
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AXXX,
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AADC,
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AADCS,
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AADCSW,
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AADCW,
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AADD,
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AADDS,
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AADDSW,
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AADDW,
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AADR,
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AADRP,
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AAND,
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AANDS,
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AANDSW,
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AANDW,
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AASR,
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AASRW,
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AAT,
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AB,
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ABFI,
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ABFIW,
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ABFM,
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ABFMW,
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ABFXIL,
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ABFXILW,
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ABIC,
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ABICS,
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ABICSW,
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ABICW,
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ABL,
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ABRK,
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ACBNZ,
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ACBNZW,
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ACBZ,
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ACBZW,
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ACCMN,
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ACCMNW,
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ACCMP,
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ACCMPW,
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ACINC,
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ACINCW,
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ACINV,
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ACINVW,
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ACLREX,
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ACLS,
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ACLSW,
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ACLZ,
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ACLZW,
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ACMN,
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ACMNW,
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ACMP,
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ACMPW,
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ACNEG,
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ACNEGW,
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ACRC32B,
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ACRC32CB,
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ACRC32CH,
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ACRC32CW,
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ACRC32CX,
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ACRC32H,
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ACRC32W,
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ACRC32X,
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ACSEL,
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ACSELW,
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ACSET,
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ACSETM,
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ACSETMW,
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ACSETW,
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ACSINC,
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ACSINCW,
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ACSINV,
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ACSINVW,
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ACSNEG,
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ACSNEGW,
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ADC,
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ADCPS1,
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ADCPS2,
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ADCPS3,
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ADMB,
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ADRPS,
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ADSB,
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AEON,
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AEONW,
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AEOR,
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AEORW,
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AERET,
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AEXTR,
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AEXTRW,
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AHINT,
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AHLT,
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AHVC,
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AIC,
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AISB,
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ALDAR,
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ALDARB,
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ALDARH,
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ALDARW,
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ALDAXP,
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ALDAXPW,
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ALDAXR,
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ALDAXRB,
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ALDAXRH,
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ALDAXRW,
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ALDXR,
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ALDXRB,
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ALDXRH,
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ALDXRW,
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ALDXP,
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ALDXPW,
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ALSL,
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ALSLW,
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ALSR,
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ALSRW,
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AMADD,
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AMADDW,
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AMNEG,
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AMNEGW,
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AMOVK,
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AMOVKW,
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AMOVN,
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AMOVNW,
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AMOVZ,
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AMOVZW,
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AMRS,
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AMSR,
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AMSUB,
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AMSUBW,
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AMUL,
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AMULW,
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AMVN,
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AMVNW,
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ANEG,
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ANEGS,
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ANEGSW,
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ANEGW,
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ANGC,
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ANGCS,
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ANGCSW,
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ANGCW,
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ANOP,
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AORN,
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AORNW,
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AORR,
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AORRW,
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APRFM,
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APRFUM,
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ARBIT,
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ARBITW,
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AREM,
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AREMW,
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ARET,
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AREV,
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AREV16,
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AREV16W,
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AREV32,
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AREVW,
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AROR,
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ARORW,
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ASBC,
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ASBCS,
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ASBCSW,
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ASBCW,
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ASBFIZ,
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ASBFIZW,
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ASBFM,
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ASBFMW,
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ASBFX,
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ASBFXW,
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ASDIV,
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ASDIVW,
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ASEV,
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ASEVL,
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ASMADDL,
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ASMC,
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ASMNEGL,
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ASMSUBL,
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ASMULH,
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ASMULL,
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ASTXR,
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ASTXRB,
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ASTXRH,
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ASTXP,
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ASTXPW,
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ASTXRW,
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ASTLP,
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ASTLPW,
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ASTLR,
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ASTLRB,
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ASTLRH,
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ASTLRW,
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ASTLXP,
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ASTLXPW,
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ASTLXR,
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ASTLXRB,
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ASTLXRH,
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ASTLXRW,
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ASUB,
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ASUBS,
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ASUBSW,
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ASUBW,
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ASVC,
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ASXTB,
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ASXTBW,
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ASXTH,
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ASXTHW,
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ASXTW,
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ASYS,
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ASYSL,
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ATBNZ,
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ATBZ,
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ATLBI,
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ATST,
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ATSTW,
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AUBFIZ,
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AUBFIZW,
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AUBFM,
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AUBFMW,
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AUBFX,
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AUBFXW,
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AUDIV,
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AUDIVW,
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AUMADDL,
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AUMNEGL,
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AUMSUBL,
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AUMULH,
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AUMULL,
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AUREM,
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AUREMW,
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AUXTB,
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AUXTH,
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AUXTW,
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AUXTBW,
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AUXTHW,
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AWFE,
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AWFI,
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AYIELD,
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AMOVB,
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AMOVBU,
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AMOVH,
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AMOVHU,
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AMOVW,
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AMOVWU,
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AMOV,
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AMOVNP,
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AMOVNPW,
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AMOVP,
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AMOVPD,
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AMOVPQ,
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AMOVPS,
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AMOVPSW,
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AMOVPW,
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/*
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* Do not reorder or fragment the conditional branch
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* opcodes, or the predication code will break
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*/
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ABEQ,
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ABNE,
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ABCS,
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ABHS,
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ABCC,
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ABLO,
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ABMI,
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ABPL,
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ABVS,
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ABVC,
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ABHI,
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ABLS,
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ABGE,
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ABLT,
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ABGT,
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ABLE,
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AFABSD,
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AFABSS,
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AFADDD,
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AFADDS,
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AFCCMPD,
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AFCCMPED,
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AFCCMPS,
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AFCCMPES,
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AFCMPD,
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AFCMPED,
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AFCMPES,
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AFCMPS,
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AFCVTSD,
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AFCVTDS,
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AFCVTZSD,
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AFCVTZSDW,
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AFCVTZSS,
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AFCVTZSSW,
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AFCVTZUD,
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AFCVTZUDW,
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AFCVTZUS,
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AFCVTZUSW,
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AFDIVD,
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AFDIVS,
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AFMOVD,
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AFMOVS,
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AFMULD,
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AFMULS,
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AFNEGD,
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AFNEGS,
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AFSQRTD,
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AFSQRTS,
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AFSUBD,
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AFSUBS,
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ASCVTFD,
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ASCVTFS,
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ASCVTFWD,
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ASCVTFWS,
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AUCVTFD,
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AUCVTFS,
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AUCVTFWD,
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AUCVTFWS,
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ATEXT,
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ADATA,
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AGLOBL,
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AHISTORY,
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ANAME,
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AWORD,
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ADYNT,
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AINIT,
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ABCASE,
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ACASE,
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ADWORD,
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ASIGNAME,
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AGOK,
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ARETURN,
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AEND,
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AFCSELS,
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AFCSELD,
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AFMAXS,
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AFMINS,
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AFMAXD,
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AFMIND,
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AFMAXNMS,
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AFMAXNMD,
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AFNMULS,
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AFNMULD,
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AFRINTNS,
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AFRINTND,
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AFRINTPS,
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AFRINTPD,
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AFRINTMS,
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AFRINTMD,
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AFRINTZS,
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AFRINTZD,
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AFRINTAS,
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AFRINTAD,
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AFRINTXS,
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AFRINTXD,
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AFRINTIS,
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AFRINTID,
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AFMADDS,
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AFMADDD,
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AFMSUBS,
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AFMSUBD,
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AFNMADDS,
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AFNMADDD,
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AFNMSUBS,
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AFNMSUBD,
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AFMINNMS,
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AFMINNMD,
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AFCVTDH,
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AFCVTHS,
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AFCVTHD,
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AFCVTSH,
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AAESD,
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AAESE,
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AAESIMC,
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AAESMC,
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ASHA1C,
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ASHA1H,
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ASHA1M,
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ASHA1P,
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ASHA1SU0,
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ASHA1SU1,
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ASHA256H,
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ASHA256H2,
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ASHA256SU0,
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ASHA256SU1,
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ALAST,
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};
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/* form offset parameter to SYS; special register number */
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#define SYSARG5(op0,op1,Cn,Cm,op2) ((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5)
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#define SYSARG4(op1,Cn,Cm,op2) SYSARG5(0,op1,Cn,Cm,op2)
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/* type/name */
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enum
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{
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D_GOK = 0,
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D_NONE,
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/* name */
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D_EXTERN,
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D_STATIC,
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D_AUTO,
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D_PARAM,
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/* type */
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D_BRANCH,
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D_OREG, /* offset(reg) */
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D_XPRE, /* offset(reg)! - pre-indexed */
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D_XPOST, /* (reg)offset! - post-indexed */
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D_CONST, /* 32-bit constant */
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D_DCONST, /* 64-bit constant */
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D_FCONST, /* floating-point constant */
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D_SCONST, /* short string constant */
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D_REG, /* Rn = Wn or Xn depending on op */
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D_SP, /* distinguish REGSP from REGZERO */
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D_FREG, /* Fn = Sn or Dn depending on op */
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D_VREG, /* Vn = SIMD register */
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D_SPR, /* special processor register */
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D_FILE,
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D_OCONST, /* absolute address constant (unused) */
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D_FILE1,
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D_SHIFT, /* Rm{, ashift #imm} */
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D_PAIR, /* pair of gprs */
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D_ADDR, /* address constant (dynamic loading) */
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D_ADRP, /* pc-relative addressing, page */
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D_ADRLO, /* low-order 12 bits of external reference */
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D_EXTREG, /* Rm{, ext #imm} */
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D_ROFF, /* register offset Rn+ext(Rm)<<s */
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D_COND, /* condition EQ, NE, etc */
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D_VLANE, /* Vn lane */
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D_VSET, /* set of Vn */
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/* offset iff type is D_SPR */
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D_DAIF = SYSARG5(3,3,4,2,1),
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D_NZCV = SYSARG5(3,3,4,2,0),
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D_FPSR = SYSARG5(3,3,4,4,1),
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D_FPCR = SYSARG5(3,3,4,4,0),
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D_SPSR_EL1 = SYSARG5(3,0,4,0,0),
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D_ELR_EL1 = SYSARG5(3,0,4,0,1),
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D_SPSR_EL2 = SYSARG5(3,4,4,0,0),
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D_ELR_EL2 = SYSARG5(3,4,4,0,1),
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// D_SPSR_EL3 = SYSARG5(3,x,4,x,x),
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// D_ELR_EL3 = SYSARG5(3,x,4,x,x),
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// D_LR_EL0 = SYSARG5(3,x,4,x,x),
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D_CurrentEL = SYSARG5(3,0,4,2,2),
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D_SP_EL0 = SYSARG5(3,0,4,1,0),
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// D_SP_EL1 = SYSARG5(3,x,4,x,x),
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// D_SP_EL2 = SYSARG5(3,x,4,x,x),
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D_SPSel = SYSARG5(3,0,4,2,0),
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// D_SPSR_abt = SYSARG5(3,x,4,x,x),
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// D_SPSR_fiq = SYSARG5(3,x,4,x,x),
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// D_SPSR_ieq = SYSARG5(3,x,4,x,x),
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// D_SPSR_und = SYSARG5(3,x,4,x,x),
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D_DAIFSet = (1<<30)|0,
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D_DAIFClr = (1<<30)|1
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};
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/*
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* this is the ranlib header
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*/
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#define SYMDEF "__.SYMDEF"
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/*
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* this is the simulated IEEE floating point
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*/
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typedef struct Ieee Ieee;
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struct Ieee
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{
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long l; /* contains ls-man 0xffffffff */
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long h; /* contains sign 0x80000000
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exp 0x7ff00000
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ms-man 0x000fffff */
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};
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