2b89cdee02
we want CNTVCT_EL0 to be the same on all cores, so we set the offset the same so it effectively becomes the system counter.
91 lines
3.2 KiB
C
91 lines
3.2 KiB
C
#define MIDR_EL1 SYSREG(3,0,0,0,0)
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#define MPIDR_EL1 SYSREG(3,0,0,0,5)
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#define ID_AA64AFR0_EL1 SYSREG(3,0,0,5,4)
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#define ID_AA64AFR1_EL1 SYSREG(3,0,0,5,5)
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#define ID_AA64DFR0_EL1 SYSREG(3,0,0,5,0)
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#define ID_AA64DFR1_EL1 SYSREG(3,0,0,5,1)
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#define ID_AA64ISAR0_EL1 SYSREG(3,0,0,6,0)
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#define ID_AA64ISAR1_EL1 SYSREG(3,0,0,6,1)
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#define ID_AA64MMFR0_EL1 SYSREG(3,0,0,7,0)
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#define ID_AA64MMFR1_EL1 SYSREG(3,0,0,7,1)
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#define ID_AA64PFR0_EL1 SYSREG(3,0,0,4,0)
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#define ID_AA64PFR1_EL1 SYSREG(3,0,0,4,1)
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#define SCTLR_EL1 SYSREG(3,0,1,0,0)
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#define CPACR_EL1 SYSREG(3,0,1,0,2)
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#define MAIR_EL1 SYSREG(3,0,10,2,0)
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#define TCR_EL1 SYSREG(3,0,2,0,2)
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#define TTBR0_EL1 SYSREG(3,0,2,0,0)
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#define TTBR1_EL1 SYSREG(3,0,2,0,1)
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#define ESR_EL1 SYSREG(3,0,5,2,0)
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#define FAR_EL1 SYSREG(3,0,6,0,0)
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#define VBAR_EL1 SYSREG(3,0,12,0,0)
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#define VTTBR_EL2 SYSREG(3,4,2,1,0)
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#define SP_EL0 SYSREG(3,0,4,1,0)
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#define SP_EL1 SYSREG(3,4,4,1,0)
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#define SP_EL2 SYSREG(3,6,4,1,0)
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#define SCTLR_EL2 SYSREG(3,4,1,0,0)
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#define HCR_EL2 SYSREG(3,4,1,1,0)
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#define MDCR_EL2 SYSREG(3,4,1,1,1)
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#define PMCR_EL0 SYSREG(3,3,9,12,0)
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#define PMCNTENSET SYSREG(3,3,9,12,1)
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#define PMCCNTR_EL0 SYSREG(3,3,9,13,0)
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#define PMUSERENR_EL0 SYSREG(3,3,9,14,0)
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#define CNTPCT_EL0 SYSREG(3,3,14,0,1)
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#define CNTVCT_EL0 SYSREG(3,3,14,0,2)
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#define CNTKCTL_EL1 SYSREG(3,0,14,1,0)
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#define CNTFRQ_EL0 SYSREG(3,3,14,0,0)
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#define CNTP_TVAL_EL0 SYSREG(3,3,14,2,0)
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#define CNTP_CTL_EL0 SYSREG(3,3,14,2,1)
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#define CNTP_CVAL_EL0 SYSREG(3,3,14,2,2)
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#define CNTVOFF_EL2 SYSREG(3,4,14,0,3)
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#define TPIDR_EL0 SYSREG(3,3,13,0,2)
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#define TPIDR_EL1 SYSREG(3,0,13,0,4)
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#define CCSIDR_EL1 SYSREG(3,1,0,0,0)
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#define CSSELR_EL1 SYSREG(3,2,0,0,0)
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#define ACTLR_EL2 SYSREG(3,4,1,0,1)
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#define CPUACTLR_EL1 SYSREG(3,1,15,2,0)
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#define CPUECTLR_EL1 SYSREG(3,1,15,2,1)
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#define CBAR_EL1 SYSREG(3,1,15,3,0)
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#define ICC_AP0R_EL1(m) SYSREG(3,0,12,8,4|(m))
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#define ICC_AP1R_EL1(m) SYSREG(3,0,12,9,0|(m))
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#define ICC_ASGI1R_EL1 SYSREG(3,0,12,11,6)
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#define ICC_BPR0_EL1 SYSREG(3,0,12,8,3)
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#define ICC_BPR1_EL1 SYSREG(3,0,12,12,3)
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#define ICC_CTLR_EL1 SYSREG(3,0,12,12,4)
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#define ICC_DIR_EL1 SYSREG(3,0,12,11,1)
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#define ICC_EOIR0_EL1 SYSREG(3,0,12,8,1)
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#define ICC_EOIR1_EL1 SYSREG(3,0,12,12,1)
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#define ICC_HPPIR0_EL1 SYSREG(3,0,12,8,2)
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#define ICC_HPPIR1_EL1 SYSREG(3,0,12,12,2)
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#define ICC_IAR0_EL1 SYSREG(3,0,12,8,0)
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#define ICC_IAR1_EL1 SYSREG(3,0,12,12,0)
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#define ICC_IGRPEN0_EL1 SYSREG(3,0,12,12,6)
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#define ICC_IGRPEN1_EL1 SYSREG(3,0,12,12,7)
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#define ICC_NMIAR1_EL1 SYSREG(3,0,12,9,5)
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#define ICC_PMR_EL1 SYSREG(3,0,4,6,0)
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#define ICC_RPR_EL1 SYSREG(3,0,12,11,3)
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#define ICC_SGI0R_EL1 SYSREG(3,0,12,11,7)
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#define ICC_SGI1R_EL1 SYSREG(3,0,12,11,5)
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#define ICC_SRE_EL1 SYSREG(3,0,12,12,5)
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/* l.s redefines this for the assembler */
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#define SYSREG(op0,op1,Cn,Cm,op2) ((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5)
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#define OSHLD (0<<2 | 1)
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#define OSHST (0<<2 | 2)
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#define OSH (0<<2 | 3)
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#define NSHLD (1<<2 | 1)
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#define NSHST (1<<2 | 2)
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#define NSH (1<<2 | 3)
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#define ISHLD (2<<2 | 1)
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#define ISHST (2<<2 | 2)
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#define ISH (2<<2 | 3)
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#define LD (3<<2 | 1)
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#define ST (3<<2 | 2)
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#define SY (3<<2 | 3)
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