6f9838a6a5
To avoid a MAXMACH limit of 32 and make txtflush into an array for the bitmap. Provide portable macros for testing and clearing the bits: needtxtflush(), donetxtflush(). On pc/pc64, define inittxtflush()/settxtflush() as no-op macros, avoiding the storage overhead of the txtflush array alltogether.
382 lines
8.2 KiB
C
382 lines
8.2 KiB
C
typedef struct BIOS32si BIOS32si;
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typedef struct BIOS32ci BIOS32ci;
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typedef struct Conf Conf;
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typedef struct Confmem Confmem;
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typedef union FPsave FPsave;
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typedef struct FPx87state FPx87state;
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typedef struct FPssestate FPssestate;
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typedef struct PFPU PFPU;
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typedef struct ISAConf ISAConf;
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typedef struct Label Label;
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typedef struct Lock Lock;
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typedef struct MMU MMU;
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typedef struct Mach Mach;
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typedef struct PCArch PCArch;
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typedef struct Pcidev Pcidev;
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typedef struct PCMmap PCMmap;
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typedef struct PCMslot PCMslot;
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typedef struct Page Page;
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typedef struct PMMU PMMU;
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typedef struct Proc Proc;
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typedef struct Segdesc Segdesc;
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typedef vlong Tval;
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typedef struct Ureg Ureg;
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typedef struct Vctl Vctl;
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#pragma incomplete BIOS32si
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#pragma incomplete Pcidev
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#pragma incomplete Ureg
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#define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */
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/*
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* parameters for sysproc.c
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*/
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#define AOUT_MAGIC (I_MAGIC)
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struct Lock
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{
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ulong key;
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ulong sr;
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uintptr pc;
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Proc *p;
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Mach *m;
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ushort isilock;
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long lockcycles;
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};
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struct Label
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{
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ulong sp;
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ulong pc;
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};
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struct FPx87state /* x87 fp state */
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{
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ushort control;
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ushort r1;
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ushort status;
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ushort r2;
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ushort tag;
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ushort r3;
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ulong pc;
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ushort selector;
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ushort opcode;
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ulong operand;
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ushort oselector;
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ushort r4;
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uchar regs[80]; /* floating point registers */
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};
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struct FPssestate /* SSE fp state */
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{
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ushort fcw; /* control */
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ushort fsw; /* status */
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ushort ftw; /* tag */
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ushort fop; /* opcode */
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ulong fpuip; /* pc */
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ushort cs; /* pc segment */
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ushort rsrvd1; /* reserved */
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ulong fpudp; /* data pointer */
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ushort ds; /* data pointer segment */
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ushort rsrvd2;
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ulong mxcsr; /* MXCSR register state */
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ulong mxcsr_mask; /* MXCSR mask register */
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uchar xregs[480]; /* extended registers */
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};
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union FPsave {
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FPx87state;
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FPssestate;
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};
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struct PFPU
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{
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int fpstate;
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FPsave *fpsave;
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};
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enum
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{
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/* this is a state */
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FPinit= 0,
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FPactive= 1,
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FPinactive= 2,
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/* the following is a bit that can be or'd into the state */
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FPillegal= 0x100,
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};
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struct Confmem
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{
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ulong base;
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ulong npage;
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ulong kbase;
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ulong klimit;
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};
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struct Conf
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{
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ulong nmach; /* processors */
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ulong nproc; /* processes */
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ulong monitor; /* has monitor? */
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ulong npage; /* total physical pages of memory */
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ulong upages; /* user page pool */
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ulong nimage; /* number of page cache image headers */
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ulong nswap; /* number of swap pages */
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int nswppo; /* max # of pageouts per segment pass */
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ulong copymode; /* 0 is copy on write, 1 is copy on reference */
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ulong ialloc; /* max interrupt time allocation in bytes */
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ulong pipeqsize; /* size in bytes of pipe queues */
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int nuart; /* number of uart devices */
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Confmem mem[64]; /* physical memory */
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};
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struct Segdesc
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{
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ulong d0;
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ulong d1;
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};
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/*
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* MMU stuff in proc
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*/
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#define NCOLOR 1
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struct PMMU
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{
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Page* mmupdb; /* page directory base */
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Page* mmufree; /* unused page table pages */
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Page* mmuused; /* used page table pages */
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Page* kmaptable; /* page table used by kmap */
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uint lastkmap; /* last entry used by kmap */
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int nkmap; /* number of current kmaps */
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Segdesc gdt[NPROCSEG]; /* per process descriptors */
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Segdesc *ldt; /* local descriptor table */
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int nldt; /* number of ldt descriptors allocated */
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u32int dr[8]; /* debug registers */
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void *vmx;
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};
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#define inittxtflush(p)
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#define settxtflush(p,c)
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#include "../port/portdat.h"
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typedef struct {
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ulong link; /* link (old TSS selector) */
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ulong esp0; /* privilege level 0 stack pointer */
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ulong ss0; /* privilege level 0 stack selector */
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ulong esp1; /* privilege level 1 stack pointer */
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ulong ss1; /* privilege level 1 stack selector */
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ulong esp2; /* privilege level 2 stack pointer */
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ulong ss2; /* privilege level 2 stack selector */
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ulong xcr3; /* page directory base register - not used because we don't use trap gates */
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ulong eip; /* instruction pointer */
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ulong eflags; /* flags register */
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ulong eax; /* general registers */
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ulong ecx;
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ulong edx;
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ulong ebx;
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ulong esp;
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ulong ebp;
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ulong esi;
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ulong edi;
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ulong es; /* segment selectors */
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ulong cs;
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ulong ss;
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ulong ds;
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ulong fs;
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ulong gs;
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ulong ldt; /* selector for task's LDT */
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ulong iomap; /* I/O map base address + T-bit */
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} Tss;
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struct Mach
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{
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int machno; /* physical id of processor */
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uintptr splpc; /* pc of last caller to splhi */
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Proc* proc; /* current process on this processor */
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Proc* externup; /* extern register Proc *up */
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PMach;
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uvlong tscticks;
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ulong spuriousintr;
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int lastintr;
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int loopconst;
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int aalcycles;
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int cpumhz;
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uvlong cpuhz;
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int cpuidax;
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int cpuidcx;
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int cpuiddx;
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char cpuidid[16];
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char* cpuidtype;
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uchar cpuidfamily;
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uchar cpuidmodel;
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uchar cpuidstepping;
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char havetsc;
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char havepge;
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char havewatchpt8;
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char havenx;
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ulong* pdb; /* page directory base for this processor (va) */
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Tss* tss; /* tss for this processor */
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Segdesc*gdt; /* gdt for this processor */
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u32int dr7; /* shadow copy of dr7 */
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u32int xcr0;
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void* vmx;
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Page* pdbpool;
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int pdbcnt;
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int pdballoc;
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int pdbfree;
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uintptr stack[1];
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};
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/*
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* KMap the structure doesn't exist, but the functions do.
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*/
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typedef struct KMap KMap;
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#define VA(k) ((void*)(k))
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KMap* kmap(Page*);
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void kunmap(KMap*);
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extern u32int MemMin;
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struct
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{
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char machs[MAXMACH]; /* active CPUs */
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int exiting; /* shutdown */
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}active;
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/*
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* routines for things outside the PC model, like power management
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*/
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struct PCArch
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{
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char* id;
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int (*ident)(void); /* this should be in the model */
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void (*reset)(void); /* this should be in the model */
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void (*intrinit)(void);
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int (*intrassign)(Vctl*);
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int (*intrirqno)(int, int);
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int (*intrspurious)(int);
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int (*intrvecno)(int);
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void (*introff)(void);
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void (*intron)(void);
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void (*clockinit)(void);
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void (*clockenable)(void);
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uvlong (*fastclock)(uvlong*);
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void (*timerset)(uvlong);
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};
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/* cpuid instruction result register bits */
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enum {
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/* cx */
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Monitor = 1<<3,
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/* dx */
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Fpuonchip = 1<<0,
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Vmex = 1<<1, /* virtual-mode extensions */
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Pse = 1<<3, /* page size extensions */
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Tsc = 1<<4, /* time-stamp counter */
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Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
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Pae = 1<<6, /* physical-addr extensions */
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Mce = 1<<7, /* machine-check exception */
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Cmpxchg8b = 1<<8,
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Cpuapic = 1<<9,
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Mtrr = 1<<12, /* memory-type range regs. */
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Pge = 1<<13, /* page global extension */
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Mca = 1<<14, /* machine-check architecture */
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Pat = 1<<16, /* page attribute table */
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Pse2 = 1<<17, /* more page size extensions */
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Clflush = 1<<19,
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Acpif = 1<<22, /* therm control msr */
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Mmx = 1<<23,
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Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */
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Sse = 1<<25, /* thus sfence instr. */
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Sse2 = 1<<26, /* thus mfence & lfence instr.s */
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Rdrnd = 1<<30, /* RDRAND support bit */
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};
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/* model-specific registers, for compatibility with pc64 code */
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enum {
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Efer = 0xc0000080, /* Extended Feature Enable */
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Star = 0xc0000081, /* Legacy Target IP and [CS]S */
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Lstar = 0xc0000082, /* Long Mode Target IP */
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Cstar = 0xc0000083, /* Compatibility Target IP */
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Sfmask = 0xc0000084, /* SYSCALL Flags Mask */
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FSbase = 0xc0000100, /* 64-bit FS Base Address */
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GSbase = 0xc0000101, /* 64-bit GS Base Address */
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KernelGSbase = 0xc0000102, /* SWAPGS instruction */
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};
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/*
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* a parsed plan9.ini line
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*/
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#define NISAOPT 8
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struct ISAConf {
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char *type;
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uvlong port;
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int irq;
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ulong dma;
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ulong mem;
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ulong size;
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ulong freq;
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int nopt;
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char *opt[NISAOPT];
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};
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extern PCArch *arch; /* PC architecture */
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/*
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* Each processor sees its own Mach structure at address MACHADDR.
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* However, the Mach structures must also be available via the per-processor
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* MMU information array machp, mainly for disambiguation and access to
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* the clock which is only maintained by the bootstrap processor (0).
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*/
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Mach* machp[MAXMACH];
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#define MACHP(n) (machp[n])
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extern Mach *m;
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#define up (((Mach*)MACHADDR)->externup)
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/*
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* hardware info about a device
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*/
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typedef struct {
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ulong port;
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int size;
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} Devport;
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struct DevConf
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{
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ulong intnum; /* interrupt number */
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char *type; /* card type, malloced */
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int nports; /* Number of ports */
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Devport *ports; /* The ports themselves */
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};
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typedef struct BIOS32ci { /* BIOS32 Calling Interface */
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u32int eax;
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u32int ebx;
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u32int ecx;
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u32int edx;
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u32int esi;
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u32int edi;
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} BIOS32ci;
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