105 lines
3.7 KiB
Plaintext
105 lines
3.7 KiB
Plaintext
global scale sheevaplug & guruplug
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marvell 88f6281 (feroceon kirkwood) SoC
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arm926ej-s rev 1 [56251311] (armv5tejl) 1.2GHz cpu
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l1 I & D VIVT caches 16K each: 4-way, 128 sets, 32-byte lines
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l1 D is write-through, l1 I is write-back
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unified l2 PIPT cache 256K: 4-way, 2048 sets, 32-byte lines
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potentially 512K: 8-way
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apparently the mmu walks the page tables in dram and won't look in the
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l2 cache. there is no hardware cache coherence, thus the l1 caches
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need to be flushed or invalidated when mmu mappings change, but l2
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only needs to be flushed or invalidated around dma operations and page
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table changes, and only the affected dma buffers and descriptors or
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page table entries need to be flushed or invalidated in l2.
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we arrange that device registers are uncached.
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be aware that cache operations act on cache lines (of CACHELINESZ
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bytes) as atomic units, so if you invalidate one word of a cache line,
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you invalidate the entire cache line, whether it's been written back
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(is clean) or not (is dirty). mixed data structures with parts
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maintained by hardware and other parts by software are especially
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tricky. we try to pad the initial hardware parts so that the software
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parts start in a new cache line.
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there are no video controllers so far, so this port is a cpu
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kernel only.
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512MB of dram at physical address 0
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512MB of nand flash
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16550 uart for console
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see http://www.marvell.com/files/products/embedded_processors/kirkwood/\
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FS_88F6180_9x_6281_OpenSource.pdf, stored locally as
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/public/doc/marvell/88f61xx.kirkwood.pdf
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If you plan to use flash, it would be wise to avoid touching the first
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megabyte, which contains u-boot, right up to 0x100000. There's a
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linux kernel from there to 0x400000, if you care. You'll also likely
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want to use paqfs rather than fossil or kfs for file systems in flash
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since there is no wear-levelling.
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The code is fairly heavy-handed with the use of barrier instructions
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(BARRIERS in assembler, coherence in C), partly in reaction to bad
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experience doing Power PC ports, but also just as precautions against
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modern processors, which may feel free to execute instructions out of
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order or some time later, store to memory out of order or some time
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later, otherwise break the model of traditional sequential processors,
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or any combination of the above.
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this plan 9 port is based on the port of native inferno to the
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sheevaplug by Salva Peiró (saoret.one@gmail.com) and Mechiel Lukkien
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(mechiel@ueber.net).
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___
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# type this once at u-boot, replacing 00504301c49e with your plug's
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# mac address; thereafter the plug will pxe boot:
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setenv bootdelay 2
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setenv bootcmd 'bootp; bootp; tftp 0x1000 /cfg/pxe/00504301c49e; bootp; tftp 0x800000; go 0x800000'
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saveenv
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# see /cfg/pxe/example-kw
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physical mem map
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hex addr size what
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----
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0 512MB sdram
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80000000 512MB pcie mem # default
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c8010000 2K cesa sram
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d0000000 1MB internal regs default address at reset
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d8000000 128MB nand flash # actually 512MB addressed through this
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e8000000 128MB spi serial flash
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f0000000 128MB boot rom # default
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f0000000 16MB pcie io # mapped from 0xc0000000 by u-boot
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f1000000 1MB internal regs as mapped by u-boot
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f1000000 64K dram regs
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f1010000 64K uart, flashes, rtc, gpio, etc.
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f1030000 64K crypto accelerator (cesa)
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f1040000 64K pci-e regs
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f1050000 64K usb otg regs (ehci-like)
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f1070000 64K gbe regs
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f1080000 64K non-ahci sata regs
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f1090000 64K sdio regs
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f8000000 128MB boot device # default, mapped to 0 by u-boot
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f8000000 16MB spi flash # mapped by u-boot
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f9000000 8MB nand flash # on sheeva/openrd, mapped by u-boot
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fb000000 64KB crypto engine
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ff000000 16MB boot rom # u-boot
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virtual mem map
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hex addr size what
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----
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0 512MB user process address space
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60000000 kzero, mapped to 0
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90000000 256MB pcie mem # mapped by u-boot
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c0000000 64KB pcie i/o # mapped by u-boot
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... as per physical map
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