2fecc5789e
when clering smi enable bits in the legacy control/status register, preserve the reserved bits. clear the RW1C bits. linux code claims intel xhci controller needs a 1ms delay before accessing any register after reset. |
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.. | ||
bcm | ||
boot | ||
ip | ||
kw | ||
mtx | ||
omap | ||
pc | ||
pc64 | ||
port | ||
ppc | ||
sgi | ||
teg2 | ||
xen | ||
zynq | ||
mkfile |