4f85115526
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
239 lines
4 KiB
C
239 lines
4 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/pci.h"
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#include "../port/error.h"
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#define Image IMAGE
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#include <draw.h>
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#include <memdraw.h>
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#include <cursor.h>
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#include "screen.h"
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typedef struct
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{
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ushort ctl;
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ushort pad;
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ulong base;
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ulong pos;
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} CursorI81x;
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enum {
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Fbsize = 8*MB,
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hwCur = 0x70080,
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SRX = 0x3c4,
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DPMSsync = 0x5002,
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};
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static void
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i81xblank(VGAscr *scr, int blank)
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{
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char *srx, *srxd, *dpms;
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char sr01, mode;
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srx = (char *)scr->mmio+SRX;
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srxd = srx+1;
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dpms = (char *)scr->mmio+DPMSsync;
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*srx = 0x01;
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sr01 = *srxd & ~0x20;
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mode = *dpms & 0xf0;
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if(blank) {
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sr01 |= 0x20;
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mode |= 0x0a;
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}
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*srxd = sr01;
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*dpms = mode;
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}
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static void
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i81xenable(VGAscr* scr)
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{
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Pcidev *p;
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int size;
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ulong *pgtbl, *rp;
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uintptr fbuf, fbend;
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if(scr->mmio)
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return;
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p = scr->pci;
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if(p == nil)
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return;
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if((p->mem[0].bar & 1) != 0
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|| (p->mem[1].bar & 1) != 0)
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return;
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scr->mmio = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size);
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if(scr->mmio == nil)
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return;
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addvgaseg("i81xmmio", p->mem[1].bar&~0x0F, p->mem[1].size);
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/* allocate page table */
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pgtbl = xspanalloc(64*1024, BY2PG, 0);
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scr->mmio[0x2020/4] = PADDR(pgtbl) | 1;
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size = p->mem[0].size;
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if(size > 0)
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size = Fbsize;
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vgalinearaddr(scr, p->mem[0].bar&~0xF, size);
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addvgaseg("i81xscreen", p->mem[0].bar&~0xF, size);
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/*
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* allocate backing store for frame buffer
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* and populate device page tables.
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*/
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fbuf = PADDR(xspanalloc(size, BY2PG, 0));
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fbend = PGROUND(fbuf+size);
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rp = scr->mmio+0x10000/4;
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while(fbuf < fbend) {
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*rp++ = fbuf | 1;
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fbuf += BY2PG;
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}
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scr->storage = 0;
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scr->blank = i81xblank;
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}
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static void
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i81xcurdisable(VGAscr* scr)
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{
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CursorI81x *hwcurs;
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if(scr->mmio == 0)
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return;
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hwcurs = (void*)((uchar*)scr->mmio+hwCur);
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hwcurs->ctl = (1<<4);
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}
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static void
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i81xcurload(VGAscr* scr, Cursor* curs)
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{
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int y;
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uchar *p;
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CursorI81x *hwcurs;
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if(scr->mmio == 0 || scr->storage == 0)
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return;
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hwcurs = (void*)((uchar*)scr->mmio+hwCur);
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/*
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* Disable the cursor then load the new image in
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* the top-left of the 32x32 array.
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* Unused portions of the image have been initialised to be
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* transparent.
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*/
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hwcurs->ctl = (1<<4);
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p = (uchar*)scr->storage;
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for(y = 0; y < 16; y += 2) {
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*p++ = ~(curs->clr[2*y]|curs->set[2*y]);
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*p++ = ~(curs->clr[2*y+1]|curs->set[2*y+1]);
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p += 2;
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*p++ = ~(curs->clr[2*y+2]|curs->set[2*y+2]);
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*p++ = ~(curs->clr[2*y+3]|curs->set[2*y+3]);
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p += 2;
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*p++ = curs->set[2*y];
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*p++ = curs->set[2*y+1];
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p += 2;
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*p++ = curs->set[2*y+2];
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*p++ = curs->set[2*y+3];
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p += 2;
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}
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/*
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* Save the cursor hotpoint and enable the cursor.
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* The 0,0 cursor point is top-left.
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*/
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scr->offset.x = curs->offset.x;
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scr->offset.y = curs->offset.y;
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hwcurs->ctl = (1<<4)|1;
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}
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static int
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i81xcurmove(VGAscr* scr, Point p)
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{
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int x, y;
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ulong pos;
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CursorI81x *hwcurs;
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if(scr->mmio == 0)
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return 1;
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hwcurs = (void*)((uchar*)scr->mmio+hwCur);
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x = p.x+scr->offset.x;
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y = p.y+scr->offset.y;
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pos = 0;
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if(x < 0) {
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pos |= (1<<15);
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x = -x;
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}
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if(y < 0) {
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pos |= (1<<31);
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y = -y;
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}
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pos |= ((y&0x7ff)<<16)|(x&0x7ff);
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hwcurs->pos = pos;
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return 0;
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}
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static void
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i81xcurenable(VGAscr* scr)
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{
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int i;
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uchar *p;
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i81xenable(scr);
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if(scr->mmio == 0)
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return;
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if(scr->storage == 0){
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CursorI81x *hwcurs;
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Page *pg = newpage(0, nil, 0);
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scr->storage = (uintptr)vmap(pg->pa, BY2PG);
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if(scr->storage == 0){
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putpage(pg);
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return;
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}
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hwcurs = (void*)((uchar*)scr->mmio+hwCur);
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hwcurs->base = pg->pa;
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}
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/*
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* Initialise the 32x32 cursor to be transparent in 2bpp mode.
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*/
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p = (uchar*)scr->storage;
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for(i = 0; i < 32/2; i++) {
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memset(p, 0xff, 8);
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memset(p+8, 0, 8);
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p += 16;
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}
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/*
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* Load, locate and enable the 32x32 cursor in 2bpp mode.
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*/
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i81xcurload(scr, &cursor);
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i81xcurmove(scr, ZP);
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}
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VGAdev vgai81xdev = {
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"i81x",
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i81xenable,
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nil,
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nil,
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nil,
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};
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VGAcur vgai81xcur = {
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"i81xhwgc",
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i81xcurenable,
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i81xcurdisable,
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i81xcurload,
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i81xcurmove,
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};
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