4f85115526
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
901 lines
21 KiB
C
901 lines
21 KiB
C
/*
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* Broadcom BCM57xx
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* Not implemented:
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* proper fatal error handling
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* multiple rings
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* QoS
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* checksum offloading
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/pci.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "../port/etherif.h"
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#define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
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typedef struct Ctlr Ctlr;
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struct Ctlr {
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Lock txlock, imlock;
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Ctlr *link;
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uvlong port;
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Pcidev *pdev;
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ulong *nic, *status;
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/* One Ring to find them, One Ring to bring them all and in the darkness bind them */
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ulong *recvret, *recvprod, *sendr;
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ulong recvreti, recvprodi, sendri, sendcleani;
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Block **sends, **recvs;
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int active, duplex;
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};
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enum {
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RecvRetRingLen = 0x200,
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RecvProdRingLen = 0x200,
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SendRingLen = 0x200,
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};
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enum {
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Reset = 1<<0,
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Enable = 1<<1,
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Attn = 1<<2,
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PowerControlStatus = 0x4C,
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MiscHostCtl = 0x68,
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ClearIntA = 1<<0,
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MaskPCIInt = 1<<1,
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ByteSwap = 1<<2,
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WordSwap = 1<<3,
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EnablePCIStateRegister = 1<<4,
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EnableClockControlRegister = 1<<5,
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IndirectAccessEnable = 1<<7,
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TaggedStatus = 1<<9,
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DMARWControl = 0x6C,
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DMAWatermarkMask = ~(7<<19),
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DMAWatermarkValue = 3<<19,
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MemoryWindow = 0x7C,
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MemoryWindowData = 0x84,
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SendRCB = 0x100,
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RecvRetRCB = 0x200,
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InterruptMailbox = 0x204,
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RecvProdBDRingIndex = 0x26c,
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RecvBDRetRingIndex = 0x284,
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SendBDRingHostIndex = 0x304,
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MACMode = 0x400,
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MACPortMask = ~((1<<3)|(1<<2)),
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MACPortGMII = 1<<3,
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MACPortMII = 1<<2,
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MACEnable = (1<<23) | (1<<22) | (1<<21) | (1 << 15) | (1 << 14) | (1<<12) | (1<<11),
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MACHalfDuplex = 1<<1,
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MACEventStatus = 0x404,
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MACEventEnable = 0x408,
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MACAddress = 0x410,
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EthernetRandomBackoff = 0x438,
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ReceiveMTU = 0x43C,
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MIComm = 0x44C,
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MIStatus = 0x450,
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MIMode = 0x454,
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ReceiveMACMode = 0x468,
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TransmitMACMode = 0x45C,
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TransmitMACLengths = 0x464,
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MACHash = 0x470,
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ReceiveRules = 0x480,
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ReceiveRulesConfiguration = 0x500,
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LowWatermarkMaximum = 0x504,
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LowWatermarkMaxMask = ~0xFFFF,
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LowWatermarkMaxValue = 2,
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SendDataInitiatorMode = 0xC00,
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SendInitiatorConfiguration = 0x0C08,
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SendStats = 1<<0,
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SendInitiatorMask = 0x0C0C,
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SendDataCompletionMode = 0x1000,
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SendBDSelectorMode = 0x1400,
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SendBDInitiatorMode = 0x1800,
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SendBDCompletionMode = 0x1C00,
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ReceiveListPlacementMode = 0x2000,
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ReceiveListPlacement = 0x2010,
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ReceiveListPlacementConfiguration = 0x2014,
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ReceiveStats = 1<<0,
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ReceiveListPlacementMask = 0x2018,
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ReceiveDataBDInitiatorMode = 0x2400,
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ReceiveBDHostAddr = 0x2450,
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ReceiveBDFlags = 0x2458,
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ReceiveBDNIC = 0x245C,
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ReceiveDataCompletionMode = 0x2800,
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ReceiveBDInitiatorMode = 0x2C00,
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ReceiveBDRepl = 0x2C18,
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ReceiveBDCompletionMode = 0x3000,
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HostCoalescingMode = 0x3C00,
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HostCoalescingRecvTicks = 0x3C08,
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HostCoalescingSendTicks = 0x3C0C,
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RecvMaxCoalescedFrames = 0x3C10,
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SendMaxCoalescedFrames = 0x3C14,
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RecvMaxCoalescedFramesInt = 0x3C20,
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SendMaxCoalescedFramesInt = 0x3C24,
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StatusBlockHostAddr = 0x3C38,
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FlowAttention = 0x3C48,
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MemArbiterMode = 0x4000,
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BufferManMode = 0x4400,
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MBUFLowWatermark = 0x4414,
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MBUFHighWatermark = 0x4418,
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ReadDMAMode = 0x4800,
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ReadDMAStatus = 0x4804,
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WriteDMAMode = 0x4C00,
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WriteDMAStatus = 0x4C04,
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RISCState = 0x5004,
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FTQReset = 0x5C00,
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MSIMode = 0x6000,
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ModeControl = 0x6800,
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ByteWordSwap = (1<<4)|(1<<5)|(1<<2),//|(1<<1),
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HostStackUp = 1<<16,
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HostSendBDs = 1<<17,
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InterruptOnMAC = 1<<26,
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MiscConfiguration = 0x6804,
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CoreClockBlocksReset = 1<<0,
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GPHYPowerDownOverride = 1<<26,
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DisableGRCResetOnPCIE = 1<<29,
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TimerMask = ~0xFF,
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TimerValue = 65<<1,
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MiscLocalControl = 0x6808,
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InterruptOnAttn = 1<<3,
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AutoSEEPROM = 1<<24,
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SwArbitration = 0x7020,
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SwArbitSet1 = 1<<1,
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SwArbitWon1 = 1<<9,
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TLPControl = 0x7C00,
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PhyControl = 0x00,
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PhyStatus = 0x01,
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PhyLinkStatus = 1<<2,
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PhyAutoNegComplete = 1<<5,
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PhyPartnerStatus = 0x05,
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Phy100FD = 1<<8,
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Phy100HD = 1<<7,
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Phy10FD = 1<<6,
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Phy10HD = 1<<5,
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PhyGbitStatus = 0x0A,
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Phy1000FD = 1<<12,
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Phy1000HD = 1<<11,
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PhyAuxControl = 0x18,
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PhyIntStatus = 0x1A,
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PhyIntMask = 0x1B,
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Updated = 1<<0,
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LinkStateChange = 1<<1,
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Error = 1<<2,
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PacketEnd = 1<<2,
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FrameError = 1<<10,
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};
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enum {
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BCM5752 = 0x1600,
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BCM5752M = 0x1601,
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BCM5709 = 0x1639,
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BCM5709S = 0x163a,
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BCM5716 = 0x163b,
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BCM5716S = 0x163c,
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BCM5700 = 0x1644,
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BCM5701 = 0x1645,
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BCM5702 = 0x1646,
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BCM5703 = 0x1647,
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BCM5704 = 0x1648,
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BCM5704S_2 = 0x1649,
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BCM5706 = 0x164a,
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BCM5708 = 0x164c,
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BCM5702FE = 0x164d,
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BCM57710 = 0x164e,
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BCM57711 = 0x164f,
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BCM57711E = 0x1650,
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BCM5705 = 0x1653,
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BCM5705_2 = 0x1654,
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BCM5717 = 0x1655,
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BCM5718 = 0x1656,
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BCM5720 = 0x1658,
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BCM5721 = 0x1659,
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BCM5722 = 0x165a,
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BCM5723 = 0x165b,
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BCM5724 = 0x165c,
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BCM5705M = 0x165d,
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BCM5705M_2 = 0x165e,
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BCM5714 = 0x1668,
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BCM5780 = 0x166a,
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BCM5780S = 0x166b,
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BCM5754M = 0x1672,
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BCM5755M = 0x1673,
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BCM5756ME = 0x1674,
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BCM5750 = 0x1676,
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BCM5751 = 0x1677,
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BCM5715 = 0x1678,
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BCM5715S = 0x1679,
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BCM5754 = 0x167a,
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BCM5755 = 0x167b,
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BCM5750M = 0x167c,
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BCM5751M = 0x167d,
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BCM5751F = 0x167e,
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BCM5787F = 0x167f,
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BCM5761e = 0x1680,
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BCM5761 = 0x1681,
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BCM5764M = 0x1684,
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BCM57760 = 0x1690,
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BCM57788 = 0x1691,
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BCM57780 = 0x1692,
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BCM5787M = 0x1693,
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BCM57790 = 0x1694,
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BCM5782 = 0x1696,
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BCM5784M = 0x1698,
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BCM5785 = 0x1699,
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BCM5786 = 0x169a,
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BCM5787 = 0x169b,
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BCM5788 = 0x169c,
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BCM5789 = 0x169d,
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BCM5785_2 = 0x16a0,
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BCM5702X = 0x16a6,
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BCM5703X = 0x16a7,
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BCM5704S = 0x16a8,
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BCM5706S = 0x16aa,
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BCM5708S = 0x16ac,
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BCM57761 = 0x16b0,
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BCM57781 = 0x16b1,
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BCM57791 = 0x16b2,
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BCM57765 = 0x16b4,
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BCM57785 = 0x16b5,
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BCM57795 = 0x16b6,
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BCM5702A3 = 0x16c6,
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BCM5703_2 = 0x16c7,
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BCM5781 = 0x16dd,
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BCM5753 = 0x16f7,
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BCM5753M = 0x16fd,
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BCM5753F = 0x16fe,
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BCM5906 = 0x1712,
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BCM5906M = 0x1713,
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};
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#define csr32(c, r) ((c)->nic[(r)/4])
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#define mem32(c, r) csr32(c, (r)+0x8000)
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static Ctlr *bcmhead, *bcmtail;
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static ulong
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dummyread(ulong x)
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{
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return x;
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}
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static int
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miir(Ctlr *ctlr, int ra)
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{
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while(csr32(ctlr, MIComm) & (1<<29));
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csr32(ctlr, MIComm) = (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
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while(csr32(ctlr, MIComm) & (1<<29));
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if(csr32(ctlr, MIComm) & (1<<28)) return -1;
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return csr32(ctlr, MIComm) & 0xFFFF;
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}
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static int
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miiw(Ctlr *ctlr, int ra, int value)
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{
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while(csr32(ctlr, MIComm) & (1<<29));
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csr32(ctlr, MIComm) = (value & 0xFFFF) | (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
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while(csr32(ctlr, MIComm) & (1<<29));
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return 0;
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}
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static void
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checklink(Ether *edev)
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{
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Ctlr *ctlr;
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ulong i;
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ctlr = edev->ctlr;
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miir(ctlr, PhyStatus); /* dummy read necessary */
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if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
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edev->link = 0;
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edev->mbps = 1000;
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ctlr->duplex = 1;
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print("bcm: no link\n");
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goto out;
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}
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edev->link = 1;
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while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
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i = miir(ctlr, PhyGbitStatus);
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if(i & (Phy1000FD | Phy1000HD)) {
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edev->mbps = 1000;
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ctlr->duplex = (i & Phy1000FD) != 0;
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} else if(i = miir(ctlr, PhyPartnerStatus), i & (Phy100FD | Phy100HD)) {
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edev->mbps = 100;
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ctlr->duplex = (i & Phy100FD) != 0;
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} else if(i & (Phy10FD | Phy10HD)) {
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edev->mbps = 10;
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ctlr->duplex = (i & Phy10FD) != 0;
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} else {
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edev->link = 0;
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edev->mbps = 1000;
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ctlr->duplex = 1;
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print("bcm: link partner supports neither 10/100/1000 Mbps\n");
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goto out;
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}
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print("bcm: %d Mbps link, %s duplex\n", edev->mbps, ctlr->duplex ? "full" : "half");
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out:
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if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
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else csr32(ctlr, MACMode) |= MACHalfDuplex;
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if(edev->mbps >= 1000)
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csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
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else
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csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortMII;
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csr32(ctlr, MACEventStatus) |= (1<<4) | (1<<3); /* undocumented bits (sync and config changed) */
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}
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static ulong*
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currentrecvret(Ctlr *ctlr)
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{
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if(ctlr->recvreti == (ctlr->status[4] & 0xFFFF)) return 0;
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return ctlr->recvret + ctlr->recvreti * 8;
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}
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static void
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consumerecvret(Ctlr *ctlr)
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{
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csr32(ctlr, RecvBDRetRingIndex) = ctlr->recvreti = (ctlr->recvreti + 1) & (RecvRetRingLen - 1);
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}
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static int
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replenish(Ctlr *ctlr)
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{
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ulong *next;
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ulong incr, idx;
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Block *bp;
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idx = ctlr->recvprodi;
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incr = (idx + 1) & (RecvProdRingLen - 1);
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if(incr == (ctlr->status[2] >> 16)) return -1;
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if(ctlr->recvs[idx] != 0) return -1;
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bp = iallocb(Rbsz);
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if(bp == nil) {
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print("bcm: out of memory for receive buffers\n");
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return -1;
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}
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ctlr->recvs[idx] = bp;
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next = ctlr->recvprod + idx * 8;
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memset(next, 0, 32);
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next[1] = PADDR(bp->rp);
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next[2] = Rbsz;
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next[7] = idx;
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coherence();
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csr32(ctlr, RecvProdBDRingIndex) = ctlr->recvprodi = incr;
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return 0;
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}
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static void
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bcmreceive(Ether *edev)
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{
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Ctlr *ctlr;
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Block *bp;
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ulong *pkt, len, idx;
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ctlr = edev->ctlr;
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for(; pkt = currentrecvret(ctlr); replenish(ctlr), consumerecvret(ctlr)) {
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idx = pkt[7] & (RecvProdRingLen - 1);
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bp = ctlr->recvs[idx];
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if(bp == 0) {
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print("bcm: nil block at %lux -- shouldn't happen\n", idx);
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break;
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}
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ctlr->recvs[idx] = 0;
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len = pkt[2] & 0xFFFF;
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bp->wp = bp->rp + len;
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if((pkt[3] & PacketEnd) == 0) print("bcm: partial frame received -- shouldn't happen\n");
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if(pkt[3] & FrameError) {
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freeb(bp); /* dump erroneous packets */
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} else {
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etheriq(edev, bp);
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}
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}
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}
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static void
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bcmtransclean(Ether *edev, int dolock)
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{
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Ctlr *ctlr;
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ctlr = edev->ctlr;
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if(dolock)
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ilock(&ctlr->txlock);
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while(ctlr->sendcleani != (ctlr->status[4] >> 16)) {
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freeb(ctlr->sends[ctlr->sendcleani]);
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ctlr->sends[ctlr->sendcleani] = 0;
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ctlr->sendcleani = (ctlr->sendcleani + 1) & (SendRingLen - 1);
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}
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if(dolock)
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iunlock(&ctlr->txlock);
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}
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static void
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bcmtransmit(Ether *edev)
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{
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Ctlr *ctlr;
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Block *bp;
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ulong *next;
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ulong incr;
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ctlr = edev->ctlr;
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ilock(&ctlr->txlock);
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while(1) {
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incr = (ctlr->sendri + 1) & (SendRingLen - 1);
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if(incr == (ctlr->status[4] >> 16)) {
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print("bcm: send queue full\n");
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break;
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}
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bp = qget(edev->oq);
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if(bp == nil) break;
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next = ctlr->sendr + ctlr->sendri * 4;
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next[0] = 0;
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next[1] = PADDR(bp->rp);
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next[2] = (BLEN(bp) << 16) | PacketEnd;
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next[3] = 0;
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if(ctlr->sends[ctlr->sendri] != 0)
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freeb(ctlr->sends[ctlr->sendri]);
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ctlr->sends[ctlr->sendri] = bp;
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coherence();
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csr32(ctlr, SendBDRingHostIndex) = ctlr->sendri = incr;
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}
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iunlock(&ctlr->txlock);
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}
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static void
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bcmerror(Ether *edev)
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{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
if(csr32(ctlr, FlowAttention)) {
|
|
if(csr32(ctlr, FlowAttention) & 0xF8FF8080UL) {
|
|
panic("bcm: fatal error %#.8ulx", csr32(ctlr, FlowAttention));
|
|
}
|
|
csr32(ctlr, FlowAttention) = 0;
|
|
}
|
|
csr32(ctlr, MACEventStatus) = 0; /* worth ignoring */
|
|
if(csr32(ctlr, ReadDMAStatus) || csr32(ctlr, WriteDMAStatus)) {
|
|
print("bcm: DMA error\n");
|
|
csr32(ctlr, ReadDMAStatus) = 0;
|
|
csr32(ctlr, WriteDMAStatus) = 0;
|
|
}
|
|
if(csr32(ctlr, RISCState)) {
|
|
if(csr32(ctlr, RISCState) & 0x78000403) {
|
|
panic("bcm: RISC halted %#.8ulx", csr32(ctlr, RISCState));
|
|
}
|
|
csr32(ctlr, RISCState) = 0;
|
|
}
|
|
}
|
|
|
|
static void
|
|
bcminterrupt(Ureg*, void *arg)
|
|
{
|
|
Ether *edev;
|
|
Ctlr *ctlr;
|
|
ulong status, tag;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
ilock(&ctlr->imlock);
|
|
dummyread(csr32(ctlr, InterruptMailbox));
|
|
csr32(ctlr, InterruptMailbox) = 1;
|
|
status = ctlr->status[0];
|
|
tag = ctlr->status[1];
|
|
ctlr->status[0] = 0;
|
|
if(status & Error) bcmerror(edev);
|
|
if(status & LinkStateChange) checklink(edev);
|
|
// print("bcm: interrupt %8ulx %8ulx\n", ctlr->status[2], ctlr->status[4]);
|
|
bcmreceive(edev);
|
|
bcmtransclean(edev, 1);
|
|
bcmtransmit(edev);
|
|
csr32(ctlr, InterruptMailbox) = tag << 24;
|
|
iunlock(&ctlr->imlock);
|
|
}
|
|
|
|
static int
|
|
bcminit(Ether *edev)
|
|
{
|
|
ulong i, j;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = edev->ctlr;
|
|
print("bcm: reset\n");
|
|
/* initialization procedure according to the datasheet */
|
|
csr32(ctlr, MiscHostCtl) |= MaskPCIInt | ClearIntA;
|
|
csr32(ctlr, SwArbitration) |= SwArbitSet1;
|
|
for(i = 0; i < 10000 && (csr32(ctlr, SwArbitration) & SwArbitWon1) == 0; i++)
|
|
microdelay(100);
|
|
if(i == 10000){
|
|
iprint("bcm: arbiter failed to respond\n");
|
|
return -1;
|
|
}
|
|
csr32(ctlr, MemArbiterMode) |= Enable;
|
|
csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister;
|
|
csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
|
|
csr32(ctlr, ModeControl) |= ByteWordSwap;
|
|
csr32(ctlr, MemoryWindow) = 0;
|
|
mem32(ctlr, 0xB50) = 0x4B657654; /* magic number bullshit */
|
|
csr32(ctlr, MiscConfiguration) |= GPHYPowerDownOverride | DisableGRCResetOnPCIE;
|
|
csr32(ctlr, MiscConfiguration) |= CoreClockBlocksReset;
|
|
microdelay(100000);
|
|
ctlr->pdev->pcr |= 1<<1; /* pci memory access enable */
|
|
pcisetbme(ctlr->pdev);
|
|
csr32(ctlr, MiscHostCtl) |= MaskPCIInt;
|
|
csr32(ctlr, MemArbiterMode) |= Enable;
|
|
csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
|
|
csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister | TaggedStatus;
|
|
csr32(ctlr, ModeControl) |= ByteWordSwap;
|
|
csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
|
|
microdelay(40000);
|
|
for(i = 0; i < 100000 && mem32(ctlr, 0xB50) != 0xB49A89AB; i++)
|
|
microdelay(100);
|
|
if(i == 100000){
|
|
iprint("bcm: chip failed to reset\n");
|
|
return -1;
|
|
}
|
|
switch(ctlr->pdev->did){
|
|
case BCM5721:
|
|
case BCM5751:
|
|
case BCM5752:
|
|
csr32(ctlr, TLPControl) |= (1<<25) | (1<<29);
|
|
break;
|
|
}
|
|
memset(ctlr->status, 0, 20);
|
|
csr32(ctlr, DMARWControl) = (csr32(ctlr, DMARWControl) & DMAWatermarkMask) | DMAWatermarkValue;
|
|
csr32(ctlr, ModeControl) |= HostSendBDs | HostStackUp | InterruptOnMAC;
|
|
csr32(ctlr, MiscConfiguration) = (csr32(ctlr, MiscConfiguration) & TimerMask) | TimerValue;
|
|
csr32(ctlr, MBUFLowWatermark) = 0x20;
|
|
csr32(ctlr, MBUFHighWatermark) = 0x60;
|
|
csr32(ctlr, LowWatermarkMaximum) = (csr32(ctlr, LowWatermarkMaximum) & LowWatermarkMaxMask) | LowWatermarkMaxValue;
|
|
csr32(ctlr, BufferManMode) |= Enable | Attn;
|
|
for(i = 0; i < 100 && (csr32(ctlr, BufferManMode) & Enable) == 0; i++)
|
|
microdelay(100);
|
|
if(i == 100){
|
|
iprint("bcm: buffer manager failed to start\n");
|
|
return -1;
|
|
}
|
|
csr32(ctlr, FTQReset) = -1;
|
|
csr32(ctlr, FTQReset) = 0;
|
|
for(i = 0; i < 1000 && csr32(ctlr, FTQReset) != 0; i++)
|
|
microdelay(100);
|
|
if(i == 1000){
|
|
iprint("bcm: ftq failed to reset\n");
|
|
return -1;
|
|
}
|
|
csr32(ctlr, ReceiveBDHostAddr) = 0;
|
|
csr32(ctlr, ReceiveBDHostAddr + 4) = PADDR(ctlr->recvprod);
|
|
csr32(ctlr, ReceiveBDFlags) = RecvProdRingLen << 16;
|
|
csr32(ctlr, ReceiveBDNIC) = 0x6000;
|
|
csr32(ctlr, ReceiveBDRepl) = 25;
|
|
csr32(ctlr, SendBDRingHostIndex) = 0;
|
|
csr32(ctlr, SendBDRingHostIndex+4) = 0;
|
|
mem32(ctlr, SendRCB) = 0;
|
|
mem32(ctlr, SendRCB + 4) = PADDR(ctlr->sendr);
|
|
mem32(ctlr, SendRCB + 8) = SendRingLen << 16;
|
|
mem32(ctlr, SendRCB + 12) = 0x4000;
|
|
for(i=1;i<4;i++)
|
|
mem32(ctlr, RecvRetRCB + i * 0x10 + 8) = 2;
|
|
mem32(ctlr, RecvRetRCB) = 0;
|
|
mem32(ctlr, RecvRetRCB + 4) = PADDR(ctlr->recvret);
|
|
mem32(ctlr, RecvRetRCB + 8) = RecvRetRingLen << 16;
|
|
csr32(ctlr, RecvProdBDRingIndex) = 0;
|
|
csr32(ctlr, RecvProdBDRingIndex+4) = 0;
|
|
/* this delay is not in the datasheet, but necessary; Broadcom is fucking with us */
|
|
microdelay(1000);
|
|
i = csr32(ctlr, 0x410);
|
|
j = edev->ea[0] = i >> 8;
|
|
j += edev->ea[1] = i;
|
|
i = csr32(ctlr, MACAddress + 4);
|
|
j += edev->ea[2] = i >> 24;
|
|
j += edev->ea[3] = i >> 16;
|
|
j += edev->ea[4] = i >> 8;
|
|
j += edev->ea[5] = i;
|
|
csr32(ctlr, EthernetRandomBackoff) = j & 0x3FF;
|
|
csr32(ctlr, ReceiveMTU) = Rbsz;
|
|
csr32(ctlr, TransmitMACLengths) = 0x2620;
|
|
csr32(ctlr, ReceiveListPlacement) = 1<<3; /* one list */
|
|
csr32(ctlr, ReceiveListPlacementMask) = 0xFFFFFF;
|
|
csr32(ctlr, ReceiveListPlacementConfiguration) |= ReceiveStats;
|
|
csr32(ctlr, SendInitiatorMask) = 0xFFFFFF;
|
|
csr32(ctlr, SendInitiatorConfiguration) |= SendStats;
|
|
csr32(ctlr, HostCoalescingMode) = 0;
|
|
for(i = 0; i < 200 && csr32(ctlr, HostCoalescingMode) != 0; i++)
|
|
microdelay(100);
|
|
if(i == 200){
|
|
iprint("bcm: host coalescing engine failed to stop\n");
|
|
return -1;
|
|
}
|
|
csr32(ctlr, HostCoalescingRecvTicks) = 150;
|
|
csr32(ctlr, HostCoalescingSendTicks) = 150;
|
|
csr32(ctlr, RecvMaxCoalescedFrames) = 10;
|
|
csr32(ctlr, SendMaxCoalescedFrames) = 10;
|
|
csr32(ctlr, RecvMaxCoalescedFramesInt) = 0;
|
|
csr32(ctlr, SendMaxCoalescedFramesInt) = 0;
|
|
csr32(ctlr, StatusBlockHostAddr) = 0;
|
|
csr32(ctlr, StatusBlockHostAddr + 4) = PADDR(ctlr->status);
|
|
csr32(ctlr, HostCoalescingMode) |= Enable;
|
|
csr32(ctlr, ReceiveBDCompletionMode) |= Enable | Attn;
|
|
csr32(ctlr, ReceiveListPlacementMode) |= Enable;
|
|
csr32(ctlr, MACMode) |= MACEnable;
|
|
csr32(ctlr, MiscLocalControl) |= InterruptOnAttn | AutoSEEPROM;
|
|
csr32(ctlr, InterruptMailbox) = 0;
|
|
csr32(ctlr, WriteDMAMode) |= 0x200003fe; /* pulled out of my nose */
|
|
csr32(ctlr, ReadDMAMode) |= 0x3fe;
|
|
csr32(ctlr, ReceiveDataCompletionMode) |= Enable | Attn;
|
|
csr32(ctlr, SendDataCompletionMode) |= Enable;
|
|
csr32(ctlr, SendBDCompletionMode) |= Enable | Attn;
|
|
csr32(ctlr, ReceiveBDInitiatorMode) |= Enable | Attn;
|
|
csr32(ctlr, ReceiveDataBDInitiatorMode) |= Enable | (1<<4);
|
|
csr32(ctlr, SendDataInitiatorMode) |= Enable;
|
|
csr32(ctlr, SendBDInitiatorMode) |= Enable | Attn;
|
|
csr32(ctlr, SendBDSelectorMode) |= Enable | Attn;
|
|
ctlr->recvprodi = 0;
|
|
while(replenish(ctlr) >= 0);
|
|
csr32(ctlr, TransmitMACMode) |= Enable;
|
|
csr32(ctlr, ReceiveMACMode) |= Enable;
|
|
csr32(ctlr, PowerControlStatus) &= ~3;
|
|
csr32(ctlr, MIStatus) |= 1<<0;
|
|
csr32(ctlr, MACEventEnable) = 0;
|
|
csr32(ctlr, MACEventStatus) |= (1<<12);
|
|
csr32(ctlr, MIMode) = 0xC0000;
|
|
microdelay(40);
|
|
miiw(ctlr, PhyControl, 1<<15);
|
|
for(i = 0; i < 1000 && miir(ctlr, PhyControl) & (1<<15); i++)
|
|
microdelay(100);
|
|
if(i == 1000){
|
|
iprint("bcm: PHY failed to reset\n");
|
|
return -1;
|
|
}
|
|
miiw(ctlr, PhyAuxControl, 2);
|
|
miir(ctlr, PhyIntStatus);
|
|
miir(ctlr, PhyIntStatus);
|
|
miiw(ctlr, PhyIntMask, ~(1<<1));
|
|
checklink(edev);
|
|
csr32(ctlr, MACEventEnable) |= 1<<12;
|
|
csr32(ctlr, MACHash) = -1;
|
|
csr32(ctlr, MACHash+4) = -1;
|
|
csr32(ctlr, MACHash+8) = -1;
|
|
csr32(ctlr, MACHash+12) = -1;
|
|
for(i = 0; i < 8; i++) csr32(ctlr, ReceiveRules + 8 * i) = 0;
|
|
csr32(ctlr, ReceiveRulesConfiguration) = 1 << 3;
|
|
csr32(ctlr, MSIMode) |= Enable;
|
|
csr32(ctlr, MiscHostCtl) &= ~(MaskPCIInt | ClearIntA);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
bcmpci(void)
|
|
{
|
|
Pcidev *pdev;
|
|
|
|
pdev = nil;
|
|
while(pdev = pcimatch(pdev, 0, 0)) {
|
|
Ctlr *ctlr;
|
|
void *mem;
|
|
|
|
if(pdev->ccrb != 2 || pdev->ccru != 0)
|
|
continue;
|
|
if(pdev->vid != 0x14e4)
|
|
continue;
|
|
if(pdev->mem[0].bar & 1)
|
|
continue;
|
|
|
|
switch(pdev->did){
|
|
default:
|
|
continue;
|
|
case BCM5752:
|
|
case BCM5752M:
|
|
case BCM5709:
|
|
case BCM5709S:
|
|
case BCM5716:
|
|
case BCM5716S:
|
|
case BCM5700:
|
|
case BCM5701:
|
|
case BCM5702:
|
|
case BCM5703:
|
|
case BCM5704:
|
|
case BCM5704S_2:
|
|
case BCM5706:
|
|
case BCM5708:
|
|
case BCM5702FE:
|
|
case BCM57710:
|
|
case BCM57711:
|
|
case BCM57711E:
|
|
case BCM5705:
|
|
case BCM5705_2:
|
|
case BCM5717:
|
|
case BCM5718:
|
|
case BCM5720:
|
|
case BCM5721:
|
|
case BCM5722:
|
|
case BCM5723:
|
|
case BCM5724:
|
|
case BCM5705M:
|
|
case BCM5705M_2:
|
|
case BCM5714:
|
|
case BCM5780:
|
|
case BCM5780S:
|
|
case BCM5754M:
|
|
case BCM5755M:
|
|
case BCM5756ME:
|
|
case BCM5750:
|
|
case BCM5751:
|
|
case BCM5715:
|
|
case BCM5715S:
|
|
case BCM5754:
|
|
case BCM5755:
|
|
case BCM5750M:
|
|
case BCM5751M:
|
|
case BCM5751F:
|
|
case BCM5787F:
|
|
case BCM5761e:
|
|
case BCM5761:
|
|
case BCM5764M:
|
|
case BCM57760:
|
|
case BCM57788:
|
|
case BCM57780:
|
|
case BCM5787M:
|
|
case BCM57790:
|
|
case BCM5782:
|
|
case BCM5784M:
|
|
case BCM5785:
|
|
case BCM5786:
|
|
case BCM5787:
|
|
case BCM5788:
|
|
case BCM5789:
|
|
case BCM5785_2:
|
|
case BCM5702X:
|
|
case BCM5703X:
|
|
case BCM5704S:
|
|
case BCM5706S:
|
|
case BCM5708S:
|
|
case BCM57761:
|
|
case BCM57781:
|
|
case BCM57791:
|
|
case BCM57765:
|
|
case BCM57785:
|
|
case BCM57795:
|
|
case BCM5702A3:
|
|
case BCM5703_2:
|
|
case BCM5781:
|
|
case BCM5753:
|
|
case BCM5753M:
|
|
case BCM5753F:
|
|
case BCM5906: /* ??? */
|
|
case BCM5906M: /* ??? */
|
|
case 0x1670: /* ??? */
|
|
break;
|
|
}
|
|
ctlr = malloc(sizeof(Ctlr));
|
|
if(ctlr == nil) {
|
|
print("bcm: unable to alloc Ctlr\n");
|
|
continue;
|
|
}
|
|
ctlr->sends = malloc(sizeof(ctlr->sends[0]) * SendRingLen);
|
|
ctlr->recvs = malloc(sizeof(ctlr->recvs[0]) * RecvProdRingLen);
|
|
if(ctlr->sends == nil || ctlr->recvs == nil){
|
|
print("bcm: unable to alloc ctlr->sends and ctlr->recvs\n");
|
|
free(ctlr->sends);
|
|
free(ctlr->recvs);
|
|
free(ctlr);
|
|
continue;
|
|
}
|
|
ctlr->port = pdev->mem[0].bar & ~0xF;
|
|
mem = vmap(ctlr->port, pdev->mem[0].size);
|
|
if(mem == nil) {
|
|
print("bcm: can't map %llux\n", ctlr->port);
|
|
free(ctlr->sends);
|
|
free(ctlr->recvs);
|
|
free(ctlr);
|
|
continue;
|
|
}
|
|
ctlr->pdev = pdev;
|
|
ctlr->nic = mem;
|
|
ctlr->status = xspanalloc(20, 16, 0);
|
|
ctlr->recvprod = xspanalloc(32 * RecvProdRingLen, 16, 0);
|
|
ctlr->recvret = xspanalloc(32 * RecvRetRingLen, 16, 0);
|
|
ctlr->sendr = xspanalloc(16 * SendRingLen, 16, 0);
|
|
if(bcmhead != nil)
|
|
bcmtail->link = ctlr;
|
|
else
|
|
bcmhead = ctlr;
|
|
bcmtail = ctlr;
|
|
}
|
|
}
|
|
|
|
static void
|
|
bcmpromiscuous(void* arg, int on)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = ((Ether*)arg)->ctlr;
|
|
if(on)
|
|
csr32(ctlr, ReceiveMACMode) |= 1<<8;
|
|
else
|
|
csr32(ctlr, ReceiveMACMode) &= ~(1<<8);
|
|
}
|
|
|
|
static void
|
|
bcmmulticast(void*, uchar*, int)
|
|
{
|
|
}
|
|
|
|
static int
|
|
bcmpnp(Ether* edev)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
again:
|
|
if(bcmhead == nil)
|
|
bcmpci();
|
|
|
|
for(ctlr = bcmhead; ctlr != nil; ctlr = ctlr->link) {
|
|
if(ctlr->active)
|
|
continue;
|
|
|
|
if(edev->port == 0 || edev->port == ctlr->port) {
|
|
ctlr->active = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
pcienable(ctlr->pdev);
|
|
pcisetbme(ctlr->pdev);
|
|
|
|
edev->ctlr = ctlr;
|
|
edev->port = ctlr->port;
|
|
edev->irq = ctlr->pdev->intl;
|
|
edev->tbdf = ctlr->pdev->tbdf;
|
|
edev->transmit = bcmtransmit;
|
|
edev->multicast = bcmmulticast;
|
|
edev->promiscuous = bcmpromiscuous;
|
|
edev->arg = edev;
|
|
edev->mbps = 1000;
|
|
|
|
if(bcminit(edev) < 0){
|
|
edev->ctlr = nil;
|
|
goto again;
|
|
}
|
|
|
|
intrenable(edev->irq, bcminterrupt, edev, edev->tbdf, edev->name);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
etherbcmlink(void)
|
|
{
|
|
addethercard("bcm", bcmpnp);
|
|
}
|