53275c7045
the max packet size is configured in 1K increments on these chips, which can result in the card receiving a 10K packet but the driver having only allocated 9.5K of buffer. this actually caued pool corruption with i210, i217, i218, i219, i350. for 82598 and x550, we explicitely round rbsz to avoid similar bugs in the future, even tho the Rbsz constant was already a multiple of 1K and is not affected by the bug.
972 lines
18 KiB
C
972 lines
18 KiB
C
/*
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* intel 10GB ethernet pci-express driver
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* copyright © 2007, coraid, inc.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "../port/etherif.h"
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/*
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* // comments note conflicts with 82563-style drivers,
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* and the registers are all different.
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*/
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enum {
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/* general */
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Ctrl = 0x00000/4, /* Device Control */
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Status = 0x00008/4, /* Device Status */
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Ctrlext = 0x00018/4, /* Extended Device Control */
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Esdp = 0x00020/4, /* extended sdp control */
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Esodp = 0x00028/4, /* extended od sdp control */
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Ledctl = 0x00200/4, /* led control */
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Tcptimer = 0x0004c/4, /* tcp timer */
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Ecc = 0x110b0/4, /* errata ecc control magic */
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/* nvm */
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Eec = 0x10010/4, /* eeprom/flash control */
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Eerd = 0x10014/4, /* eeprom read */
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Fla = 0x1001c/4, /* flash access */
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Flop = 0x1013c/4, /* flash opcode */
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Grc = 0x10200/4, /* general rx control */
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/* interrupt */
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Icr = 0x00800/4, /* interrupt cause read */
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Ics = 0x00808/4, /* " set */
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Ims = 0x00880/4, /* " mask read/set */
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Imc = 0x00888/4, /* " mask clear */
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Iac = 0x00810/4, /* " ayto clear */
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Iam = 0x00890/4, /* " auto mask enable */
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Itr = 0x00820/4, /* " throttling rate (0-19) */
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Ivar = 0x00900/4, /* " vector allocation regs. */
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/* msi interrupt */
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Msixt = 0x0000/4, /* msix table (bar3) */
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Msipba = 0x2000/4, /* msix pending bit array (bar3) */
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Pbacl = 0x11068/4, /* pba clear */
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Gpie = 0x00898/4, /* general purpose int enable */
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/* flow control */
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Pfctop = 0x03008/4, /* priority flow ctl type opcode */
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Fcttv = 0x03200/4, /* " transmit timer value (0-3) */
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Fcrtl = 0x03220/4, /* " rx threshold low (0-7) +8n */
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Fcrth = 0x03260/4, /* " rx threshold high (0-7) +8n */
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Rcrtv = 0x032a0/4, /* " refresh value threshold */
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Tfcs = 0x0ce00/4, /* " tx status */
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/* rx dma */
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Rbal = 0x01000/4, /* rx desc base low (0-63) +0x40n */
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Rbah = 0x01004/4, /* " high */
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Rdlen = 0x01008/4, /* " length */
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Rdh = 0x01010/4, /* " head */
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Rdt = 0x01018/4, /* " tail */
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Rxdctl = 0x01028/4, /* " control */
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Srrctl = 0x02100/4, /* split and replication rx ctl. */
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Dcarxctl = 0x02200/4, /* rx dca control */
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Rdrxctl = 0x02f00/4, /* rx dma control */
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Rxpbsize = 0x03c00/4, /* rx packet buffer size */
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Rxctl = 0x03000/4, /* rx control */
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Dropen = 0x03d04/4, /* drop enable control */
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/* rx */
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Rxcsum = 0x05000/4, /* rx checksum control */
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Rfctl = 0x04008/4, /* rx filter control */
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Mta = 0x05200/4, /* multicast table array (0-127) */
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Ral = 0x05400/4, /* rx address low */
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Rah = 0x05404/4,
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Psrtype = 0x05480/4, /* packet split rx type. */
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Vfta = 0x0a000/4, /* vlan filter table array. */
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Fctrl = 0x05080/4, /* filter control */
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Vlnctrl = 0x05088/4, /* vlan control */
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Msctctrl = 0x05090/4, /* multicast control */
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Mrqc = 0x05818/4, /* multiple rx queues cmd */
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Vmdctl = 0x0581c/4, /* vmdq control */
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Imir = 0x05a80/4, /* immediate irq rx (0-7) */
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Imirext = 0x05aa0/4, /* immediate irq rx ext */
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Imirvp = 0x05ac0/4, /* immediate irq vlan priority */
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Reta = 0x05c00/4, /* redirection table */
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Rssrk = 0x05c80/4, /* rss random key */
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/* tx */
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Tdbal = 0x06000/4, /* tx desc base low +0x40n */
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Tdbah = 0x06004/4, /* " high */
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Tdlen = 0x06008/4, /* " len */
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Tdh = 0x06010/4, /* " head */
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Tdt = 0x06018/4, /* " tail */
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Txdctl = 0x06028/4, /* " control */
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Tdwbal = 0x06038/4, /* " write-back address low */
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Tdwbah = 0x0603c/4,
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Dmatxctl = 0x04a80/4,
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Dtxctl = 0x07e00/4, /* tx dma control */
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Tdcatxctrl = 0x07200/4, /* tx dca register (0-15) */
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Tipg = 0x0cb00/4, /* tx inter-packet gap */
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Txpbsize = 0x0cc00/4, /* tx packet-buffer size (0-15) */
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/* mac */
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Hlreg0 = 0x04240/4, /* highlander control reg 0 */
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Hlreg1 = 0x04244/4, /* highlander control reg 1 (ro) */
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Msca = 0x0425c/4, /* mdi signal cmd & addr */
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Msrwd = 0x04260/4, /* mdi single rw data */
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Mhadd = 0x04268/4, /* mac addr high & max frame */
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Pcss1 = 0x04288/4, /* xgxs status 1 */
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Pcss2 = 0x0428c/4,
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Xpcss = 0x04290/4, /* 10gb-x pcs status */
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Serdesc = 0x04298/4, /* serdes control */
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Macs = 0x0429c/4, /* fifo control & report */
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Autoc = 0x042a0/4, /* autodetect control & status */
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Links = 0x042a4/4, /* link status */
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Autoc2 = 0x042a8/4,
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};
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enum {
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/* Ctrl */
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Rst = 1<<26, /* full nic reset */
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/* Txdctl */
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Ten = 1<<25,
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/* Fctrl */
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Bam = 1<<10, /* broadcast accept mode */
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Upe = 1<<9, /* unicast promiscuous */
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Mpe = 1<<8, /* multicast promiscuous */
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/* Rxdctl */
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Pthresh = 0, /* prefresh threshold shift in bits */
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Hthresh = 8, /* host buffer minimum threshold " */
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Wthresh = 16, /* writeback threshold */
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Renable = 1<<25,
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/* Dmatxctl */
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Txen = 1<<0,
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/* Rxctl */
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Rxen = 1<<0,
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Dmbyps = 1<<1,
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/* Rdrxctl */
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Rdmt½ = 0,
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Rdmt¼ = 1,
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Rdmt⅛ = 2,
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/* Rxcsum */
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Ippcse = 1<<12, /* ip payload checksum enable */
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/* Eerd */
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EEstart = 1<<0, /* Start Read */
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EEdone = 1<<1, /* Read done */
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/* interrupts */
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Irx0 = 1<<0, /* driver defined */
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Itx0 = 1<<1, /* driver defined */
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Lsc = 1<<20, /* link status change */
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/* Links */
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Lnkup = 1<<30,
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Lnkspd = 1<<29,
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/* Hlreg0 */
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Jumboen = 1<<2,
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};
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typedef struct {
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uint reg;
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char *name;
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} Stat;
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Stat stattab[] = {
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0x4000, "crc error",
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0x4004, "illegal byte",
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0x4008, "short packet",
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0x3fa0, "missed pkt0",
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0x4034, "mac local flt",
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0x4038, "mac rmt flt",
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0x4040, "rx length err",
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0x3f60, "xon tx",
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0xcf60, "xon rx",
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0x3f68, "xoff tx",
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0xcf68, "xoff rx",
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0x405c, "rx 040",
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0x4060, "rx 07f",
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0x4064, "rx 100",
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0x4068, "rx 200",
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0x406c, "rx 3ff",
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0x4070, "rx big",
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0x4074, "rx ok",
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0x4078, "rx bcast",
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0x3fc0, "rx no buf0",
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0x40a4, "rx runt",
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0x40a8, "rx frag",
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0x40ac, "rx ovrsz",
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0x40b0, "rx jab",
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0x40d0, "rx pkt",
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0x40d4, "tx pkt",
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0x40d8, "tx 040",
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0x40dc, "tx 07f",
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0x40e0, "tx 100",
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0x40e4, "tx 200",
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0x40e8, "tx 3ff",
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0x40ec, "tx big",
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0x40f4, "tx bcast",
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0x4120, "xsum err",
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};
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/* status */
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enum {
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Pif = 1<<7, /* past exact filter (sic) */
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Ipcs = 1<<6, /* ip checksum calcuated */
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L4cs = 1<<5, /* layer 2 */
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Tcpcs = 1<<4, /* tcp checksum calcuated */
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Vp = 1<<3, /* 802.1q packet matched vet */
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Ixsm = 1<<2, /* ignore checksum */
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Reop = 1<<1, /* end of packet */
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Rdd = 1<<0, /* descriptor done */
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};
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typedef struct {
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u32int addr[2];
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ushort length;
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ushort cksum;
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uchar status;
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uchar errors;
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ushort vlan;
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} Rd;
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enum {
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/* Td cmd */
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Rs = 1<<3,
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Ic = 1<<2,
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Ifcs = 1<<1,
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Teop = 1<<0,
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/* Td status */
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Tdd = 1<<0,
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};
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typedef struct {
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u32int addr[2];
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ushort length;
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uchar cso;
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uchar cmd;
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uchar status;
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uchar css;
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ushort vlan;
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} Td;
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enum {
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Factive = 1<<0,
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Fstarted = 1<<1,
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};
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typedef struct {
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Pcidev *p;
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Ether *edev;
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uintptr io;
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u32int *reg;
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u32int *regmsi;
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uchar flag;
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int nrd;
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int ntd;
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int rbsz;
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Lock slock;
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Lock alock;
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QLock tlock;
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Rendez lrendez;
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Rendez trendez;
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Rendez rrendez;
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uint im;
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uint lim;
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uint rim;
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uint tim;
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Lock imlock;
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char *alloc;
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Rd *rdba;
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Block **rb;
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uint rdt;
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uint rdfree;
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Td *tdba;
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uint tdh;
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uint tdt;
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Block **tb;
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uchar ra[Eaddrlen];
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u32int mta[128];
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ulong stats[nelem(stattab)];
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uint speeds[3];
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} Ctlr;
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/* tweakable paramaters */
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enum {
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Mtu = 12*1024,
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Nrd = 256,
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Ntd = 256,
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Nrb = 256,
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};
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static Ctlr *ctlrtab[4];
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static int nctlr;
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static void
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readstats(Ctlr *c)
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{
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int i;
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lock(&c->slock);
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for(i = 0; i < nelem(c->stats); i++)
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c->stats[i] += c->reg[stattab[i].reg >> 2];
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unlock(&c->slock);
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}
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static int speedtab[] = {
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0,
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1000,
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10000,
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};
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static long
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ifstat(Ether *e, void *a, long n, ulong offset)
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{
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uint i, *t;
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char *s, *p, *q;
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Ctlr *c;
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p = s = smalloc(READSTR);
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q = p + READSTR;
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c = e->ctlr;
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readstats(c);
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for(i = 0; i < nelem(stattab); i++)
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if(c->stats[i] > 0)
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p = seprint(p, q, "%.10s %uld\n", stattab[i].name, c->stats[i]);
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t = c->speeds;
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p = seprint(p, q, "speeds: 0:%d 1000:%d 10000:%d\n", t[0], t[1], t[2]);
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seprint(p, q, "rdfree %d rdh %d rdt %d\n", c->rdfree, c->reg[Rdt],
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c->reg[Rdh]);
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n = readstr(offset, a, n, s);
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free(s);
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return n;
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}
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static void
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im(Ctlr *c, int i)
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{
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ilock(&c->imlock);
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c->im |= i;
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c->reg[Ims] = c->im;
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iunlock(&c->imlock);
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}
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static int
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lim(void *v)
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{
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return ((Ctlr*)v)->lim != 0;
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}
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static void
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lproc(void *v)
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{
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int r, i;
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Ctlr *c;
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Ether *e;
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e = v;
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c = e->ctlr;
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while(waserror())
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;
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for (;;) {
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r = c->reg[Links];
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e->link = (r & Lnkup) != 0;
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i = 0;
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if(e->link)
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i = 1 + ((r & Lnkspd) != 0);
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c->speeds[i]++;
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e->mbps = speedtab[i];
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c->lim = 0;
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im(c, Lsc);
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sleep(&c->lrendez, lim, c);
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c->lim = 0;
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}
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}
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static long
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ctl(Ether *, void *, long)
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{
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error(Ebadarg);
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return -1;
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}
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#define Next(x, m) (((x)+1) & (m))
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static int
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cleanup(Ctlr *c, int tdh)
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{
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Block *b;
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uint m, n;
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m = c->ntd - 1;
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while(c->tdba[n = Next(tdh, m)].status & Tdd){
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tdh = n;
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b = c->tb[tdh];
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c->tb[tdh] = 0;
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freeb(b);
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c->tdba[tdh].status = 0;
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}
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return tdh;
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}
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void
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transmit(Ether *e)
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{
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uint i, m, tdt, tdh;
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Ctlr *c;
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Block *b;
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Td *t;
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c = e->ctlr;
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if(!canqlock(&c->tlock)){
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im(c, Itx0);
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return;
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}
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tdh = c->tdh = cleanup(c, c->tdh);
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tdt = c->tdt;
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m = c->ntd - 1;
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for(i = 0; i < 8; i++){
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if(Next(tdt, m) == tdh){
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im(c, Itx0);
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break;
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}
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if(!(b = qget(e->oq)))
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break;
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t = c->tdba + tdt;
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t->addr[0] = PCIWADDR(b->rp);
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t->length = BLEN(b);
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t->cmd = Rs | Ifcs | Teop;
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c->tb[tdt] = b;
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tdt = Next(tdt, m);
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}
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if(i){
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c->tdt = tdt;
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c->reg[Tdt] = tdt;
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}
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qunlock(&c->tlock);
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}
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static int
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tim(void *c)
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{
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return ((Ctlr*)c)->tim != 0;
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}
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static void
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tproc(void *v)
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{
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Ctlr *c;
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Ether *e;
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e = v;
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c = e->ctlr;
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while(waserror())
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;
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for (;;) {
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sleep(&c->trendez, tim, c); /* transmit kicks us */
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c->tim = 0;
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transmit(e);
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}
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}
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static void
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rxinit(Ctlr *c)
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{
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int i;
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Block *b;
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c->reg[Rxctl] &= ~Rxen;
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for(i = 0; i < c->nrd; i++){
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b = c->rb[i];
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c->rb[i] = 0;
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if(b)
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freeb(b);
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}
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c->rdfree = 0;
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c->reg[Fctrl] |= Bam;
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c->reg[Rxcsum] |= Ipcs;
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c->reg[Srrctl] = c->rbsz / 1024;
|
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c->reg[Mhadd] = c->rbsz << 16;
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c->reg[Hlreg0] |= Jumboen;
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c->reg[Rbal] = PCIWADDR(c->rdba);
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c->reg[Rbah] = 0;
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c->reg[Rdlen] = c->nrd*sizeof(Rd);
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c->reg[Rdh] = 0;
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c->reg[Rdt] = c->rdt = 0;
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c->reg[Rdrxctl] = Rdmt¼;
|
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c->reg[Rxdctl] = 8<<Wthresh | 8<<Pthresh | 4<<Hthresh | Renable;
|
|
c->reg[Rxctl] |= Rxen | Dmbyps;
|
|
}
|
|
|
|
static void
|
|
replenish(Ctlr *c, uint rdh)
|
|
{
|
|
int rdt, m, i;
|
|
Block *b;
|
|
Rd *r;
|
|
|
|
m = c->nrd - 1;
|
|
i = 0;
|
|
for(rdt = c->rdt; Next(rdt, m) != rdh; rdt = Next(rdt, m)){
|
|
b = allocb(c->rbsz+BY2PG);
|
|
b->rp = (uchar*)PGROUND((uintptr)b->base);
|
|
b->wp = b->rp;
|
|
c->rb[rdt] = b;
|
|
r = c->rdba + rdt;
|
|
r->addr[0] = PCIWADDR(b->rp);
|
|
r->status = 0;
|
|
c->rdfree++;
|
|
i++;
|
|
}
|
|
if(i)
|
|
c->reg[Rdt] = c->rdt = rdt;
|
|
}
|
|
|
|
static int
|
|
rim(void *v)
|
|
{
|
|
return ((Ctlr*)v)->rim != 0;
|
|
}
|
|
|
|
static uchar zeroea[Eaddrlen];
|
|
|
|
void
|
|
rproc(void *v)
|
|
{
|
|
uint m, rdh;
|
|
Block *b;
|
|
Ctlr *c;
|
|
Ether *e;
|
|
Rd *r;
|
|
|
|
e = v;
|
|
c = e->ctlr;
|
|
m = c->nrd - 1;
|
|
rdh = 0;
|
|
while(waserror())
|
|
;
|
|
loop:
|
|
replenish(c, rdh);
|
|
im(c, Irx0);
|
|
sleep(&c->rrendez, rim, c);
|
|
loop1:
|
|
c->rim = 0;
|
|
if(c->nrd - c->rdfree >= 16)
|
|
replenish(c, rdh);
|
|
r = c->rdba + rdh;
|
|
if(!(r->status & Rdd))
|
|
goto loop; /* UGH */
|
|
b = c->rb[rdh];
|
|
c->rb[rdh] = 0;
|
|
b->wp += r->length;
|
|
if(!(r->status & Ixsm)){
|
|
if(r->status & Ipcs)
|
|
b->flag |= Bipck;
|
|
if(r->status & Tcpcs)
|
|
b->flag |= Btcpck | Budpck;
|
|
b->checksum = r->cksum;
|
|
}
|
|
// r->status = 0;
|
|
etheriq(e, b);
|
|
c->rdfree--;
|
|
rdh = Next(rdh, m);
|
|
goto loop1; /* UGH */
|
|
}
|
|
|
|
static void
|
|
promiscuous(void *a, int on)
|
|
{
|
|
Ctlr *c;
|
|
Ether *e;
|
|
|
|
e = a;
|
|
c = e->ctlr;
|
|
if(on)
|
|
c->reg[Fctrl] |= Upe | Mpe;
|
|
else
|
|
c->reg[Fctrl] &= ~(Upe | Mpe);
|
|
}
|
|
|
|
static void
|
|
multicast(void *a, uchar *ea, int on)
|
|
{
|
|
int b, i;
|
|
Ctlr *c;
|
|
Ether *e;
|
|
|
|
e = a;
|
|
c = e->ctlr;
|
|
|
|
/*
|
|
* multiple ether addresses can hash to the same filter bit,
|
|
* so it's never safe to clear a filter bit.
|
|
* if we want to clear filter bits, we need to keep track of
|
|
* all the multicast addresses in use, clear all the filter bits,
|
|
* then set the ones corresponding to in-use addresses.
|
|
*/
|
|
i = ea[5] >> 1;
|
|
b = (ea[5]&1)<<4 | ea[4]>>4;
|
|
b = 1 << b;
|
|
if(on)
|
|
c->mta[i] |= b;
|
|
// else
|
|
// c->mta[i] &= ~b;
|
|
c->reg[Mta+i] = c->mta[i];
|
|
}
|
|
|
|
static int
|
|
detach(Ctlr *c)
|
|
{
|
|
int i;
|
|
|
|
c->reg[Imc] = ~0;
|
|
c->reg[Ctrl] |= Rst;
|
|
for(i = 0; i < 100; i++){
|
|
delay(1);
|
|
if((c->reg[Ctrl] & Rst) == 0)
|
|
break;
|
|
}
|
|
if (i >= 100)
|
|
return -1;
|
|
/* errata */
|
|
delay(50);
|
|
c->reg[Ecc] &= ~(1<<21 | 1<<18 | 1<<9 | 1<<6);
|
|
|
|
/* not cleared by reset; kill it manually. */
|
|
for(i = 1; i < 16; i++)
|
|
c->reg[Rah] &= ~(1 << 31);
|
|
for(i = 0; i < 128; i++)
|
|
c->reg[Mta + i] = 0;
|
|
for(i = 1; i < 640; i++)
|
|
c->reg[Vfta + i] = 0;
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
shutdown(Ether *e)
|
|
{
|
|
detach(e->ctlr);
|
|
}
|
|
|
|
/* ≤ 20ms */
|
|
static ushort
|
|
eeread(Ctlr *c, int i)
|
|
{
|
|
c->reg[Eerd] = EEstart | i<<2;
|
|
while((c->reg[Eerd] & EEdone) == 0)
|
|
;
|
|
return c->reg[Eerd] >> 16;
|
|
}
|
|
|
|
static int
|
|
eeload(Ctlr *c)
|
|
{
|
|
ushort u, v, p, l, i, j;
|
|
|
|
if((eeread(c, 0) & 0xc0) != 0x40)
|
|
return -1;
|
|
u = 0;
|
|
for(i = 0; i < 0x40; i++)
|
|
u += eeread(c, i);
|
|
for(i = 3; i < 0xf; i++){
|
|
p = eeread(c, i);
|
|
l = eeread(c, p++);
|
|
if((int)p + l + 1 > 0xffff)
|
|
continue;
|
|
for(j = p; j < p + l; j++)
|
|
u += eeread(c, j);
|
|
}
|
|
if(u != 0xbaba)
|
|
return -1;
|
|
if(c->reg[Status] & (1<<3))
|
|
u = eeread(c, 10);
|
|
else
|
|
u = eeread(c, 9);
|
|
u++;
|
|
for(i = 0; i < Eaddrlen;){
|
|
v = eeread(c, u + i/2);
|
|
c->ra[i++] = v;
|
|
c->ra[i++] = v>>8;
|
|
}
|
|
c->ra[5] += (c->reg[Status] & 0xc) >> 2;
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
reset(Ctlr *c)
|
|
{
|
|
int i;
|
|
|
|
if(detach(c)){
|
|
print("82598: reset timeout\n");
|
|
return -1;
|
|
}
|
|
if(eeload(c)){
|
|
print("82598: eeprom failure\n");
|
|
memset(c->ra, 0, Eaddrlen);
|
|
}
|
|
|
|
readstats(c);
|
|
for(i = 0; i<nelem(c->stats); i++)
|
|
c->stats[i] = 0;
|
|
|
|
c->reg[Ctrlext] |= 1 << 16;
|
|
/* make some guesses for flow control */
|
|
c->reg[Fcrtl] = 0x10000 | 1<<31;
|
|
c->reg[Fcrth] = 0x40000 | 1<<31;
|
|
c->reg[Rcrtv] = 0x6000;
|
|
|
|
/* configure interrupt mapping (don't ask) */
|
|
c->reg[Ivar+0] = 0 | 1<<7;
|
|
c->reg[Ivar+64/4] = 1 | 1<<7;
|
|
// c->reg[Ivar+97/4] = (2 | 1<<7) << (8*(97%4));
|
|
|
|
/* interrupt throttling goes here. */
|
|
for(i = Itr; i < Itr + 20; i++)
|
|
c->reg[i] = 128; /* ¼µs intervals */
|
|
c->reg[Itr + Itx0] = 256;
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
txinit(Ctlr *c)
|
|
{
|
|
Block *b;
|
|
int i;
|
|
|
|
c->reg[Txdctl] = 16<<Wthresh | 16<<Pthresh;
|
|
for(i = 0; i < c->ntd; i++){
|
|
b = c->tb[i];
|
|
c->tb[i] = 0;
|
|
if(b)
|
|
freeb(b);
|
|
}
|
|
memset(c->tdba, 0, c->ntd * sizeof(Td));
|
|
c->reg[Tdbal] = PCIWADDR(c->tdba);
|
|
c->reg[Tdbah] = 0;
|
|
c->reg[Tdlen] = c->ntd*sizeof(Td);
|
|
c->reg[Tdh] = 0;
|
|
c->reg[Tdt] = 0;
|
|
c->tdh = c->ntd - 1;
|
|
c->tdt = 0;
|
|
c->reg[Txdctl] |= Ten;
|
|
|
|
c->reg[Dmatxctl] |= Txen;
|
|
}
|
|
|
|
static void
|
|
attach(Ether *e)
|
|
{
|
|
Ctlr *c;
|
|
int t;
|
|
char buf[KNAMELEN];
|
|
|
|
c = e->ctlr;
|
|
c->edev = e; /* point back to Ether* */
|
|
lock(&c->alock);
|
|
if(c->alloc){
|
|
unlock(&c->alock);
|
|
return;
|
|
}
|
|
|
|
c->nrd = Nrd;
|
|
c->ntd = Ntd;
|
|
t = c->nrd * sizeof *c->rdba + 255;
|
|
t += c->ntd * sizeof *c->tdba + 255;
|
|
t += (c->ntd + c->nrd) * sizeof(Block*);
|
|
c->alloc = malloc(t);
|
|
unlock(&c->alock);
|
|
if(c->alloc == nil)
|
|
error(Enomem);
|
|
|
|
c->rdba = (Rd*)ROUNDUP((uintptr)c->alloc, 256);
|
|
c->tdba = (Td*)ROUNDUP((uintptr)(c->rdba + c->nrd), 256);
|
|
c->rb = (Block**)(c->tdba + c->ntd);
|
|
c->tb = (Block**)(c->rb + c->nrd);
|
|
|
|
rxinit(c);
|
|
txinit(c);
|
|
|
|
snprint(buf, sizeof buf, "#l%dl", e->ctlrno);
|
|
kproc(buf, lproc, e);
|
|
snprint(buf, sizeof buf, "#l%dr", e->ctlrno);
|
|
kproc(buf, rproc, e);
|
|
snprint(buf, sizeof buf, "#l%dt", e->ctlrno);
|
|
kproc(buf, tproc, e);
|
|
}
|
|
|
|
static void
|
|
interrupt(Ureg*, void *v)
|
|
{
|
|
int icr, im;
|
|
Ctlr *c;
|
|
Ether *e;
|
|
|
|
e = v;
|
|
c = e->ctlr;
|
|
ilock(&c->imlock);
|
|
c->reg[Imc] = ~0;
|
|
im = c->im;
|
|
while((icr = c->reg[Icr] & c->im) != 0){
|
|
if(icr & Lsc){
|
|
im &= ~Lsc;
|
|
c->lim = icr & Lsc;
|
|
wakeup(&c->lrendez);
|
|
}
|
|
if(icr & Irx0){
|
|
im &= ~Irx0;
|
|
c->rim = icr & Irx0;
|
|
wakeup(&c->rrendez);
|
|
}
|
|
if(icr & Itx0){
|
|
im &= ~Itx0;
|
|
c->tim = icr & Itx0;
|
|
wakeup(&c->trendez);
|
|
}
|
|
}
|
|
c->reg[Ims] = c->im = im;
|
|
iunlock(&c->imlock);
|
|
}
|
|
|
|
static void
|
|
scan(void)
|
|
{
|
|
uintptr io, iomsi;
|
|
void *mem, *memmsi;
|
|
int pciregs, pcimsix;
|
|
Ctlr *c;
|
|
Pcidev *p;
|
|
|
|
p = 0;
|
|
while(p = pcimatch(p, 0x8086, 0)){
|
|
switch(p->did){
|
|
case 0x10c6: /* 82598 af dual port */
|
|
case 0x10c7: /* 82598 af single port */
|
|
case 0x10b6: /* 82598 backplane */
|
|
case 0x10dd: /* 82598 at cx4 */
|
|
case 0x10ec: /* 82598 at cx4 dual port */
|
|
pcimsix = 3;
|
|
break;
|
|
case 0x10fb: /* 82599 */
|
|
case 0x1528: /* T540-T1 */
|
|
pcimsix = 4;
|
|
break;
|
|
|
|
default:
|
|
continue;
|
|
}
|
|
pciregs = 0;
|
|
if(nctlr == nelem(ctlrtab)){
|
|
print("i82598: too many controllers\n");
|
|
return;
|
|
}
|
|
c = malloc(sizeof *c);
|
|
if(c == nil){
|
|
print("i82598: can't allocate memory\n");
|
|
continue;
|
|
}
|
|
io = p->mem[pciregs].bar & ~0xf;
|
|
mem = vmap(io, p->mem[pciregs].size);
|
|
if(mem == nil){
|
|
print("i82598: can't map regs %#p\n", io);
|
|
free(c);
|
|
continue;
|
|
}
|
|
iomsi = p->mem[pcimsix].bar & ~0xf;
|
|
memmsi = vmap(iomsi, p->mem[pcimsix].size);
|
|
if(memmsi == nil){
|
|
print("i82598: can't map msi-x regs %#p\n", iomsi);
|
|
vunmap(mem, p->mem[pciregs].size);
|
|
free(c);
|
|
continue;
|
|
}
|
|
pcienable(p);
|
|
c->p = p;
|
|
c->io = io;
|
|
c->reg = (u32int*)mem;
|
|
c->regmsi = (u32int*)memmsi;
|
|
c->rbsz = ROUND(Mtu, 1024);
|
|
if(reset(c)){
|
|
print("i82598: can't reset\n");
|
|
free(c);
|
|
vunmap(mem, p->mem[pciregs].size);
|
|
vunmap(memmsi, p->mem[pcimsix].size);
|
|
continue;
|
|
}
|
|
pcisetbme(p);
|
|
ctlrtab[nctlr++] = c;
|
|
}
|
|
}
|
|
|
|
static int
|
|
pnp(Ether *e)
|
|
{
|
|
static uchar zeros[Eaddrlen];
|
|
int i;
|
|
Ctlr *c = nil;
|
|
uchar *p;
|
|
|
|
if(nctlr == 0)
|
|
scan();
|
|
for(i = 0; i < nctlr; i++){
|
|
c = ctlrtab[i];
|
|
if(c == nil || c->flag & Factive)
|
|
continue;
|
|
if(e->port == 0 || e->port == c->io)
|
|
break;
|
|
}
|
|
if (i >= nctlr)
|
|
return -1;
|
|
|
|
if(memcmp(c->ra, zeros, Eaddrlen) != 0)
|
|
memmove(e->ea, c->ra, Eaddrlen);
|
|
|
|
p = e->ea;
|
|
c->reg[Ral] = p[3]<<24 | p[2]<<16 | p[1]<<8 | p[0];
|
|
c->reg[Rah] = p[5]<<8 | p[4] | 1<<31;
|
|
|
|
c->flag |= Factive;
|
|
e->ctlr = c;
|
|
e->port = (uintptr)c->reg;
|
|
e->irq = c->p->intl;
|
|
e->tbdf = c->p->tbdf;
|
|
e->mbps = 10000;
|
|
e->maxmtu = Mtu;
|
|
|
|
e->arg = e;
|
|
e->attach = attach;
|
|
e->ctl = ctl;
|
|
e->ifstat = ifstat;
|
|
e->multicast = multicast;
|
|
e->promiscuous = promiscuous;
|
|
e->shutdown = shutdown;
|
|
e->transmit = transmit;
|
|
|
|
intrenable(e->irq, interrupt, e, e->tbdf, e->name);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ether82598link(void)
|
|
{
|
|
addethercard("i82598", pnp);
|
|
}
|