347ac6ef58
use fastclock timer (pit2) to measure cpufreq in guesscpuhz(). this gives a bigger period minimizing the danger of overrun as pit2 runs at the constant maximum period of 0x10000 ticks. also use smaller loop increments (1000) and bigger maximum loop upper bound. move the loops < ... check to the bottom of the loop so we get the effective count *before* adding the next loop increment. ilock() while doing measurements in guesscpuhz() to prevent accidents with other processors reading fastclock or doing guesscpuhz() in parralel. export new i8253reset() function for apm to reset the timers after a apm bios suspend.
161 lines
3.8 KiB
C
161 lines
3.8 KiB
C
/*
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* Interface to Advanced Power Management 1.2 BIOS
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*
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* This is, in many ways, a giant hack, and when things settle down
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* a bit and standardize, hopefully we can write a driver that deals
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* more directly with the hardware and thus might be a bit cleaner.
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*
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* ACPI might be the answer, but at the moment this is simpler
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* and more widespread.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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extern int apmfarcall(ushort, ulong, Ureg*); /* apmjump.s */
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static int
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getreg(ulong *reg, ISAConf *isa, char *name)
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{
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int i;
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int nl;
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nl = strlen(name);
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for(i=0; i<isa->nopt; i++){
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if(cistrncmp(isa->opt[i], name, nl)==0 && isa->opt[i][nl] == '='){
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*reg = strtoul(isa->opt[i]+nl+1, nil, 16);
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return 0;
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}
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}
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return -1;
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}
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/*
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* Segment descriptors look like this.
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*
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* d1: [base 31:24] [gran] [is32bit] [0] [unused] [limit 19:16]
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[present] [privlev] [type 3:0] [base 23:16]
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* d0: [base 15:00] [limit 15:00]
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*
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* gran is 0 for 1-byte granularity, 1 for 4k granularity
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* type is 0 for system segment, 1 for code/data.
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*
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* clearly we know way too much about the memory unit.
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* however, knowing this much about the memory unit
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* means that the memory unit need not know anything
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* about us.
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*
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* what a crock.
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*/
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static void
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setgdt(int sel, ulong base, ulong limit, int flag)
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{
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if(sel < 0 || sel >= NGDT)
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panic("setgdt");
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base = (ulong)KADDR(base);
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m->gdt[sel].d0 = (base<<16) | (limit&0xFFFF);
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m->gdt[sel].d1 = (base&0xFF000000) | (limit&0x000F0000) |
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((base>>16)&0xFF) | SEGP | SEGPL(0) | flag;
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}
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static ulong ax, cx, dx, di, ebx, esi;
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static Ureg apmu;
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static long
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apmread(Chan*, void *a, long n, vlong off)
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{
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if(off < 0)
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error("badarg");
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if(n+off > sizeof apmu)
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n = sizeof apmu - off;
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if(n <= 0)
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return 0;
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memmove(a, (char*)&apmu+off, n);
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return n;
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}
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static long
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apmwrite(Chan*, void *a, long n, vlong off)
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{
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int s, needreset;
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if(off || n != sizeof apmu)
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error("write a Ureg");
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memmove(&apmu, a, sizeof apmu);
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needreset = apmu.ax==0x5307; /* set power state */
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s = splhi();
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apmfarcall(APMCSEL, ebx, &apmu);
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if(needreset){
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/*
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* some BIOS disable the timers. have to
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* reset them after suspend.
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*/
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splhi();
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i8253reset();
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}
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splx(s);
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return n;
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}
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void
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apmlink(void)
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{
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ISAConf isa;
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char *s;
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if(isaconfig("apm", 0, &isa) == 0)
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return;
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/*
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* APM info passed from boot loader.
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* Now we need to set up the GDT entries for APM.
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*
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* AX = 32-bit code segment base address
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* EBX = 32-bit code segment offset
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* CX = 16-bit code segment base address
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* DX = 32-bit data segment base address
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* ESI = <16-bit code segment length> <32-bit code segment length> (hi then lo)
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* DI = 32-bit data segment length
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*/
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if(getreg(&ax, &isa, s="ax") < 0
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|| getreg(&ebx, &isa, s="ebx") < 0
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|| getreg(&cx, &isa, s="cx") < 0
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|| getreg(&dx, &isa, s="dx") < 0
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|| getreg(&esi, &isa, s="esi") < 0
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|| getreg(&di, &isa, s="di") < 0){
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print("apm: missing register %s\n", s);
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return;
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}
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/*
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* The NEC Versa SX bios does not report the correct 16-bit code
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* segment length when loaded directly from mbr -> 9load (as compared
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* with going through ld.com). We'll make both code segments 64k-1 bytes.
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*/
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esi = 0xFFFFFFFF;
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/*
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* We are required by the BIOS to set up three consecutive segments,
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* one for the APM 32-bit code, one for the APM 16-bit code, and
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* one for the APM data. The BIOS handler uses the code segment it
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* get called with to determine the other two segment selector.
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*/
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setgdt(APMCSEG, ax<<4, ((esi&0xFFFF)-1)&0xFFFF, SEGEXEC|SEGR|SEGD);
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setgdt(APMCSEG16, cx<<4, ((esi>>16)-1)&0xFFFF, SEGEXEC|SEGR);
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setgdt(APMDSEG, dx<<4, (di-1)&0xFFFF, SEGDATA|SEGW|SEGD);
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addarchfile("apm", 0660, apmread, apmwrite);
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print("apm: configured cbase %.8lux off %.8lux\n", ax<<4, ebx);
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return;
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}
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