1123 lines
23 KiB
C
1123 lines
23 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/error.h"
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enum {
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Qdir = 0,
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Qiob,
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Qiow,
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Qiol,
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Qmsr,
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Qbase,
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Qmax = 32,
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};
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enum { /* cpuid standard function codes */
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Highstdfunc = 0, /* also returns vendor string */
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Procsig,
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Proctlbcache,
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Procserial,
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Highextfunc = 0x80000000,
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Procextfeat,
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};
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typedef long Rdwrfn(Chan*, void*, long, vlong);
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static Rdwrfn *readfn[Qmax];
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static Rdwrfn *writefn[Qmax];
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static Dirtab archdir[Qmax] = {
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".", { Qdir, 0, QTDIR }, 0, 0555,
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"iob", { Qiob, 0 }, 0, 0660,
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"iow", { Qiow, 0 }, 0, 0660,
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"iol", { Qiol, 0 }, 0, 0660,
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"msr", { Qmsr, 0 }, 0, 0660,
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};
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Lock archwlock; /* the lock is only for changing archdir */
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int narchdir = Qbase;
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int (*_pcmspecial)(char*, ISAConf*);
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void (*_pcmspecialclose)(int);
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/*
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* Add a file to the #P listing. Once added, you can't delete it.
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* You can't add a file with the same name as one already there,
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* and you get a pointer to the Dirtab entry so you can do things
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* like change the Qid version. Changing the Qid path is disallowed.
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*/
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Dirtab*
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addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
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{
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int i;
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Dirtab d;
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Dirtab *dp;
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memset(&d, 0, sizeof d);
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strcpy(d.name, name);
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d.perm = perm;
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lock(&archwlock);
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if(narchdir >= Qmax){
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unlock(&archwlock);
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print("addarchfile: out of entries for %s\n", name);
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return nil;
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}
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for(i=0; i<narchdir; i++)
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if(strcmp(archdir[i].name, name) == 0){
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unlock(&archwlock);
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return nil;
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}
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d.qid.path = narchdir;
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archdir[narchdir] = d;
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readfn[narchdir] = rdfn;
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writefn[narchdir] = wrfn;
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dp = &archdir[narchdir++];
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unlock(&archwlock);
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return dp;
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}
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void
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ioinit(void)
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{
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char *excluded;
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iomapinit(0xffff);
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/*
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* This is necessary to make the IBM X20 boot.
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* Have not tracked down the reason.
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* i82557 is at 0x1000, the dummy entry is needed for swappable devs.
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*/
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ioalloc(0x0fff, 1, 0, "dummy");
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if ((excluded = getconf("ioexclude")) != nil) {
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char *s;
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s = excluded;
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while (s && *s != '\0' && *s != '\n') {
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char *ends;
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int io_s, io_e;
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io_s = (int)strtol(s, &ends, 0);
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if (ends == nil || ends == s || *ends != '-') {
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print("ioinit: cannot parse option string\n");
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break;
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}
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s = ++ends;
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io_e = (int)strtol(s, &ends, 0);
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if (ends && *ends == ',')
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*ends++ = '\0';
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s = ends;
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ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
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}
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}
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}
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static void
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checkport(ulong start, ulong end)
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{
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if(end < start || end > 0x10000)
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error(Ebadarg);
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/* standard vga regs are OK */
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if(start >= 0x2b0 && end <= 0x2df+1)
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return;
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if(start >= 0x3c0 && end <= 0x3da+1)
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return;
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if(iounused(start, end))
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return;
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error(Eperm);
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}
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static Chan*
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archattach(char* spec)
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{
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return devattach('P', spec);
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}
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Walkqid*
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archwalk(Chan* c, Chan *nc, char** name, int nname)
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{
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return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
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}
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static int
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archstat(Chan* c, uchar* dp, int n)
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{
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return devstat(c, dp, n, archdir, narchdir, devgen);
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}
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static Chan*
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archopen(Chan* c, int omode)
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{
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return devopen(c, omode, archdir, narchdir, devgen);
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}
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static void
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archclose(Chan*)
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{
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}
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static long
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archread(Chan *c, void *a, long n, vlong offset)
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{
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ulong port, end;
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uchar *cp;
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ushort *sp;
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ulong *lp;
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vlong *vp;
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Rdwrfn *fn;
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port = offset;
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end = port+n;
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switch((ulong)c->qid.path){
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case Qdir:
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return devdirread(c, a, n, archdir, narchdir, devgen);
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case Qiob:
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checkport(port, end);
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for(cp = a; port < end; port++)
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*cp++ = inb(port);
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return n;
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case Qiow:
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if(n & 1)
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error(Ebadarg);
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checkport(port, end);
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for(sp = a; port < end; port += 2)
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*sp++ = ins(port);
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return n;
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case Qiol:
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if(n & 3)
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error(Ebadarg);
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checkport(port, end);
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for(lp = a; port < end; port += 4)
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*lp++ = inl(port);
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return n;
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case Qmsr:
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if(n & 7)
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error(Ebadarg);
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if((ulong)n/8 > -port)
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error(Ebadarg);
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end = port+(n/8);
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for(vp = a; port != end; port++)
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if(rdmsr(port, vp++) < 0)
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error(Ebadarg);
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return n;
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default:
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if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
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return fn(c, a, n, offset);
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error(Eperm);
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return 0;
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}
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}
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static long
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archwrite(Chan *c, void *a, long n, vlong offset)
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{
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ulong port, end;
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uchar *cp;
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ushort *sp;
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ulong *lp;
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vlong *vp;
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Rdwrfn *fn;
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port = offset;
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end = port+n;
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switch((ulong)c->qid.path){
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case Qiob:
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checkport(port, end);
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for(cp = a; port < end; port++)
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outb(port, *cp++);
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return n;
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case Qiow:
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if(n & 1)
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error(Ebadarg);
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checkport(port, end);
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for(sp = a; port < end; port += 2)
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outs(port, *sp++);
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return n;
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case Qiol:
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if(n & 3)
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error(Ebadarg);
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checkport(port, end);
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for(lp = a; port < end; port += 4)
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outl(port, *lp++);
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return n;
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case Qmsr:
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if(n & 7)
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error(Ebadarg);
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if((ulong)n/8 > -port)
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error(Ebadarg);
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end = port+(n/8);
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for(vp = a; port != end; port++)
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if(wrmsr(port, *vp++) < 0)
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error(Ebadarg);
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return n;
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default:
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if(c->qid.path < narchdir && (fn = writefn[c->qid.path]) != nil)
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return fn(c, a, n, offset);
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error(Eperm);
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break;
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}
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return 0;
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}
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Dev archdevtab = {
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'P',
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"arch",
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devreset,
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devinit,
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devshutdown,
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archattach,
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archwalk,
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archstat,
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archopen,
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devcreate,
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archclose,
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archread,
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devbread,
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archwrite,
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devbwrite,
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devremove,
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devwstat,
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};
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/*
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* the following is a generic version of the
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* architecture specific stuff
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*/
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static int
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unimplemented(int)
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{
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return 0;
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}
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static void
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nop(void)
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{
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}
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/*
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* 386 has no compare-and-swap instruction.
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* Run it with interrupts turned off instead.
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*/
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static int
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cmpswap386(long *addr, long old, long new)
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{
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int r, s;
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s = splhi();
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if(r = (*addr == old))
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*addr = new;
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splx(s);
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return r;
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}
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/*
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* On a uniprocessor, you'd think that coherence could be nop,
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* but it can't. We still need a barrier when using coherence() in
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* device drivers.
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*
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* On VMware, it's safe (and a huge win) to set this to nop.
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* Aux/vmware does this via the #P/archctl file.
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*/
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void (*coherence)(void) = nop;
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int (*cmpswap)(long*, long, long) = cmpswap386;
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PCArch* arch;
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extern PCArch* knownarch[];
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typedef struct X86type X86type;
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struct X86type {
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int family;
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int model;
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int aalcycles;
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char* name;
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};
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static X86type x86intel[] =
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{
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{ 4, 0, 22, "486DX", }, /* known chips */
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{ 4, 1, 22, "486DX50", },
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{ 4, 2, 22, "486SX", },
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{ 4, 3, 22, "486DX2", },
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{ 4, 4, 22, "486SL", },
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{ 4, 5, 22, "486SX2", },
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{ 4, 7, 22, "DX2WB", }, /* P24D */
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{ 4, 8, 22, "DX4", }, /* P24C */
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{ 4, 9, 22, "DX4WB", }, /* P24CT */
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{ 5, 0, 23, "P5", },
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{ 5, 1, 23, "P5", },
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{ 5, 2, 23, "P54C", },
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{ 5, 3, 23, "P24T", },
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{ 5, 4, 23, "P55C MMX", },
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{ 5, 7, 23, "P54C VRT", },
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{ 6, 1, 16, "PentiumPro", },/* trial and error */
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{ 6, 3, 16, "PentiumII", },
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{ 6, 5, 16, "PentiumII/Xeon", },
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{ 6, 6, 16, "Celeron", },
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{ 6, 7, 16, "PentiumIII/Xeon", },
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{ 6, 8, 16, "PentiumIII/Xeon", },
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{ 6, 0xB, 16, "PentiumIII/Xeon", },
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{ 6, 0xF, 16, "Xeon5000-series", },
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{ 6, 0x16, 16, "Celeron", },
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{ 6, 0x17, 16, "Core 2/Xeon", },
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{ 6, 0x1A, 16, "Core i7/Xeon", },
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{ 6, 0x1C, 16, "Atom", },
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{ 6, 0x1D, 16, "Xeon MP", },
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{ 0xF, 1, 16, "P4", }, /* P4 */
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{ 0xF, 2, 16, "PentiumIV/Xeon", },
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{ 0xF, 6, 16, "PentiumIV/Xeon", },
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{ 3, -1, 32, "386", }, /* family defaults */
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{ 4, -1, 22, "486", },
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{ 5, -1, 23, "P5", },
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{ 6, -1, 16, "P6", },
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{ 0xF, -1, 16, "P4", }, /* P4 */
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{ -1, -1, 16, "unknown", }, /* total default */
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};
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/*
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* The AMD processors all implement the CPUID instruction.
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* The later ones also return the processor name via functions
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* 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
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* and DX:
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* K5 "AMD-K5(tm) Processor"
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* K6 "AMD-K6tm w/ multimedia extensions"
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* K6 3D "AMD-K6(tm) 3D processor"
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* K6 3D+ ?
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*/
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static X86type x86amd[] =
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{
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{ 5, 0, 23, "AMD-K5", }, /* guesswork */
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{ 5, 1, 23, "AMD-K5", }, /* guesswork */
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{ 5, 2, 23, "AMD-K5", }, /* guesswork */
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{ 5, 3, 23, "AMD-K5", }, /* guesswork */
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{ 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
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{ 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
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{ 5, 6, 11, "AMD-K6", }, /* trial and error */
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{ 5, 7, 11, "AMD-K6", }, /* trial and error */
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{ 5, 8, 11, "AMD-K6-2", }, /* trial and error */
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{ 5, 9, 11, "AMD-K6-III", },/* trial and error */
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{ 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
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{ 6, 1, 11, "AMD-Athlon", },/* trial and error */
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{ 6, 2, 11, "AMD-Athlon", },/* trial and error */
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{ 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
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{ 4, -1, 22, "Am486", }, /* guesswork */
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{ 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
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{ 6, -1, 11, "AMD-Athlon", },/* guesswork */
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{ 0xF, -1, 11, "AMD-K8", }, /* guesswork */
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{ 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
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{ 23, 1, 13, "AMD Ryzen" },
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{ -1, -1, 11, "unknown", }, /* total default */
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};
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/*
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* WinChip 240MHz
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*/
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static X86type x86winchip[] =
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{
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{5, 4, 23, "Winchip",}, /* guesswork */
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{6, 7, 23, "Via C3 Samuel 2 or Ezra",},
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{6, 8, 23, "Via C3 Ezra-T",},
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{6, 9, 23, "Via C3 Eden-N",},
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{ -1, -1, 23, "unknown", }, /* total default */
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};
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/*
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* SiS 55x
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*/
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static X86type x86sis[] =
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{
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{5, 0, 23, "SiS 55x",}, /* guesswork */
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{ -1, -1, 23, "unknown", }, /* total default */
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};
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static void simplecycles(uvlong*);
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void (*cycles)(uvlong*) = simplecycles;
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void _cycles(uvlong*); /* in l.s */
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static void
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simplecycles(uvlong*x)
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{
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*x = m->ticks;
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}
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void
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cpuidprint(void)
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{
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print("cpu%d: %dMHz %s %s (AX %8.8uX CX %8.8uX DX %8.8uX)\n",
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m->machno, m->cpumhz, m->cpuidid, m->cpuidtype,
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m->cpuidax, m->cpuidcx, m->cpuiddx);
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}
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/*
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* figure out:
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* - cpu type
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* - whether or not we have a TSC (cycle counter)
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* - whether or not it supports page size extensions
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* (if so turn it on)
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* - whether or not it supports machine check exceptions
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* (if so turn it on)
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* - whether or not it supports the page global flag
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* (if so turn it on)
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* - detect PAT feature and add write-combining entry
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* - detect MTRR support and synchronize state with cpu0
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* - detect NX support and enable it for AMD64
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* - detect watchpoint support
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* - detect FPU features and enable the FPU
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*/
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int
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cpuidentify(void)
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{
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int family, model;
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X86type *t, *tab;
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ulong regs[4];
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uintptr cr4;
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cpuid(Highstdfunc, 0, regs);
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memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
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memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
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memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
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m->cpuidid[12] = '\0';
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cpuid(Procsig, 0, regs);
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m->cpuidax = regs[0];
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m->cpuidcx = regs[2];
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m->cpuiddx = regs[3];
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m->cpuidfamily = m->cpuidax >> 8 & 0xf;
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m->cpuidmodel = m->cpuidax >> 4 & 0xf;
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m->cpuidstepping = m->cpuidax & 0xf;
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switch(m->cpuidfamily){
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case 15:
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m->cpuidfamily += m->cpuidax >> 20 & 0xff;
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m->cpuidmodel += m->cpuidax >> 16 & 0xf;
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break;
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case 6:
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m->cpuidmodel += m->cpuidax >> 16 & 0xf;
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break;
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}
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if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
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strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
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tab = x86amd;
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else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
|
|
tab = x86winchip;
|
|
else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
|
|
tab = x86sis;
|
|
else
|
|
tab = x86intel;
|
|
|
|
family = m->cpuidfamily;
|
|
model = m->cpuidmodel;
|
|
for(t=tab; t->name; t++)
|
|
if((t->family == family && t->model == model)
|
|
|| (t->family == family && t->model == -1)
|
|
|| (t->family == -1))
|
|
break;
|
|
|
|
m->aalcycles = t->aalcycles;
|
|
m->cpuidtype = t->name;
|
|
|
|
/*
|
|
* if there is one, set tsc to a known value
|
|
*/
|
|
if(m->cpuiddx & Tsc){
|
|
m->havetsc = 1;
|
|
cycles = _cycles;
|
|
if(m->cpuiddx & Cpumsr)
|
|
wrmsr(0x10, 0);
|
|
}
|
|
|
|
/*
|
|
* If machine check exception, page size extensions or page global bit
|
|
* are supported enable them in CR4 and clear any other set extensions.
|
|
* If machine check was enabled clear out any lingering status.
|
|
*/
|
|
if(m->cpuiddx & (Pge|Mce|Pse)){
|
|
vlong mca, mct;
|
|
|
|
cr4 = getcr4();
|
|
if(m->cpuiddx & Pse)
|
|
cr4 |= 0x10; /* page size extensions */
|
|
|
|
if((m->cpuiddx & Mce) != 0 && getconf("*nomce") == nil){
|
|
if((m->cpuiddx & Mca) != 0){
|
|
vlong cap;
|
|
int bank;
|
|
|
|
cap = 0;
|
|
rdmsr(0x179, &cap);
|
|
|
|
if(cap & 0x100)
|
|
wrmsr(0x17B, ~0ULL); /* enable all mca features */
|
|
|
|
bank = cap & 0xFF;
|
|
if(bank > 64)
|
|
bank = 64;
|
|
|
|
/* init MCi .. MC1 (except MC0) */
|
|
while(--bank > 0){
|
|
wrmsr(0x400 + bank*4, ~0ULL);
|
|
wrmsr(0x401 + bank*4, 0);
|
|
}
|
|
|
|
if(family != 6 || model >= 0x1A)
|
|
wrmsr(0x400, ~0ULL);
|
|
|
|
wrmsr(0x401, 0);
|
|
}
|
|
else if(family == 5){
|
|
rdmsr(0x00, &mca);
|
|
rdmsr(0x01, &mct);
|
|
}
|
|
cr4 |= 0x40; /* machine check enable */
|
|
}
|
|
|
|
/*
|
|
* Detect whether the chip supports the global bit
|
|
* in page directory and page table entries. When set
|
|
* in a particular entry, it means ``don't bother removing
|
|
* this from the TLB when CR3 changes.''
|
|
*
|
|
* We flag all kernel pages with this bit. Doing so lessens the
|
|
* overhead of switching processes on bare hardware,
|
|
* even more so on VMware. See mmu.c:/^memglobal.
|
|
*
|
|
* For future reference, should we ever need to do a
|
|
* full TLB flush, it can be accomplished by clearing
|
|
* the PGE bit in CR4, writing to CR3, and then
|
|
* restoring the PGE bit.
|
|
*/
|
|
if(m->cpuiddx & Pge){
|
|
cr4 |= 0x80; /* page global enable bit */
|
|
m->havepge = 1;
|
|
}
|
|
putcr4(cr4);
|
|
|
|
if((m->cpuiddx & (Mca|Mce)) == Mce)
|
|
rdmsr(0x01, &mct);
|
|
}
|
|
|
|
#ifdef PATWC
|
|
/* IA32_PAT write combining */
|
|
if((m->cpuiddx & Pat) != 0){
|
|
vlong pat;
|
|
|
|
if(rdmsr(0x277, &pat) != -1){
|
|
pat &= ~(255LL<<(PATWC*8));
|
|
pat |= 1LL<<(PATWC*8); /* WC */
|
|
wrmsr(0x277, pat);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if((m->cpuiddx & Mtrr) != 0 && getconf("*nomtrr") == nil)
|
|
mtrrsync();
|
|
|
|
if(strcmp(m->cpuidid, "GenuineIntel") == 0 && (m->cpuidcx & Rdrnd) != 0)
|
|
hwrandbuf = rdrandbuf;
|
|
else
|
|
hwrandbuf = nil;
|
|
|
|
if(sizeof(uintptr) == 8) {
|
|
/* 8-byte watchpoints are supported in Long Mode */
|
|
m->havewatchpt8 = 1;
|
|
|
|
/* check and enable NX bit */
|
|
cpuid(Highextfunc, 0, regs);
|
|
if(regs[0] >= Procextfeat){
|
|
cpuid(Procextfeat, 0, regs);
|
|
if((regs[3] & (1<<20)) != 0){
|
|
vlong efer;
|
|
|
|
/* enable no-execute feature */
|
|
if(rdmsr(Efer, &efer) != -1){
|
|
efer |= 1ull<<11;
|
|
if(wrmsr(Efer, efer) != -1)
|
|
m->havenx = 1;
|
|
}
|
|
}
|
|
}
|
|
} else if(strcmp(m->cpuidid, "GenuineIntel") == 0){
|
|
/* some random CPUs that support 8-byte watchpoints */
|
|
if(family == 15 && (model == 3 || model == 4 || model == 6)
|
|
|| family == 6 && (model == 15 || model == 23 || model == 28))
|
|
m->havewatchpt8 = 1;
|
|
/* Intel SDM claims amd64 support implies 8-byte watchpoint support */
|
|
cpuid(Highextfunc, 0, regs);
|
|
if(regs[0] >= Procextfeat){
|
|
cpuid(Procextfeat, 0, regs);
|
|
if((regs[3] & 1<<29) != 0)
|
|
m->havewatchpt8 = 1;
|
|
}
|
|
}
|
|
|
|
fpuinit();
|
|
|
|
return t->family;
|
|
}
|
|
|
|
static long
|
|
cputyperead(Chan*, void *a, long n, vlong offset)
|
|
{
|
|
char str[32];
|
|
|
|
snprint(str, sizeof(str), "%s %d\n", m->cpuidtype, m->cpumhz);
|
|
return readstr(offset, a, n, str);
|
|
}
|
|
|
|
static long
|
|
archctlread(Chan*, void *a, long nn, vlong offset)
|
|
{
|
|
int n;
|
|
char *buf, *p, *ep;
|
|
|
|
p = buf = smalloc(READSTR);
|
|
ep = p + READSTR;
|
|
p = seprint(p, ep, "cpu %s %d%s\n",
|
|
m->cpuidtype, m->cpumhz, m->havepge ? " pge" : "");
|
|
p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
|
|
p = seprint(p, ep, "coherence ");
|
|
if(coherence == mb386)
|
|
p = seprint(p, ep, "mb386\n");
|
|
else if(coherence == mb586)
|
|
p = seprint(p, ep, "mb586\n");
|
|
else if(coherence == mfence)
|
|
p = seprint(p, ep, "mfence\n");
|
|
else if(coherence == nop)
|
|
p = seprint(p, ep, "nop\n");
|
|
else
|
|
p = seprint(p, ep, "0x%p\n", coherence);
|
|
p = seprint(p, ep, "cmpswap ");
|
|
if(cmpswap == cmpswap386)
|
|
p = seprint(p, ep, "cmpswap386\n");
|
|
else if(cmpswap == cmpswap486)
|
|
p = seprint(p, ep, "cmpswap486\n");
|
|
else
|
|
p = seprint(p, ep, "0x%p\n", cmpswap);
|
|
p = seprint(p, ep, "arch %s\n", arch->id);
|
|
n = p - buf;
|
|
n += mtrrprint(p, ep - p);
|
|
buf[n] = '\0';
|
|
|
|
n = readstr(offset, a, nn, buf);
|
|
free(buf);
|
|
return n;
|
|
}
|
|
|
|
enum
|
|
{
|
|
CMpge,
|
|
CMcoherence,
|
|
CMcache,
|
|
};
|
|
|
|
static Cmdtab archctlmsg[] =
|
|
{
|
|
CMpge, "pge", 2,
|
|
CMcoherence, "coherence", 2,
|
|
CMcache, "cache", 4,
|
|
};
|
|
|
|
static long
|
|
archctlwrite(Chan*, void *a, long n, vlong)
|
|
{
|
|
uvlong base, size;
|
|
Cmdbuf *cb;
|
|
Cmdtab *ct;
|
|
char *ep;
|
|
|
|
cb = parsecmd(a, n);
|
|
if(waserror()){
|
|
free(cb);
|
|
nexterror();
|
|
}
|
|
ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
|
|
switch(ct->index){
|
|
case CMpge:
|
|
if(!m->havepge)
|
|
error("processor does not support pge");
|
|
if(strcmp(cb->f[1], "on") == 0)
|
|
putcr4(getcr4() | 0x80);
|
|
else if(strcmp(cb->f[1], "off") == 0)
|
|
putcr4(getcr4() & ~0x80);
|
|
else
|
|
cmderror(cb, "invalid pge ctl");
|
|
break;
|
|
case CMcoherence:
|
|
if(strcmp(cb->f[1], "mb386") == 0)
|
|
coherence = mb386;
|
|
else if(strcmp(cb->f[1], "mb586") == 0){
|
|
if(m->cpuidfamily < 5)
|
|
error("invalid coherence ctl on this cpu family");
|
|
coherence = mb586;
|
|
}else if(strcmp(cb->f[1], "mfence") == 0){
|
|
if((m->cpuiddx & Sse2) == 0)
|
|
error("invalid coherence ctl on this cpu family");
|
|
coherence = mfence;
|
|
}else if(strcmp(cb->f[1], "nop") == 0){
|
|
/* only safe on vmware */
|
|
if(conf.nmach > 1)
|
|
error("cannot disable coherence on a multiprocessor");
|
|
coherence = nop;
|
|
}else
|
|
cmderror(cb, "invalid coherence ctl");
|
|
break;
|
|
case CMcache:
|
|
base = strtoull(cb->f[1], &ep, 0);
|
|
if(*ep)
|
|
error("cache: parse error: base not a number?");
|
|
size = strtoull(cb->f[2], &ep, 0);
|
|
if(*ep)
|
|
error("cache: parse error: size not a number?");
|
|
ep = mtrr(base, size, cb->f[3]);
|
|
if(ep != nil)
|
|
error(ep);
|
|
break;
|
|
}
|
|
free(cb);
|
|
poperror();
|
|
return n;
|
|
}
|
|
|
|
static long
|
|
rmemrw(int isr, void *a, long n, vlong off)
|
|
{
|
|
uintptr addr = off;
|
|
|
|
if(off < 0 || n < 0)
|
|
error("bad offset/count");
|
|
if(isr){
|
|
if(addr >= MB)
|
|
return 0;
|
|
if(addr+n > MB)
|
|
n = MB - addr;
|
|
memmove(a, KADDR(addr), n);
|
|
}else{
|
|
/* allow vga framebuf's write access */
|
|
if(addr >= MB || addr+n > MB ||
|
|
(addr < 0xA0000 || addr+n > 0xB0000+0x10000))
|
|
error("bad offset/count in write");
|
|
memmove(KADDR(addr), a, n);
|
|
}
|
|
return n;
|
|
}
|
|
|
|
static long
|
|
rmemread(Chan*, void *a, long n, vlong off)
|
|
{
|
|
return rmemrw(1, a, n, off);
|
|
}
|
|
|
|
static long
|
|
rmemwrite(Chan*, void *a, long n, vlong off)
|
|
{
|
|
return rmemrw(0, a, n, off);
|
|
}
|
|
|
|
void
|
|
archinit(void)
|
|
{
|
|
PCArch **p;
|
|
|
|
arch = knownarch[0];
|
|
for(p = knownarch; *p != nil; p++){
|
|
if((*p)->ident != nil && (*p)->ident() == 0){
|
|
arch = *p;
|
|
break;
|
|
}
|
|
}
|
|
if(arch != knownarch[0]){
|
|
if(arch->id == nil)
|
|
arch->id = knownarch[0]->id;
|
|
if(arch->reset == nil)
|
|
arch->reset = knownarch[0]->reset;
|
|
if(arch->intrinit == nil)
|
|
arch->intrinit = knownarch[0]->intrinit;
|
|
if(arch->intrassign == nil)
|
|
arch->intrassign = knownarch[0]->intrassign;
|
|
if(arch->clockinit == nil)
|
|
arch->clockinit = knownarch[0]->clockinit;
|
|
}
|
|
|
|
/*
|
|
* Decide whether to use copy-on-reference (386 and mp).
|
|
* We get another chance to set it in mpinit() for a
|
|
* multiprocessor.
|
|
*/
|
|
if(m->cpuidfamily == 3)
|
|
conf.copymode = 1;
|
|
|
|
if(m->cpuidfamily >= 4)
|
|
cmpswap = cmpswap486;
|
|
|
|
if(m->cpuidfamily >= 5)
|
|
coherence = mb586;
|
|
|
|
if(m->cpuiddx & Sse2)
|
|
coherence = mfence;
|
|
|
|
addarchfile("cputype", 0444, cputyperead, nil);
|
|
addarchfile("archctl", 0664, archctlread, archctlwrite);
|
|
addarchfile("realmodemem", 0660, rmemread, rmemwrite);
|
|
}
|
|
|
|
/*
|
|
* call either the pcmcia or pccard device setup
|
|
*/
|
|
int
|
|
pcmspecial(char *idstr, ISAConf *isa)
|
|
{
|
|
return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
|
|
}
|
|
|
|
/*
|
|
* call either the pcmcia or pccard device teardown
|
|
*/
|
|
void
|
|
pcmspecialclose(int a)
|
|
{
|
|
if (_pcmspecialclose != nil)
|
|
_pcmspecialclose(a);
|
|
}
|
|
|
|
/*
|
|
* return value and speed of timer set in arch->clockenable
|
|
*/
|
|
uvlong
|
|
fastticks(uvlong *hz)
|
|
{
|
|
return (*arch->fastclock)(hz);
|
|
}
|
|
|
|
ulong
|
|
µs(void)
|
|
{
|
|
return fastticks2us((*arch->fastclock)(nil));
|
|
}
|
|
|
|
/*
|
|
* set next timer interrupt
|
|
*/
|
|
void
|
|
timerset(Tval x)
|
|
{
|
|
(*arch->timerset)(x);
|
|
}
|
|
|
|
/*
|
|
* put the processor in the halt state if we've no processes to run.
|
|
* an interrupt will get us going again.
|
|
*
|
|
* halting in an smp system can result in a startup latency for
|
|
* processes that become ready.
|
|
* if idle_spin is zero, we care more about saving energy
|
|
* than reducing this latency.
|
|
*
|
|
* the performance loss with idle_spin == 0 seems to be slight
|
|
* and it reduces lock contention (thus system time and real time)
|
|
* on many-core systems with large values of NPROC.
|
|
*/
|
|
void
|
|
idlehands(void)
|
|
{
|
|
extern int nrdy, idle_spin;
|
|
|
|
if(conf.nmach == 1)
|
|
halt();
|
|
else if(m->cpuidcx & Monitor)
|
|
mwait(&nrdy);
|
|
else if(idle_spin == 0)
|
|
halt();
|
|
}
|
|
|
|
int
|
|
isaconfig(char *class, int ctlrno, ISAConf *isa)
|
|
{
|
|
char cc[32], *p, *x;
|
|
int i;
|
|
|
|
snprint(cc, sizeof cc, "%s%d", class, ctlrno);
|
|
p = getconf(cc);
|
|
if(p == nil)
|
|
return 0;
|
|
|
|
x = nil;
|
|
kstrdup(&x, p);
|
|
p = x;
|
|
|
|
isa->type = "";
|
|
isa->nopt = tokenize(p, isa->opt, NISAOPT);
|
|
for(i = 0; i < isa->nopt; i++){
|
|
p = isa->opt[i];
|
|
if(cistrncmp(p, "type=", 5) == 0)
|
|
isa->type = p + 5;
|
|
else if(cistrncmp(p, "port=", 5) == 0)
|
|
isa->port = strtoull(p+5, &p, 0);
|
|
else if(cistrncmp(p, "irq=", 4) == 0)
|
|
isa->irq = strtoul(p+4, &p, 0);
|
|
else if(cistrncmp(p, "dma=", 4) == 0)
|
|
isa->dma = strtoul(p+4, &p, 0);
|
|
else if(cistrncmp(p, "mem=", 4) == 0)
|
|
isa->mem = strtoul(p+4, &p, 0);
|
|
else if(cistrncmp(p, "size=", 5) == 0)
|
|
isa->size = strtoul(p+5, &p, 0);
|
|
else if(cistrncmp(p, "freq=", 5) == 0)
|
|
isa->freq = strtoul(p+5, &p, 0);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
dumpmcregs(void)
|
|
{
|
|
vlong v, w;
|
|
int bank;
|
|
|
|
if((m->cpuiddx & (Mce|Cpumsr)) != (Mce|Cpumsr))
|
|
return;
|
|
if((m->cpuiddx & Mca) == 0){
|
|
rdmsr(0x00, &v);
|
|
rdmsr(0x01, &w);
|
|
iprint("MCA %8.8llux MCT %8.8llux\n", v, w);
|
|
return;
|
|
}
|
|
rdmsr(0x179, &v);
|
|
rdmsr(0x17A, &w);
|
|
iprint("MCG CAP %.16llux STATUS %.16llux\n", v, w);
|
|
|
|
bank = v & 0xFF;
|
|
if(bank > 64)
|
|
bank = 64;
|
|
while(--bank >= 0){
|
|
rdmsr(0x401 + bank*4, &v);
|
|
if((v & (1ull << 63)) == 0)
|
|
continue;
|
|
iprint("MC%d STATUS %.16llux", bank, v);
|
|
if(v & (1ull << 58)){
|
|
rdmsr(0x402 + bank*4, &w);
|
|
iprint(" ADDR %.16llux", w);
|
|
}
|
|
if(v & (1ull << 59)){
|
|
rdmsr(0x403 + bank*4, &w);
|
|
iprint(" MISC %.16llux", w);
|
|
}
|
|
iprint("\n");
|
|
}
|
|
}
|
|
|
|
static void
|
|
nmihandler(Ureg *ureg, void*)
|
|
{
|
|
iprint("cpu%d: nmi PC %#p, status %ux\n",
|
|
m->machno, ureg->pc, inb(0x61));
|
|
while(m->machno != 0)
|
|
;
|
|
}
|
|
|
|
void
|
|
nmienable(void)
|
|
{
|
|
int x;
|
|
|
|
trapenable(VectorNMI, nmihandler, nil, "nmi");
|
|
|
|
/*
|
|
* Hack: should be locked with NVRAM access.
|
|
*/
|
|
outb(0x70, 0x80); /* NMI latch clear */
|
|
outb(0x70, 0);
|
|
|
|
x = inb(0x61) & 0x07; /* Enable NMI */
|
|
outb(0x61, 0x0C|x);
|
|
outb(0x61, x);
|
|
}
|
|
|
|
void
|
|
setupwatchpts(Proc *pr, Watchpt *wp, int nwp)
|
|
{
|
|
int i;
|
|
u8int cfg;
|
|
Watchpt *p;
|
|
|
|
if(nwp > 4)
|
|
error("there are four watchpoints.");
|
|
if(nwp == 0){
|
|
memset(pr->dr, 0, sizeof(pr->dr));
|
|
return;
|
|
}
|
|
for(p = wp; p < wp + nwp; p++){
|
|
switch(p->type){
|
|
case WATCHRD|WATCHWR: case WATCHWR:
|
|
break;
|
|
case WATCHEX:
|
|
if(p->len != 1)
|
|
error("length must be 1 on breakpoints");
|
|
break;
|
|
default:
|
|
error("type must be rw-, -w- or --x");
|
|
}
|
|
switch(p->len){
|
|
case 1: case 2: case 4:
|
|
break;
|
|
case 8:
|
|
if(m->havewatchpt8) break;
|
|
default:
|
|
error(m->havewatchpt8 ? "length must be 1,2,4,8" : "length must be 1,2,4");
|
|
}
|
|
if((p->addr & p->len - 1) != 0)
|
|
error("address must be aligned according to length");
|
|
}
|
|
|
|
memset(pr->dr, 0, sizeof(pr->dr));
|
|
pr->dr[6] = 0xffff8ff0;
|
|
for(i = 0; i < nwp; i++){
|
|
pr->dr[i] = wp[i].addr;
|
|
switch(wp[i].type){
|
|
case WATCHRD|WATCHWR: cfg = 3; break;
|
|
case WATCHWR: cfg = 1; break;
|
|
case WATCHEX: cfg = 0; break;
|
|
default: continue;
|
|
}
|
|
switch(wp[i].len){
|
|
case 1: break;
|
|
case 2: cfg |= 4; break;
|
|
case 4: cfg |= 12; break;
|
|
case 8: cfg |= 8; break;
|
|
default: continue;
|
|
}
|
|
pr->dr[7] |= cfg << 16 + 4 * i;
|
|
pr->dr[7] |= 1 << 2 * i + 1;
|
|
}
|
|
}
|