f48f1a324a
the change to support no-execute bits broke the original raspberry pi1, as it uses backwards compatible page table format. to use the XN bit, subpage AP bits have to be disabled using the XP bit in CP15 Control Register c1 Bit 23.
318 lines
11 KiB
C
318 lines
11 KiB
C
/*
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* arm-specific definitions for armv6 (arm11), armv7 (cortex-a8 and -a7)
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* these are used in C and assembler
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*/
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/*
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* Program Status Registers
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*/
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#define PsrMusr 0x00000010 /* mode */
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#define PsrMfiq 0x00000011
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#define PsrMirq 0x00000012
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#define PsrMsvc 0x00000013 /* `protected mode for OS' */
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#define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */
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#define PsrMabt 0x00000017
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#define PsrMhyp 0x0000001A
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#define PsrMund 0x0000001B
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#define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */
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#define PsrMask 0x0000001F
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#define PsrDfiq 0x00000040 /* disable FIQ interrupts */
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#define PsrDirq 0x00000080 /* disable IRQ interrupts */
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#define PsrV 0x10000000 /* overflow */
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#define PsrC 0x20000000 /* carry/borrow/extend */
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#define PsrZ 0x40000000 /* zero */
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#define PsrN 0x80000000 /* negative/less than */
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/* instruction decoding */
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#define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC)
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#define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op))
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#define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op))
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/*
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* Coprocessors
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*/
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#define CpOFPA 1 /* ancient 7500 FPA */
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#define CpFP 10 /* float FP, VFP cfg. */
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#define CpDFP 11 /* double FP */
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#define CpSC 15 /* System Control */
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/*
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* Primary (CRn) CpSC registers.
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*/
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#define CpID 0 /* ID and cache type */
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#define CpCONTROL 1 /* miscellaneous control */
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#define CpTTB 2 /* Translation Table Base(s) */
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#define CpDAC 3 /* Domain Access Control */
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#define CpFSR 5 /* Fault Status */
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#define CpFAR 6 /* Fault Address */
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#define CpCACHE 7 /* cache/write buffer control */
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#define CpTLB 8 /* TLB control */
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#define CpCLD 9 /* L2 Cache Lockdown, op1==1 */
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#define CpTLD 10 /* TLB Lockdown, with op2 */
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#define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */
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#define CpPID 13 /* Process ID */
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#define CpTIMER 14 /* Generic timer (cortex-a7) */
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#define CpSPM 15 /* system performance monitor (arm1176) */
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/*
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* CpTIMER op1==0 Crm and opcode2 registers (cortex-a7)
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*/
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#define CpTIMERcntfrq 0
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#define CpTIMERphys 2
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#define CpTIMERphysval 0
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#define CpTIMERphysctl 1
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/*
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* CpTTB op1==0, Crm==0 opcode2 values.
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*/
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#define CpTTB0 0
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#define CpTTB1 1 /* cortex */
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#define CpTTBctl 2 /* cortex */
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/*
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* CpFSR opcode2 values.
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*/
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#define CpFSRdata 0 /* armv6, armv7 */
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#define CpFSRinst 1 /* armv6, armv7 */
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/*
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* CpID Secondary (CRm) registers.
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*/
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#define CpIDidct 0
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#define CpIDfeat 1
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/*
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* CpID op1==0 opcode2 fields.
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* the cortex has more op1 codes for cache size, etc.
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*/
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#define CpIDid 0 /* main ID */
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#define CpIDct 1 /* cache type */
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#define CpIDtlb 3 /* tlb type (cortex) */
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#define CpIDmpid 5 /* multiprocessor id (cortex) */
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#define CpIDrevid 6 /* extra revision ID */
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/* CpIDid op1 values */
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#define CpIDcsize 1 /* cache size (cortex) */
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#define CpIDcssel 2 /* cache size select (cortex) */
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/*
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* CpCONTROL op2 codes, op1==0, Crm==0.
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*/
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#define CpMainctl 0
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#define CpAuxctl 1
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#define CpCPaccess 2
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/*
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* CpCONTROL: op1==0, CRm==0, op2==CpMainctl.
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* main control register.
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* cortex/armv7 has more ops and CRm values.
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*/
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#define CpCmmu 0x00000001 /* M: MMU enable */
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#define CpCalign 0x00000002 /* A: alignment fault enable */
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#define CpCdcache 0x00000004 /* C: data cache on */
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#define CpCsbo (3<<22|1<<18|1<<16|017<<3) /* must be 1 (armv7) */
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#define CpCsbz (CpCtre|1<<26|CpCve|1<<15|7<<7) /* must be 0 (armv7) */
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#define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */
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#define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */
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#define CpCicache 0x00001000 /* I: instruction cache on */
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#define CpChv 0x00002000 /* V: high vectors */
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#define CpCrr (1<<14) /* RR: round robin vs random cache replacement */
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#define CpCha (1<<17) /* HA: hw access flag enable */
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#define CpCdz (1<<19) /* DZ: divide by zero fault enable */
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#define CpCfi (1<<21) /* FI: fast intrs */
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#define CpCxp (1<<23) /* XP: subpage AP bits disabled */
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#define CpCve (1<<24) /* VE: intr vectors enable */
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#define CpCee (1<<25) /* EE: exception endianness */
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#define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. */
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#define CpCtre (1<<28) /* TRE: TEX remap enable */
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#define CpCafe (1<<29) /* AFE: access flag (ttb) enable */
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/*
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* CpCONTROL: op1==0, CRm==0, op2==CpAuxctl.
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* Auxiliary control register on cortex at least.
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*/
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#define CpACcachenopipe (1<<20) /* don't pipeline cache maint. */
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#define CpACcp15serial (1<<18) /* serialise CP1[45] ops. */
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#define CpACcp15waitidle (1<<17) /* CP1[45] wait-on-idle */
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#define CpACcp15pipeflush (1<<16) /* CP1[45] flush pipeline */
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#define CpACneonissue1 (1<<12) /* neon single issue */
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#define CpACldstissue1 (1<<11) /* force single issue ld, st */
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#define CpACissue1 (1<<10) /* force single issue */
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#define CpACnobsm (1<<7) /* no branch size mispredicts */
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#define CpACibe (1<<6) /* cp15 invalidate & btb enable */
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#define CpACl1neon (1<<5) /* cache neon (FP) data in L1 cache */
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#define CpACasa (1<<4) /* enable speculative accesses */
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#define CpACl1pe (1<<3) /* l1 cache parity enable */
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#define CpACl2en (1<<1) /* l2 cache enable; default 1 */
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/* cortex-a7 and cortex-a9 */
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#define CpACsmp (1<<6) /* SMP l1 caches coherence; needed for ldrex/strex */
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#define CpACl1pctl (3<<13) /* l1 prefetch control */
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/*
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* CpCONTROL Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpCONTROLscr 1
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#define CpSCRscr 0
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/*
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* CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0.
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* In ARM-speak, 'flush' means invalidate and 'clean' means writeback.
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*/
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#define CpCACHEintr 0 /* interrupt (op2==4) */
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#define CpCACHEisi 1 /* inner-sharable I cache (v7) */
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#define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */
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#define CpCACHEinvi 5 /* instruction, branch table */
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#define CpCACHEinvd 6 /* data or unified */
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#define CpCACHEinvu 7 /* unified (not on cortex) */
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#define CpCACHEva2pa 8 /* va -> pa translation (cortex) */
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#define CpCACHEwb 10 /* writeback to PoC */
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#define CpCACHEwbu 11 /* writeback to PoU */
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#define CpCACHEwbi 14 /* writeback+invalidate (to PoC) */
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#define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */
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#define CpCACHEse 1 /* single entry */
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#define CpCACHEsi 2 /* set/index (set/way) */
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#define CpCACHEtest 3 /* test loop */
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#define CpCACHEwait 4 /* wait (prefetch flush on cortex) */
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#define CpCACHEdmbarr 5 /* wb only (cortex) */
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#define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */
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#define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */
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/*
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* CpTLB Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpTLBinvi 5 /* instruction */
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#define CpTLBinvd 6 /* data */
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#define CpTLBinvu 7 /* unified */
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#define CpTLBinv 0 /* invalidate all */
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#define CpTLBinvse 1 /* invalidate single entry */
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#define CpTBLasid 2 /* by ASID (cortex) */
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/*
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* CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex)
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*/
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#define CpCLDena 12 /* enables */
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#define CpCLDcyc 13 /* cycle counter */
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#define CpCLDuser 14 /* user enable */
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#define CpCLDenapmnc 0
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#define CpCLDenacyc 1
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/*
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* CpCLD Secondary (CRm) registers and opcode2 fields for op1==1.
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*/
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#define CpCLDl2 0 /* l2 cache */
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#define CpCLDl2aux 2 /* auxiliary control */
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/*
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* l2 cache aux. control
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*/
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#define CpCl2ecc (1<<28) /* use ecc, not parity */
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#define CpCl2noldforw (1<<27) /* no ld forwarding */
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#define CpCl2nowrcomb (1<<25) /* no write combining */
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#define CpCl2nowralldel (1<<24) /* no write allocate delay */
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#define CpCl2nowrallcomb (1<<23) /* no write allocate combine */
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#define CpCl2nowralloc (1<<22) /* no write allocate */
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#define CpCl2eccparity (1<<21) /* enable ecc or parity */
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#define CpCl2inner (1<<16) /* inner cacheability */
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/* other bits are tag ram & data ram latencies */
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/*
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* CpTLD Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpTLDlock 0 /* TLB lockdown registers */
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#define CpTLDpreload 1 /* TLB preload */
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#define CpTLDi 0 /* TLB instr. lockdown reg. */
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#define CpTLDd 1 /* " data " " */
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/*
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* CpVECS Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpVECSbase 0
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#define CpVECSnorm 0 /* (non-)secure base addr */
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#define CpVECSmon 1 /* secure monitor base addr */
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/*
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* CpSPM Secondary (CRm) registers and opcode2 fields (armv6)
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*/
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#define CpSPMperf 12 /* various counters */
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#define CpSPMctl 0 /* performance monitor control */
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#define CpSPMcyc 1 /* cycle counter register */
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/*
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* CpCACHERANGE opcode2 fields for MCRR instruction (armv6)
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*/
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#define CpCACHERANGEinvi 5 /* invalidate instruction */
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#define CpCACHERANGEinvd 6 /* invalidate data */
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#define CpCACHERANGEdwb 12 /* writeback */
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#define CpCACHERANGEdwbi 14 /* writeback+invalidate */
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/*
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* CpTTB cache control bits
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*/
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#define CpTTBnos (1<<5) /* only Inner cache shareable */
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#define CpTTBinc (0<<0|0<<6) /* inner non-cacheable */
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#define CpTTBiwba (0<<0|1<<6) /* inner write-back write-allocate */
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#define CpTTBiwt (1<<0|0<<6) /* inner write-through */
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#define CpTTBiwb (1<<0|1<<6) /* inner write-back no write-allocate */
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#define CpTTBonc (0<<3) /* outer non-cacheable */
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#define CpTTBowba (1<<3) /* outer write-back write-allocate */
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#define CpTTBowt (2<<3) /* outer write-through */
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#define CpTTBowb (3<<3) /* outer write-back no write-allocate */
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#define CpTTBs (1<<1) /* page table in shareable memory */
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#define CpTTBbase ~0x7F /* mask off control bits */
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/*
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* MMU page table entries.
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* Mbz (0x10) bit is implementation-defined and must be 0 on the cortex.
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*/
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#define Mbz (0<<4)
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#define Fault 0x00000000 /* L[12] pte: unmapped */
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#define Coarse (Mbz|1) /* L1 */
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#define Section (Mbz|2) /* L1 1MB */
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#define Fine (Mbz|3) /* L1 */
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#define Large 0x00000001 /* L2 64KB */
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#define Small 0x00000002 /* L2 4KB */
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#define Tiny 0x00000003 /* L2 1KB: not in v7 */
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#define Buffered 0x00000004 /* L[12]: write-back not -thru */
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#define Cached 0x00000008 /* L[12] */
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#define Dom0 0
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#define L1wralloc (1<<12) /* L1 TEX */
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#define L1sharable (1<<16)
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#define L1noexec (1<<4)
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#define L2wralloc (1<<6) /* L2 TEX (small pages) */
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#define L2sharable (1<<10)
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#define L2noexec (1<<0) /* L2 XN (small pages) */
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/* attributes for memory containing locks -- differs between armv6 and armv7 */
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//#define L1ptedramattrs (Cached | Buffered | L1wralloc | L1sharable)
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//#define L2ptedramattrs (Cached | Buffered | L2wralloc | L2sharable)
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#define Noaccess 0 /* AP, DAC */
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#define Krw 1 /* AP */
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/* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */
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#define Uro 2 /* AP */
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#define Urw 3 /* AP */
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#define Client 1 /* DAC */
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#define Manager 3 /* DAC */
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#define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
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#define AP(n, v) F((v), ((n)*2)+4, 2)
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#define L1AP(ap) AP(3, (ap))
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#define L2AP(ap) AP(0, (ap))
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#define DAC(n, v) F((v), (n)*2, 2)
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#define HVECTORS 0xffff0000
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