119 lines
2.1 KiB
Plaintext
119 lines
2.1 KiB
Plaintext
// ARM support
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defn acidinit() // Called after all the init modules are loaded
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{
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bplist = {};
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bpfmt = 'X';
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wplist = {};
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wpflush();
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srcpath = {
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"./",
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"/sys/src/libc/port/",
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"/sys/src/libc/9sys/",
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"/sys/src/libc/arm/"
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};
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srcfiles = {}; // list of loaded files
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srctext = {}; // the text of the files
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}
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defn linkreg(addr)
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{
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return *R14;
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}
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defn stk() // trace
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{
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_stk(*PC, *SP, linkreg(0), 0);
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}
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defn lstk() // trace with locals
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{
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_stk(*PC, *SP, linkreg(0), 1);
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}
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defn gpr() // print general purpose registers
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{
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print("R0\t", *R0, " R1\t", *R1, " R2\t", *R2, "\n");
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print("R3\t", *R3, " R4\t", *R4, " R5\t", *R5, "\n");
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print("R6\t", *R6, " R7\t", *R7, " R8\t", *R8, "\n");
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print("R9\t", *R9, " R10\t", *R10, " R11\t", *R11, "\n");
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print("R12\t", *R12, " R13\t", *R13, " R14\t", *R14, "\n");
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print("R15\t", *R15, "\n");
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}
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defn regs() // print all registers
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{
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gpr();
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}
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defn pstop(pid)
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{
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local l;
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local pc;
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pc = *PC;
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print(pid,": ", reason(*TYPE), "\t");
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print(fmt(pc, 'a'), "\t", fmt(pc, 'i'), "\n");
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if notes then {
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if notes[0] != "sys: breakpoint" then {
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print("Notes pending:\n");
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l = notes;
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while l do {
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print("\t", head l, "\n");
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l = tail l;
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}
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}
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}
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}
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aggr Ureg
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{
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'U' 0 r0;
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'U' 4 r1;
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'U' 8 r2;
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'U' 12 r3;
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'U' 16 r4;
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'U' 20 r5;
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'U' 24 r6;
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'U' 28 r7;
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'U' 32 r8;
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'U' 36 r9;
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'U' 40 r10;
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'U' 44 r11;
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'U' 48 r12;
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'U' 52 r13;
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'U' 56 r14;
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'U' 60 type;
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'U' 64 psr;
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'U' 68 pc;
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};
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defn
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Ureg(addr) {
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complex Ureg addr;
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print(" r0 ", addr.r0, "\n");
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print(" r1 ", addr.r1, "\n");
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print(" r2 ", addr.r2, "\n");
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print(" r3 ", addr.r3, "\n");
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print(" r4 ", addr.r4, "\n");
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print(" r5 ", addr.r5, "\n");
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print(" r6 ", addr.r6, "\n");
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print(" r7 ", addr.r7, "\n");
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print(" r8 ", addr.r8, "\n");
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print(" r9 ", addr.r9, "\n");
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print(" r10 ", addr.r10, "\n");
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print(" r11 ", addr.r11, "\n");
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print(" r12 ", addr.r12, "\n");
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print(" r13 ", addr.r13, "\n");
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print(" r14 ", addr.r14, "\n");
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print(" type ", addr.type, "\n");
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print(" psr ", addr.psr, "\n");
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print(" pc ", addr.pc, "\n");
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};
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print("/sys/lib/acid/arm");
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