55d31f2cab
catch the error() that can be thrown by sleep() and tsleep() in kprocs. add missing pexit() calls. always set the freemem argument to pexit() from kproc otherwise the process gets added to the broken list.
1052 lines
22 KiB
C
1052 lines
22 KiB
C
/*
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* VIA VT6102 Fast Ethernet Controller (Rhine II).
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* To do:
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* cache-line size alignments - done
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* reduce tx interrupts
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* use 2 descriptors on tx for alignment - done
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* reorganise initialisation/shutdown/reset
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* adjust Tx FIFO threshold on underflow - untested
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* why does the link status never cause an interrupt?
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* use the lproc as a periodic timer for stalls, etc.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#include "ethermii.h"
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enum {
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Par0 = 0x00, /* Ethernet Address */
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Rcr = 0x06, /* Receive Configuration */
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Tcr = 0x07, /* Transmit Configuration */
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Cr = 0x08, /* Control */
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Isr = 0x0C, /* Interrupt Status */
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Imr = 0x0E, /* Interrupt Mask */
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Mcfilt0 = 0x10, /* Multicast Filter 0 */
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Mcfilt1 = 0x14, /* Multicast Filter 1 */
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Rxdaddr = 0x18, /* Current Rx Descriptor Address */
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Txdaddr = 0x1C, /* Current Tx Descriptor Address */
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Phyadr = 0x6C, /* Phy Address */
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Miisr = 0x6D, /* MII Status */
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Bcr0 = 0x6E, /* Bus Control */
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Bcr1 = 0x6F,
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Miicr = 0x70, /* MII Control */
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Miiadr = 0x71, /* MII Address */
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Miidata = 0x72, /* MII Data */
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Eecsr = 0x74, /* EEPROM Control and Status */
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Stickhw = 0x83, /* Sticky Hardware Control */
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Wolcrclr = 0xA4,
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Wolcgclr = 0xA7,
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Pwrcsrclr = 0xAC,
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};
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enum { /* Rcr */
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Sep = 0x01, /* Accept Error Packets */
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Ar = 0x02, /* Accept Small Packets */
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Am = 0x04, /* Accept Multicast */
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Ab = 0x08, /* Accept Broadcast */
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Prom = 0x10, /* Accept Physical Address Packets */
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RrftMASK = 0xE0, /* Receive FIFO Threshold */
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RrftSHIFT = 5,
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Rrft64 = 0<<RrftSHIFT,
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Rrft32 = 1<<RrftSHIFT,
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Rrft128 = 2<<RrftSHIFT,
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Rrft256 = 3<<RrftSHIFT,
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Rrft512 = 4<<RrftSHIFT,
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Rrft768 = 5<<RrftSHIFT,
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Rrft1024 = 6<<RrftSHIFT,
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RrftSAF = 7<<RrftSHIFT,
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};
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enum { /* Tcr */
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Lb0 = 0x02, /* Loopback Mode */
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Lb1 = 0x04,
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Ofset = 0x08, /* Back-off Priority Selection */
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RtsfMASK = 0xE0, /* Transmit FIFO Threshold */
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RtsfSHIFT = 5,
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Rtsf128 = 0<<RtsfSHIFT,
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Rtsf256 = 1<<RtsfSHIFT,
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Rtsf512 = 2<<RtsfSHIFT,
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Rtsf1024 = 3<<RtsfSHIFT,
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RtsfSAF = 7<<RtsfSHIFT,
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};
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enum { /* Cr */
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Init = 0x0001, /* INIT Process Begin */
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Strt = 0x0002, /* Start NIC */
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Stop = 0x0004, /* Stop NIC */
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Rxon = 0x0008, /* Turn on Receive Process */
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Txon = 0x0010, /* Turn on Transmit Process */
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Tdmd = 0x0020, /* Transmit Poll Demand */
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Rdmd = 0x0040, /* Receive Poll Demand */
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Eren = 0x0100, /* Early Receive Enable */
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Fdx = 0x0400, /* Set MAC to Full Duplex Mode */
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Dpoll = 0x0800, /* Disable Td/Rd Auto Polling */
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Tdmd1 = 0x2000, /* Transmit Poll Demand 1 */
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Rdmd1 = 0x4000, /* Receive Poll Demand 1 */
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Sfrst = 0x8000, /* Software Reset */
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};
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enum { /* Isr/Imr */
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Prx = 0x0001, /* Received Packet Successfully */
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Ptx = 0x0002, /* Transmitted Packet Successfully */
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Rxe = 0x0004, /* Receive Error */
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Txe = 0x0008, /* Transmit Error */
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Tu = 0x0010, /* Transmit Buffer Underflow */
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Ru = 0x0020, /* Receive Buffer Link Error */
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Be = 0x0040, /* PCI Bus Error */
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Cnt = 0x0080, /* Counter Overflow */
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Eri = 0x0100, /* Early Receive Interrupt */
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Udfi = 0x0200, /* Tx FIFO Underflow */
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Ovfi = 0x0400, /* Receive FIFO Overflow */
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Pktrace = 0x0800, /* Hmmm... */
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Norbf = 0x1000, /* No Receive Buffers */
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Abti = 0x2000, /* Transmission Abort */
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Srci = 0x4000, /* Port State Change */
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Geni = 0x8000, /* General Purpose Interrupt */
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};
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enum { /* Phyadr */
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PhyadMASK = 0x1F, /* PHY Address */
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PhyadSHIFT = 0,
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Mfdc = 0x20, /* Accelerate MDC Speed */
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Mpo0 = 0x40, /* MII Polling Timer Interval */
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Mpo1 = 0x80,
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};
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enum { /* Bcr0 */
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DmaMASK = 0x07, /* DMA Length */
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DmaSHIFT = 0,
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Dma32 = 0<<DmaSHIFT,
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Dma64 = 1<<DmaSHIFT,
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Dma128 = 2<<DmaSHIFT,
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Dma256 = 3<<DmaSHIFT,
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Dma512 = 4<<DmaSHIFT,
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Dma1024 = 5<<DmaSHIFT,
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DmaSAF = 7<<DmaSHIFT,
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CrftMASK = 0x38, /* Rx FIFO Threshold */
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CrftSHIFT = 3,
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Crft64 = 1<<CrftSHIFT,
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Crft128 = 2<<CrftSHIFT,
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Crft256 = 3<<CrftSHIFT,
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Crft512 = 4<<CrftSHIFT,
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Crft1024 = 5<<CrftSHIFT,
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CrftSAF = 7<<CrftSHIFT,
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Extled = 0x40, /* Extra LED Support Control */
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Med2 = 0x80, /* Medium Select Control */
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};
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enum { /* Bcr1 */
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PotMASK = 0x07, /* Polling Timer Interval */
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PotSHIFT = 0,
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CtftMASK = 0x38, /* Tx FIFO Threshold */
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CtftSHIFT = 3,
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Ctft64 = 1<<CtftSHIFT,
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Ctft128 = 2<<CtftSHIFT,
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Ctft256 = 3<<CtftSHIFT,
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Ctft512 = 4<<CtftSHIFT,
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Ctft1024 = 5<<CtftSHIFT,
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CtftSAF = 7<<CtftSHIFT,
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};
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enum { /* Miicr */
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Mdc = 0x01, /* Clock */
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Mdi = 0x02, /* Data In */
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Mdo = 0x04, /* Data Out */
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Mout = 0x08, /* Output Enable */
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Mdpm = 0x10, /* Direct Program Mode Enable */
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Wcmd = 0x20, /* Write Enable */
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Rcmd = 0x40, /* Read Enable */
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Mauto = 0x80, /* Auto Polling Enable */
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};
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enum { /* Miiadr */
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MadMASK = 0x1F, /* MII Port Address */
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MadSHIFT = 0,
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Mdone = 0x20, /* Accelerate MDC Speed */
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Msrcen = 0x40, /* MII Polling Timer Interval */
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Midle = 0x80,
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};
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enum { /* Eecsr */
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Edo = 0x01, /* Data Out */
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Edi = 0x02, /* Data In */
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Eck = 0x04, /* Clock */
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Ecs = 0x08, /* Chip Select */
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Dpm = 0x10, /* Direct Program Mode Enable */
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Autold = 0x20, /* Dynamic Reload */
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Embp = 0x40, /* Embedded Program Enable */
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Eepr = 0x80, /* Programmed */
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};
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/*
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* Ring descriptor. The space allocated for each
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* of these will be rounded up to a cache-line boundary.
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* The first 4 elements are known to the hardware.
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*/
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typedef struct Ds Ds;
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typedef struct Ds {
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uint status;
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uint control;
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uint addr;
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uint branch;
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Block* bp;
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void* bounce;
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Ds* next;
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Ds* prev;
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} Ds;
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enum { /* Rx Ds status */
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Rerr = 0x00000001, /* Receiver Error */
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Crc = 0x00000002, /* CRC Error */
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Fae = 0x00000004, /* Frame Alignment Error */
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Fov = 0x00000008, /* FIFO Overflow */
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Long = 0x00000010, /* A Long Packet */
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Runt = 0x00000020, /* A Runt Packet */
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Rxserr = 0x00000040, /* System Error */
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Buff = 0x00000080, /* Buffer Underflow Error */
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Rxedp = 0x00000100, /* End of Packet Buffer */
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Rxstp = 0x00000200, /* Packet Start */
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Chn = 0x00000400, /* Chain Buffer */
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Phy = 0x00000800, /* Physical Address Packet */
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Bar = 0x00001000, /* Broadcast Packet */
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Mar = 0x00002000, /* Multicast Packet */
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Rxok = 0x00008000, /* Packet Received Successfully */
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LengthMASK = 0x07FF0000, /* Received Packet Length */
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LengthSHIFT = 16,
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Own = 0x80000000, /* Descriptor Owned by NIC */
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};
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enum { /* Tx Ds status */
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NcrMASK = 0x0000000F, /* Collision Retry Count */
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NcrSHIFT = 0,
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Cols = 0x00000010, /* Experienced Collisions */
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Cdh = 0x00000080, /* CD Heartbeat */
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Abt = 0x00000100, /* Aborted after Excessive Collisions */
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Owc = 0x00000200, /* Out of Window Collision Seen */
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Crs = 0x00000400, /* Carrier Sense Lost */
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Udf = 0x00000800, /* FIFO Underflow */
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Tbuff = 0x00001000, /* Invalid Td */
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Txserr = 0x00002000, /* System Error */
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Terr = 0x00008000, /* Excessive Collisions */
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};
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enum { /* Tx Ds control */
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TbsMASK = 0x000007FF, /* Tx Buffer Size */
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TbsSHIFT = 0,
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Chain = 0x00008000, /* Chain Buffer */
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Crcdisable = 0x00010000, /* Disable CRC generation */
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Stp = 0x00200000, /* Start of Packet */
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Edp = 0x00400000, /* End of Packet */
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Ic = 0x00800000, /* Assert Interrupt Immediately */
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};
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enum {
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Nrd = 64,
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Ntd = 64,
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Rdbsz = ROUNDUP(ETHERMAXTU+4, 4),
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Nrxstats = 8,
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Ntxstats = 9,
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Txcopy = 128,
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};
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typedef struct Ctlr Ctlr;
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typedef struct Ctlr {
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int port;
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Pcidev* pcidev;
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Ctlr* next;
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int active;
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int id;
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uchar par[Eaddrlen];
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QLock alock; /* attach */
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void* alloc; /* receive/transmit descriptors */
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int cls; /* alignment */
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int nrd;
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int ntd;
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Ds* rd;
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Ds* rdh;
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Lock tlock;
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Ds* td;
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Ds* tdh;
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Ds* tdt;
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int tdused;
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Lock clock; /* */
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int cr;
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int imr;
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int tft; /* Tx threshold */
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Mii* mii;
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Rendez lrendez;
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int lwakeup;
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uint rxstats[Nrxstats]; /* statistics */
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uint txstats[Ntxstats];
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uint intr;
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uint lintr;
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uint lsleep;
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uint rintr;
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uint tintr;
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uint taligned;
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uint tsplit;
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uint tcopied;
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uint txdw;
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} Ctlr;
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static Ctlr* vt6102ctlrhead;
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static Ctlr* vt6102ctlrtail;
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#define csr8r(c, r) (inb((c)->port+(r)))
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#define csr16r(c, r) (ins((c)->port+(r)))
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#define csr32r(c, r) (inl((c)->port+(r)))
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#define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
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#define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
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#define csr32w(c, r, w) (outl((c)->port+(r), (ulong)(w)))
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static char* rxstats[Nrxstats] = {
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"Receiver Error",
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"CRC Error",
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"Frame Alignment Error",
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"FIFO Overflow",
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"Long Packet",
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"Runt Packet",
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"System Error",
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"Buffer Underflow Error",
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};
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static char* txstats[Ntxstats] = {
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"Aborted after Excessive Collisions",
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"Out of Window Collision Seen",
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"Carrier Sense Lost",
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"FIFO Underflow",
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"Invalid Td",
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"System Error",
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nil,
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"Excessive Collisions",
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};
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static long
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vt6102ifstat(Ether* edev, void* a, long n, ulong offset)
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{
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char *p;
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Ctlr *ctlr;
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int i, l, r;
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ctlr = edev->ctlr;
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p = smalloc(READSTR);
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l = 0;
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for(i = 0; i < Nrxstats; i++){
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l += snprint(p+l, READSTR-l, "%s: %ud\n",
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rxstats[i], ctlr->rxstats[i]);
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}
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for(i = 0; i < Ntxstats; i++){
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if(txstats[i] == nil)
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continue;
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l += snprint(p+l, READSTR-l, "%s: %ud\n",
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txstats[i], ctlr->txstats[i]);
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}
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l += snprint(p+l, READSTR-l, "cls: %ud\n", ctlr->cls);
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l += snprint(p+l, READSTR-l, "intr: %ud\n", ctlr->intr);
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l += snprint(p+l, READSTR-l, "lintr: %ud\n", ctlr->lintr);
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l += snprint(p+l, READSTR-l, "lsleep: %ud\n", ctlr->lsleep);
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l += snprint(p+l, READSTR-l, "rintr: %ud\n", ctlr->rintr);
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l += snprint(p+l, READSTR-l, "tintr: %ud\n", ctlr->tintr);
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l += snprint(p+l, READSTR-l, "taligned: %ud\n", ctlr->taligned);
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l += snprint(p+l, READSTR-l, "tsplit: %ud\n", ctlr->tsplit);
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l += snprint(p+l, READSTR-l, "tcopied: %ud\n", ctlr->tcopied);
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l += snprint(p+l, READSTR-l, "txdw: %ud\n", ctlr->txdw);
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l += snprint(p+l, READSTR-l, "tft: %ud\n", ctlr->tft);
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if(ctlr->mii != nil && ctlr->mii->curphy != nil){
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l += snprint(p+l, READSTR-l, "phy: ");
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for(i = 0; i < NMiiPhyr; i++){
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if(i && ((i & 0x07) == 0))
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l += snprint(p+l, READSTR-l, "\n ");
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r = miimir(ctlr->mii, i);
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l += snprint(p+l, READSTR-l, " %4.4uX", r);
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}
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snprint(p+l, READSTR-l, "\n");
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}
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snprint(p+l, READSTR-l, "\n");
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n = readstr(offset, a, n, p);
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free(p);
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return n;
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}
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static void
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vt6102promiscuous(void* arg, int on)
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{
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int rcr;
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Ctlr *ctlr;
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Ether *edev;
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edev = arg;
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ctlr = edev->ctlr;
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rcr = csr8r(ctlr, Rcr);
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if(on)
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rcr |= Prom;
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else
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rcr &= ~Prom;
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csr8w(ctlr, Rcr, rcr);
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}
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static void
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vt6102multicast(void* arg, uchar* addr, int on)
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{
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/*
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* For now Am is set in Rcr.
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* Will need to interlock with promiscuous
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* when this gets filled in.
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*/
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USED(arg, addr, on);
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}
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static int
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vt6102wakeup(void* v)
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{
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return *((int*)v) != 0;
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}
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static void
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vt6102imr(Ctlr* ctlr, int imr)
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{
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ilock(&ctlr->clock);
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ctlr->imr |= imr;
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csr16w(ctlr, Imr, ctlr->imr);
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iunlock(&ctlr->clock);
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}
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static void
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vt6102lproc(void* arg)
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{
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Ctlr *ctlr;
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Ether *edev;
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MiiPhy *phy;
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edev = arg;
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ctlr = edev->ctlr;
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while(waserror())
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;
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for(;;){
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if(ctlr->mii == nil || ctlr->mii->curphy == nil)
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break;
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if(miistatus(ctlr->mii) < 0)
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goto enable;
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phy = ctlr->mii->curphy;
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ilock(&ctlr->clock);
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if(phy->fd)
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ctlr->cr |= Fdx;
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else
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ctlr->cr &= ~Fdx;
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csr16w(ctlr, Cr, ctlr->cr);
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iunlock(&ctlr->clock);
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enable:
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ctlr->lwakeup = 0;
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vt6102imr(ctlr, Srci);
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ctlr->lsleep++;
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sleep(&ctlr->lrendez, vt6102wakeup, &ctlr->lwakeup);
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}
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pexit("vt6102lproc: done", 1);
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}
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static void
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vt6102attach(Ether* edev)
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{
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int dsz, i;
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Ctlr *ctlr;
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Ds *ds, *prev;
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uchar *alloc, *bounce;
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char name[KNAMELEN];
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ctlr = edev->ctlr;
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qlock(&ctlr->alock);
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if(ctlr->alloc != nil){
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qunlock(&ctlr->alock);
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return;
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}
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/*
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* Descriptor and bounce-buffer space.
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* Must all be aligned on a 4-byte boundary,
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* but try to align on cache-lines.
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*/
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ctlr->nrd = Nrd;
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ctlr->ntd = Ntd;
|
|
dsz = ROUNDUP(sizeof(Ds), ctlr->cls);
|
|
alloc = mallocalign((ctlr->nrd+ctlr->ntd)*dsz + ctlr->ntd*Txcopy, dsz, 0, 0);
|
|
if(alloc == nil){
|
|
qunlock(&ctlr->alock);
|
|
error(Enomem);
|
|
}
|
|
ctlr->alloc = alloc;
|
|
|
|
ctlr->rd = (Ds*)alloc;
|
|
|
|
if(waserror()){
|
|
ds = ctlr->rd;
|
|
for(i = 0; i < ctlr->nrd; i++){
|
|
if(ds->bp != nil){
|
|
freeb(ds->bp);
|
|
ds->bp = nil;
|
|
}
|
|
if((ds = ds->next) == nil)
|
|
break;
|
|
}
|
|
free(ctlr->alloc);
|
|
ctlr->alloc = nil;
|
|
qunlock(&ctlr->alock);
|
|
nexterror();
|
|
}
|
|
|
|
prev = ctlr->rd + ctlr->nrd-1;
|
|
for(i = 0; i < ctlr->nrd; i++){
|
|
ds = (Ds*)alloc;
|
|
alloc += dsz;
|
|
|
|
ds->control = Rdbsz;
|
|
ds->branch = PCIWADDR(alloc);
|
|
|
|
ds->bp = iallocb(Rdbsz+3);
|
|
if(ds->bp == nil)
|
|
error("vt6102: can't allocate receive ring\n");
|
|
ds->bp->rp = (uchar*)ROUNDUP((ulong)ds->bp->rp, 4);
|
|
ds->addr = PCIWADDR(ds->bp->rp);
|
|
|
|
ds->next = (Ds*)alloc;
|
|
ds->prev = prev;
|
|
prev = ds;
|
|
|
|
ds->status = Own;
|
|
}
|
|
prev->branch = 0;
|
|
prev->next = ctlr->rd;
|
|
prev->status = 0;
|
|
ctlr->rdh = ctlr->rd;
|
|
|
|
ctlr->td = (Ds*)alloc;
|
|
prev = ctlr->td + ctlr->ntd-1;
|
|
bounce = alloc + ctlr->ntd*dsz;
|
|
for(i = 0; i < ctlr->ntd; i++){
|
|
ds = (Ds*)alloc;
|
|
alloc += dsz;
|
|
|
|
ds->bounce = bounce;
|
|
bounce += Txcopy;
|
|
ds->next = (Ds*)alloc;
|
|
ds->prev = prev;
|
|
prev = ds;
|
|
}
|
|
prev->next = ctlr->td;
|
|
ctlr->tdh = ctlr->tdt = ctlr->td;
|
|
ctlr->tdused = 0;
|
|
|
|
ctlr->cr = Dpoll|Rdmd|Txon|Rxon|Strt;
|
|
/*Srci|Abti|Norbf|Pktrace|Ovfi|Udfi|Be|Ru|Tu|Txe|Rxe|Ptx|Prx*/
|
|
ctlr->imr = Abti|Norbf|Pktrace|Ovfi|Udfi|Be|Ru|Tu|Txe|Rxe|Ptx|Prx;
|
|
|
|
ilock(&ctlr->clock);
|
|
csr32w(ctlr, Rxdaddr, PCIWADDR(ctlr->rd));
|
|
csr32w(ctlr, Txdaddr, PCIWADDR(ctlr->td));
|
|
csr16w(ctlr, Isr, ~0);
|
|
csr16w(ctlr, Imr, ctlr->imr);
|
|
csr16w(ctlr, Cr, ctlr->cr);
|
|
iunlock(&ctlr->clock);
|
|
|
|
snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
|
|
kproc(name, vt6102lproc, edev);
|
|
|
|
qunlock(&ctlr->alock);
|
|
poperror();
|
|
}
|
|
|
|
static void
|
|
vt6102transmit(Ether* edev)
|
|
{
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
Ds *ds, *next;
|
|
int control, i, o, prefix, size, tdused, timeo;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
ilock(&ctlr->tlock);
|
|
|
|
/*
|
|
* Free any completed packets
|
|
*/
|
|
ds = ctlr->tdh;
|
|
for(tdused = ctlr->tdused; tdused > 0; tdused--){
|
|
/*
|
|
* For some errors the chip will turn the Tx engine
|
|
* off. Wait for that to happen.
|
|
* Could reset and re-init the chip here if it doesn't
|
|
* play fair.
|
|
* To do: adjust Tx FIFO threshold on underflow.
|
|
*/
|
|
if(ds->status & (Abt|Tbuff|Udf)){
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!(csr16r(ctlr, Cr) & Txon))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
ds->status = Own;
|
|
csr32w(ctlr, Txdaddr, PCIWADDR(ds));
|
|
}
|
|
|
|
if(ds->status & Own)
|
|
break;
|
|
ds->addr = 0;
|
|
ds->branch = 0;
|
|
|
|
if(ds->bp != nil){
|
|
freeb(ds->bp);
|
|
ds->bp = nil;
|
|
}
|
|
for(i = 0; i < Ntxstats-1; i++){
|
|
if(ds->status & (1<<i))
|
|
ctlr->txstats[i]++;
|
|
}
|
|
ctlr->txstats[i] += (ds->status & NcrMASK)>>NcrSHIFT;
|
|
|
|
ds = ds->next;
|
|
}
|
|
ctlr->tdh = ds;
|
|
|
|
/*
|
|
* Try to fill the ring back up.
|
|
*/
|
|
ds = ctlr->tdt;
|
|
while(tdused < ctlr->ntd-2){
|
|
if((bp = qget(edev->oq)) == nil)
|
|
break;
|
|
tdused++;
|
|
|
|
size = BLEN(bp);
|
|
prefix = 0;
|
|
|
|
if(o = (((int)bp->rp) & 0x03)){
|
|
prefix = Txcopy-o;
|
|
if(prefix > size)
|
|
prefix = size;
|
|
memmove(ds->bounce, bp->rp, prefix);
|
|
ds->addr = PCIWADDR(ds->bounce);
|
|
bp->rp += prefix;
|
|
size -= prefix;
|
|
}
|
|
|
|
next = ds->next;
|
|
ds->branch = PCIWADDR(ds->next);
|
|
|
|
if(size){
|
|
if(prefix){
|
|
next->bp = bp;
|
|
next->addr = PCIWADDR(bp->rp);
|
|
next->branch = PCIWADDR(next->next);
|
|
next->control = Edp|Chain|((size<<TbsSHIFT) & TbsMASK);
|
|
|
|
control = Stp|Chain|((prefix<<TbsSHIFT) & TbsMASK);
|
|
|
|
next = next->next;
|
|
tdused++;
|
|
ctlr->tsplit++;
|
|
}
|
|
else{
|
|
ds->bp = bp;
|
|
ds->addr = PCIWADDR(bp->rp);
|
|
control = Edp|Stp|((size<<TbsSHIFT) & TbsMASK);
|
|
ctlr->taligned++;
|
|
}
|
|
}
|
|
else{
|
|
freeb(bp);
|
|
control = Edp|Stp|((prefix<<TbsSHIFT) & TbsMASK);
|
|
ctlr->tcopied++;
|
|
}
|
|
|
|
ds->control = control;
|
|
if(tdused >= ctlr->ntd-2){
|
|
ds->control |= Ic;
|
|
ctlr->txdw++;
|
|
}
|
|
coherence();
|
|
ds->status = Own;
|
|
|
|
ds = next;
|
|
}
|
|
ctlr->tdt = ds;
|
|
ctlr->tdused = tdused;
|
|
if(ctlr->tdused)
|
|
csr16w(ctlr, Cr, Tdmd|ctlr->cr);
|
|
|
|
iunlock(&ctlr->tlock);
|
|
}
|
|
|
|
static void
|
|
vt6102receive(Ether* edev)
|
|
{
|
|
Ds *ds;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
int i, len;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
ds = ctlr->rdh;
|
|
while(!(ds->status & Own) && ds->status != 0){
|
|
if(ds->status & Rerr){
|
|
for(i = 0; i < Nrxstats; i++){
|
|
if(ds->status & (1<<i))
|
|
ctlr->rxstats[i]++;
|
|
}
|
|
}
|
|
else if(bp = iallocb(Rdbsz+3)){
|
|
len = ((ds->status & LengthMASK)>>LengthSHIFT)-4;
|
|
ds->bp->wp = ds->bp->rp+len;
|
|
etheriq(edev, ds->bp, 1);
|
|
bp->rp = (uchar*)ROUNDUP((ulong)bp->rp, 4);
|
|
ds->addr = PCIWADDR(bp->rp);
|
|
ds->bp = bp;
|
|
}
|
|
ds->control = Rdbsz;
|
|
ds->branch = 0;
|
|
ds->status = 0;
|
|
|
|
ds->prev->branch = PCIWADDR(ds);
|
|
coherence();
|
|
ds->prev->status = Own;
|
|
|
|
ds = ds->next;
|
|
}
|
|
ctlr->rdh = ds;
|
|
|
|
csr16w(ctlr, Cr, ctlr->cr);
|
|
}
|
|
|
|
static void
|
|
vt6102interrupt(Ureg*, void* arg)
|
|
{
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
int imr, isr, r, timeo;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
ilock(&ctlr->clock);
|
|
csr16w(ctlr, Imr, 0);
|
|
imr = ctlr->imr;
|
|
ctlr->intr++;
|
|
for(;;){
|
|
if((isr = csr16r(ctlr, Isr)) != 0)
|
|
csr16w(ctlr, Isr, isr);
|
|
if((isr & ctlr->imr) == 0)
|
|
break;
|
|
|
|
if(isr & Srci){
|
|
imr &= ~Srci;
|
|
ctlr->lwakeup = isr & Srci;
|
|
wakeup(&ctlr->lrendez);
|
|
isr &= ~Srci;
|
|
ctlr->lintr++;
|
|
}
|
|
if(isr & (Norbf|Pktrace|Ovfi|Ru|Rxe|Prx)){
|
|
vt6102receive(edev);
|
|
isr &= ~(Norbf|Pktrace|Ovfi|Ru|Rxe|Prx);
|
|
ctlr->rintr++;
|
|
}
|
|
if(isr & (Abti|Udfi|Tu|Txe|Ptx)){
|
|
if(isr & (Abti|Udfi|Tu)){
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!(csr16r(ctlr, Cr) & Txon))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
|
|
if((isr & Udfi) && ctlr->tft < CtftSAF){
|
|
ctlr->tft += 1<<CtftSHIFT;
|
|
r = csr8r(ctlr, Bcr1) & ~CtftMASK;
|
|
csr8w(ctlr, Bcr1, r|ctlr->tft);
|
|
}
|
|
}
|
|
vt6102transmit(edev);
|
|
isr &= ~(Abti|Udfi|Tu|Txe|Ptx);
|
|
ctlr->tintr++;
|
|
}
|
|
if(isr)
|
|
panic("vt6102: isr %4.4uX", isr);
|
|
}
|
|
ctlr->imr = imr;
|
|
csr16w(ctlr, Imr, ctlr->imr);
|
|
iunlock(&ctlr->clock);
|
|
}
|
|
|
|
static int
|
|
vt6102miimicmd(Mii* mii, int pa, int ra, int cmd, int data)
|
|
{
|
|
Ctlr *ctlr;
|
|
int r, timeo;
|
|
|
|
ctlr = mii->ctlr;
|
|
|
|
csr8w(ctlr, Miicr, 0);
|
|
r = csr8r(ctlr, Phyadr);
|
|
csr8w(ctlr, Phyadr, (r & ~PhyadMASK)|pa);
|
|
csr8w(ctlr, Phyadr, pa);
|
|
csr8w(ctlr, Miiadr, ra);
|
|
if(cmd == Wcmd)
|
|
csr16w(ctlr, Miidata, data);
|
|
csr8w(ctlr, Miicr, cmd);
|
|
|
|
for(timeo = 0; timeo < 10000; timeo++){
|
|
if(!(csr8r(ctlr, Miicr) & cmd))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
if(timeo >= 10000)
|
|
return -1;
|
|
|
|
if(cmd == Wcmd)
|
|
return 0;
|
|
return csr16r(ctlr, Miidata);
|
|
}
|
|
|
|
static int
|
|
vt6102miimir(Mii* mii, int pa, int ra)
|
|
{
|
|
return vt6102miimicmd(mii, pa, ra, Rcmd, 0);
|
|
}
|
|
|
|
static int
|
|
vt6102miimiw(Mii* mii, int pa, int ra, int data)
|
|
{
|
|
return vt6102miimicmd(mii, pa, ra, Wcmd, data);
|
|
}
|
|
|
|
static int
|
|
vt6102detach(Ctlr* ctlr)
|
|
{
|
|
int revid, timeo;
|
|
|
|
/*
|
|
* Reset power management registers.
|
|
*/
|
|
revid = pcicfgr8(ctlr->pcidev, PciRID);
|
|
if(revid >= 0x40){
|
|
/* Set power state D0. */
|
|
csr8w(ctlr, Stickhw, csr8r(ctlr, Stickhw) & 0xFC);
|
|
|
|
/* Disable force PME-enable. */
|
|
csr8w(ctlr, Wolcgclr, 0x80);
|
|
|
|
/* Clear WOL config and status bits. */
|
|
csr8w(ctlr, Wolcrclr, 0xFF);
|
|
csr8w(ctlr, Pwrcsrclr, 0xFF);
|
|
}
|
|
|
|
/*
|
|
* Soft reset the controller.
|
|
*/
|
|
csr16w(ctlr, Cr, Stop);
|
|
csr16w(ctlr, Cr, Stop|Sfrst);
|
|
for(timeo = 0; timeo < 10000; timeo++){
|
|
if(!(csr16r(ctlr, Cr) & Sfrst))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
if(timeo >= 1000)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
vt6102reset(Ctlr* ctlr)
|
|
{
|
|
MiiPhy *phy;
|
|
int i, r, timeo;
|
|
|
|
if(vt6102detach(ctlr) < 0)
|
|
return -1;
|
|
|
|
/*
|
|
* Load the MAC address into the PAR[01]
|
|
* registers.
|
|
*/
|
|
r = csr8r(ctlr, Eecsr);
|
|
csr8w(ctlr, Eecsr, Autold|r);
|
|
for(timeo = 0; timeo < 100; timeo++){
|
|
if(!(csr8r(ctlr, Cr) & Autold))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
if(timeo >= 100)
|
|
return -1;
|
|
|
|
for(i = 0; i < Eaddrlen; i++)
|
|
ctlr->par[i] = csr8r(ctlr, Par0+i);
|
|
|
|
/*
|
|
* Configure DMA and Rx/Tx thresholds.
|
|
* If the Rx/Tx threshold bits in Bcr[01] are 0 then
|
|
* the thresholds are determined by Rcr/Tcr.
|
|
*/
|
|
r = csr8r(ctlr, Bcr0) & ~(CrftMASK|DmaMASK);
|
|
csr8w(ctlr, Bcr0, r|Crft64|Dma64);
|
|
r = csr8r(ctlr, Bcr1) & ~CtftMASK;
|
|
csr8w(ctlr, Bcr1, r|ctlr->tft);
|
|
|
|
r = csr8r(ctlr, Rcr) & ~(RrftMASK|Prom|Ar|Sep);
|
|
csr8w(ctlr, Rcr, r|Ab|Am);
|
|
csr32w(ctlr, Mcfilt0, ~0UL); /* accept all multicast */
|
|
csr32w(ctlr, Mcfilt1, ~0UL);
|
|
|
|
r = csr8r(ctlr, Tcr) & ~(RtsfMASK|Ofset|Lb1|Lb0);
|
|
csr8w(ctlr, Tcr, r);
|
|
|
|
/*
|
|
* Link management.
|
|
*/
|
|
if((ctlr->mii = malloc(sizeof(Mii))) == nil)
|
|
return -1;
|
|
ctlr->mii->mir = vt6102miimir;
|
|
ctlr->mii->miw = vt6102miimiw;
|
|
ctlr->mii->ctlr = ctlr;
|
|
|
|
if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
|
|
free(ctlr->mii);
|
|
ctlr->mii = nil;
|
|
return -1;
|
|
}
|
|
// print("oui %X phyno %d\n", phy->oui, phy->phyno);
|
|
USED(phy);
|
|
|
|
//miiane(ctlr->mii, ~0, ~0, ~0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
vt6102pci(void)
|
|
{
|
|
Pcidev *p;
|
|
Ctlr *ctlr;
|
|
int cls, port;
|
|
|
|
p = nil;
|
|
while(p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != Pcibcnet || p->ccru != Pciscether)
|
|
continue;
|
|
|
|
switch((p->did<<16)|p->vid){
|
|
default:
|
|
continue;
|
|
case (0x3065<<16)|0x1106: /* Rhine II */
|
|
case (0x3106<<16)|0x1106: /* Rhine III */
|
|
break;
|
|
}
|
|
|
|
port = p->mem[0].bar & ~0x01;
|
|
if(ioalloc(port, p->mem[0].size, 0, "vt6102") < 0){
|
|
print("vt6102: port 0x%uX in use\n", port);
|
|
continue;
|
|
}
|
|
ctlr = malloc(sizeof(Ctlr));
|
|
if(ctlr == nil){
|
|
print("vt6102: can't allocate memory\n");
|
|
iofree(port);
|
|
continue;
|
|
}
|
|
ctlr->port = port;
|
|
ctlr->pcidev = p;
|
|
ctlr->id = (p->did<<16)|p->vid;
|
|
if((cls = pcicfgr8(p, PciCLS)) == 0 || cls == 0xFF)
|
|
cls = 0x10;
|
|
ctlr->cls = cls*4;
|
|
ctlr->tft = Ctft64;
|
|
|
|
if(vt6102reset(ctlr)){
|
|
iofree(port);
|
|
free(ctlr);
|
|
continue;
|
|
}
|
|
pcisetbme(p);
|
|
|
|
if(vt6102ctlrhead != nil)
|
|
vt6102ctlrtail->next = ctlr;
|
|
else
|
|
vt6102ctlrhead = ctlr;
|
|
vt6102ctlrtail = ctlr;
|
|
}
|
|
}
|
|
|
|
static int
|
|
vt6102pnp(Ether* edev)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
if(vt6102ctlrhead == nil)
|
|
vt6102pci();
|
|
|
|
/*
|
|
* Any adapter matches if no edev->port is supplied,
|
|
* otherwise the ports must match.
|
|
*/
|
|
for(ctlr = vt6102ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
if(ctlr->active)
|
|
continue;
|
|
if(edev->port == 0 || edev->port == ctlr->port){
|
|
ctlr->active = 1;
|
|
break;
|
|
}
|
|
}
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
edev->ctlr = ctlr;
|
|
edev->port = ctlr->port;
|
|
edev->irq = ctlr->pcidev->intl;
|
|
edev->tbdf = ctlr->pcidev->tbdf;
|
|
edev->mbps = 100;
|
|
memmove(edev->ea, ctlr->par, Eaddrlen);
|
|
|
|
/*
|
|
* Linkage to the generic ethernet driver.
|
|
*/
|
|
edev->attach = vt6102attach;
|
|
edev->transmit = vt6102transmit;
|
|
edev->interrupt = vt6102interrupt;
|
|
edev->ifstat = vt6102ifstat;
|
|
edev->ctl = nil;
|
|
|
|
edev->arg = edev;
|
|
edev->promiscuous = vt6102promiscuous;
|
|
edev->multicast = vt6102multicast;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ethervt6102link(void)
|
|
{
|
|
addethercard("vt6102", vt6102pnp);
|
|
addethercard("rhine", vt6102pnp);
|
|
}
|