4f85115526
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
1045 lines
18 KiB
C
1045 lines
18 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/pci.h"
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#include "../port/error.h"
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#include "mp.h"
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#include <aml.h>
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typedef struct Rsd Rsd;
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typedef struct Tbl Tbl;
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struct Rsd {
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uchar sig[8];
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uchar csum;
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uchar oemid[6];
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uchar rev;
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uchar raddr[4];
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uchar len[4];
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uchar xaddr[8];
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uchar xcsum;
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uchar reserved[3];
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};
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struct Tbl {
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uchar sig[4];
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uchar len[4];
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uchar rev;
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uchar csum;
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uchar oemid[6];
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uchar oemtid[8];
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uchar oemrev[4];
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uchar cid[4];
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uchar crev[4];
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uchar data[];
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};
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enum {
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Tblsz = 4+4+1+1+6+8+4+4+4,
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};
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static Rsd *rsd;
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/* physical addresses visited by maptable() */
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static int ntblpa;
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static uvlong tblpa[64];
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/* successfully mapped tables */
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static int ntblmap;
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static Tbl *tblmap[64];
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static ushort
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get16(uchar *p){
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return p[1]<<8 | p[0];
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}
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static uint
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get32(uchar *p){
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return p[3]<<24 | p[2]<<16 | p[1]<<8 | p[0];
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}
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static uvlong
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get64(uchar *p){
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uvlong u;
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u = get32(p+4);
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return u<<32 | get32(p);
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}
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static uint
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tbldlen(Tbl *t){
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return get32(t->len) - Tblsz;
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}
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static long
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memcheck(uintptr pa, long len)
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{
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int i;
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uintptr pe;
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Confmem *cm;
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if(len <= 0)
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return len;
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pe = pa + len-1;
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if(pe < pa){
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len = -pa;
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pe = pa + len-1;
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}
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if(pa < PADDR(CPU0END))
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return 0;
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if(pe >= PADDR(KTZERO) && pa < PADDR(end))
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return PADDR(KTZERO) - pa;
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for(i=0; i<nelem(conf.mem); i++){
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cm = &conf.mem[i];
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if(cm->npage == 0)
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continue;
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if(pe >= cm->base && pa <= cm->base + cm->npage*BY2PG - 1)
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return cm->base - pa;
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}
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return len;
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}
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static void
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maptable(uvlong pa)
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{
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uchar *p, *e;
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u32int l;
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Tbl *t;
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int i;
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if(-pa < 8)
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return;
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if(ntblpa >= nelem(tblpa) || ntblmap >= nelem(tblmap))
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return;
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for(i=0; i<ntblpa; i++){
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if(pa == tblpa[i])
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return;
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}
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tblpa[ntblpa++] = pa;
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memreserve(pa, 8);
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if((t = vmap(pa, 8)) == nil)
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return;
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l = get32(t->len);
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if(l < Tblsz
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|| l >= 0x10000000
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|| -pa < l){
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vunmap(t, 8);
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return;
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}
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memreserve(pa, l);
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vunmap(t, 8);
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if((t = vmap(pa, l)) == nil)
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return;
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if(checksum(t, l)){
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vunmap(t, l);
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return;
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}
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tblmap[ntblmap++] = t;
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p = (uchar*)t;
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e = p + l;
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if(memcmp("RSDT", t->sig, 4) == 0){
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for(p = t->data; p+3 < e; p += 4)
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maptable(get32(p));
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return;
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}
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if(memcmp("XSDT", t->sig, 4) == 0){
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for(p = t->data; p+7 < e; p += 8)
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maptable(get64(p));
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return;
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}
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if(memcmp("FACP", t->sig, 4) == 0){
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if(l < 44)
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return;
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maptable(get32(p + 40));
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if(l < 148)
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return;
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maptable(get64(p + 140));
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return;
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}
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}
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static void
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maptables(void)
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{
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if(rsd == nil || ntblmap > 0 || ntblpa > 0)
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return;
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if(!checksum(rsd, 20))
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maptable(get32(rsd->raddr));
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if(rsd->rev >= 2){
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if(!checksum(rsd, 36))
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maptable(get64(rsd->xaddr));
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}
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}
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static Apic*
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findapic(int gsi, int *pintin)
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{
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Apic *a;
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int i;
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for(i=0; i<=MaxAPICNO; i++){
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if((a = mpioapic[i]) == nil)
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continue;
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if((a->flags & PcmpEN) == 0)
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continue;
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if(gsi >= a->gsibase && gsi <= a->gsibase+a->mre){
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if(pintin)
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*pintin = gsi - a->gsibase;
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return a;
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}
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}
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print("findapic: no ioapic found for gsi %d\n", gsi);
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return nil;
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}
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static void
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addirq(int gsi, int type, int busno, int irq, int flags)
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{
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Apic *a;
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Bus *bus;
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Aintr *ai;
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PCMPintr *pi;
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int intin;
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if((a = findapic(gsi, &intin)) == nil)
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return;
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for(bus = mpbus; bus; bus = bus->next)
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if(bus->type == type && bus->busno == busno)
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goto Foundbus;
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if((bus = xalloc(sizeof(Bus))) == nil)
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panic("addirq: no memory for Bus");
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bus->busno = busno;
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bus->type = type;
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if(type == BusISA){
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bus->po = PcmpHIGH;
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bus->el = PcmpEDGE;
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if(mpisabus == -1)
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mpisabus = busno;
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} else {
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bus->po = PcmpLOW;
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bus->el = PcmpLEVEL;
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}
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if(mpbus)
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mpbuslast->next = bus;
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else
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mpbus = bus;
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mpbuslast = bus;
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Foundbus:
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for(ai = bus->aintr; ai; ai = ai->next)
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if(ai->intr->irq == irq)
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return;
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if((pi = xalloc(sizeof(PCMPintr))) == nil)
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panic("addirq: no memory for PCMPintr");
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pi->type = PcmpIOINTR;
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pi->intr = PcmpINT;
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pi->flags = flags & (PcmpPOMASK|PcmpELMASK);
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pi->busno = busno;
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pi->irq = irq;
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pi->apicno = a->apicno;
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pi->intin = intin;
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if((ai = xalloc(sizeof(Aintr))) == nil)
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panic("addirq: no memory for Aintr");
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ai->intr = pi;
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ai->apic = a;
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ai->next = bus->aintr;
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bus->aintr = ai;
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}
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static char*
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eisaid(void *v)
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{
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static char id[8];
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ulong b, l;
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int i;
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if(amltag(v) == 's')
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return v;
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b = amlint(v);
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for(l = 0, i=24; i>=0; i -= 8, b >>= 8)
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l |= (b & 0xFF) << i;
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id[7] = 0;
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for(i=6; i>=3; i--, l >>= 4)
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id[i] = "0123456789ABCDEF"[l & 0xF];
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for(i=2; i>=0; i--, l >>= 5)
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id[i] = '@' + (l & 0x1F);
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return id;
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}
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static int
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pcibusno(void *dot)
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{
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int bno, adr, tbdf;
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Pcidev *pdev;
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void *p, *x;
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char *id;
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id = nil;
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if((x = amlwalk(dot, "^_HID")) != nil)
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if((p = amlval(x)) != nil)
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id = eisaid(p);
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if((x = amlwalk(dot, "^_BBN")) == nil)
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if((x = amlwalk(dot, "^_ADR")) == nil)
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return -1;
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p = nil;
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if(amleval(x, "", &p) < 0)
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return -1;
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adr = amlint(p);
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/* if root bridge, then we are done here */
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if(id != nil && (strcmp(id, "PNP0A03")==0 || strcmp(id, "PNP0A08")==0))
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return adr;
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x = amlwalk(dot, "^");
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if(x == nil || x == dot)
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return -1;
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if((bno = pcibusno(x)) < 0)
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return -1;
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tbdf = MKBUS(BusPCI, bno, adr>>16, adr&0xFFFF);
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pdev = pcimatchtbdf(tbdf);
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if(pdev == nil)
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return -1;
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if(pdev->bridge == nil)
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return bno;
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return BUSBNO(pdev->bridge->tbdf);
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}
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static int
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pciaddr(void *dot)
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{
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int adr, bno;
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void *x, *p;
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for(;;){
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if((x = amlwalk(dot, "_ADR")) == nil){
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x = amlwalk(dot, "^");
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if(x == nil || x == dot)
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break;
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dot = x;
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continue;
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}
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if((bno = pcibusno(x)) < 0)
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break;
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p = nil;
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if(amleval(x, "", &p) < 0)
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break;
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adr = amlint(p);
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return MKBUS(BusPCI, bno, adr>>16, adr&0xFFFF);
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}
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return -1;
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}
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static int
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getirqs(void *d, uchar pmask[32], int *pflags)
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{
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int i, n, m;
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uchar *p;
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*pflags = 0;
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memset(pmask, 0, 32);
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if(amltag(d) != 'b')
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return -1;
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p = amlval(d);
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if(amllen(d) >= 2 && (p[0] == 0x22 || p[0] == 0x23)){
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pmask[0] = p[1];
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pmask[1] = p[2];
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if(amllen(d) >= 3 && p[0] == 0x23)
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*pflags = ((p[3] & (1<<0)) ? PcmpEDGE : PcmpLEVEL)
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| ((p[3] & (1<<3)) ? PcmpLOW : PcmpHIGH);
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return 0;
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}
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if(amllen(d) >= 5 && p[0] == 0x89){
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n = p[4];
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if(amllen(d) < 5+n*4)
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return -1;
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for(i=0; i<n; i++){
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m = get32(p+5 + i*4);
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if(m >= 0 && m < 256)
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pmask[m/8] |= 1<<(m%8);
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}
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*pflags = ((p[3] & (1<<1)) ? PcmpEDGE : PcmpLEVEL)
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| ((p[3] & (1<<2)) ? PcmpLOW : PcmpHIGH);
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return 0;
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}
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return -1;
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}
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static uchar*
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setirq(void *d, uint irq)
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{
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uchar *p;
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if(amltag(d) != 'b')
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return nil;
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p = amlnew('b', amllen(d));
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memmove(p, d, amllen(p));
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if(p[0] == 0x22 || p[0] == 0x23){
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irq = 1<<irq;
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p[1] = irq;
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p[2] = irq>>8;
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}
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if(p[0] == 0x89){
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p[4] = 1;
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p[5] = irq;
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p[6] = irq>>8;
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p[7] = irq>>16;
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p[8] = irq>>24;
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}
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return p;
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}
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static int
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setuplink(void *link, int *pflags)
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{
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uchar im, pm[32], cm[32], *c;
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static int lastirq = 1;
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int gsi, i;
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void *r;
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if(amltag(link) != 'N')
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return -1;
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r = nil;
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if(amleval(amlwalk(link, "_PRS"), "", &r) < 0)
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return -1;
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if(getirqs(r, pm, pflags) < 0)
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return -1;
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r = nil;
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if(amleval(amlwalk(link, "_CRS"), "", &r) < 0)
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return -1;
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if(getirqs(r, cm, pflags) < 0)
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return -1;
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gsi = -1;
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for(i=0; i<256; i++){
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im = 1<<(i%8);
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if(pm[i/8] & im){
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if(cm[i/8] & im)
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gsi = i;
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}
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}
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if(gsi > 0 || getconf("*nopcirouting") != nil)
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return gsi;
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for(i=0; i<256; i++){
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gsi = lastirq++ & 0xFF; /* round robin */
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im = 1<<(gsi%8);
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if(pm[gsi/8] & im){
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if((c = setirq(r, gsi)) == nil)
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break;
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if(amleval(amlwalk(link, "_SRS"), "b", c, nil) < 0)
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break;
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return gsi;
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}
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}
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return -1;
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}
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static int
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enumprt(void *dot, void *)
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{
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void *p, **a, **b;
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int bno, dno, pin, gsi, flags;
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int n, i;
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bno = pcibusno(dot);
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if(bno < 0)
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return 1;
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/* evalulate _PRT method */
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p = nil;
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if(amleval(dot, "", &p) < 0)
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return 1;
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if(amltag(p) != 'p')
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return 1;
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amltake(p);
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n = amllen(p);
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a = amlval(p);
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for(i=0; i<n; i++){
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if(amltag(a[i]) != 'p')
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continue;
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if(amllen(a[i]) != 4)
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continue;
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flags = 0;
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b = amlval(a[i]);
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dno = amlint(b[0])>>16;
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pin = amlint(b[1]);
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gsi = amlint(b[3]);
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if(gsi==0){
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gsi = setuplink(b[2], &flags);
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if(gsi <= 0)
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continue;
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}
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addirq(gsi, BusPCI, bno, (dno<<2)|pin, flags);
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}
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amldrop(p);
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return 1;
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}
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static int
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enumec(void *dot, void *)
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{
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int cmdport, dataport;
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uchar *b;
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void *x;
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char *id;
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b = nil;
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id = eisaid(amlval(amlwalk(dot, "^_HID")));
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if(id == nil || strcmp(id, "PNP0C09") != 0)
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return 1;
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if((x = amlwalk(dot, "^_CRS")) == nil)
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return 1;
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if(amleval(x, "", &b) < 0 || amltag(b) != 'b' || amllen(b) < 16)
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return 1;
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if(b[0] != 0x47 || b[8] != 0x47) /* two i/o port descriptors */
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return 1;
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dataport = b[0+2] | b[0+3]<<8;
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cmdport = b[8+2] | b[8+3]<<8;
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ecinit(cmdport, dataport);
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return 1;
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}
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|
|
static long
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readmem(Chan*, void *v, long n, vlong o)
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|
{
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uvlong pa = (uvlong)o;
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void *t;
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if((n = memcheck(pa, n)) <= 0)
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return 0;
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if((t = vmap(pa, n)) == nil)
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error(Enovmem);
|
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if(waserror()){
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vunmap(t, n);
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nexterror();
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}
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memmove(v, t, n);
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vunmap(t, n);
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poperror();
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return n;
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}
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|
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static long
|
|
writemem(Chan*, void *v, long n, vlong o)
|
|
{
|
|
uvlong pa = (uvlong)o;
|
|
void *t;
|
|
|
|
if(memcheck(pa, n) != n)
|
|
error(Eio);
|
|
if((t = vmap(pa, n)) == nil)
|
|
error(Enovmem);
|
|
if(waserror()){
|
|
vunmap(t, n);
|
|
nexterror();
|
|
}
|
|
memmove(t, v, n);
|
|
vunmap(t, n);
|
|
poperror();
|
|
return n;
|
|
}
|
|
|
|
static void
|
|
acpiinit(void)
|
|
{
|
|
Tbl *t;
|
|
Apic *a;
|
|
void *va;
|
|
uchar *s, *p, *e;
|
|
ulong lapicbase;
|
|
int machno, i, c;
|
|
|
|
amlinit();
|
|
|
|
/* load DSDT */
|
|
for(i=0; i<ntblmap; i++){
|
|
t = tblmap[i];
|
|
if(memcmp(t->sig, "DSDT", 4) == 0){
|
|
amlintmask = (~0ULL) >> (t->rev <= 1)*32;
|
|
amlload(t->data, tbldlen(t));
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* load SSDT, there can be multiple tables */
|
|
for(i=0; i<ntblmap; i++){
|
|
t = tblmap[i];
|
|
if(memcmp(t->sig, "SSDT", 4) == 0)
|
|
amlload(t->data, tbldlen(t));
|
|
}
|
|
|
|
/* set APIC mode */
|
|
amleval(amlwalk(amlroot, "_PIC"), "i", 1, nil);
|
|
|
|
for(i=0; i<ntblmap; i++){
|
|
t = tblmap[i];
|
|
if(memcmp(t->sig, "APIC", 4) == 0)
|
|
goto Foundapic;
|
|
}
|
|
panic("acpiinit: no MADT (APIC) table");
|
|
return;
|
|
|
|
Foundapic:
|
|
s = t->data;
|
|
e = s + tbldlen(t);
|
|
lapicbase = get32(s); s += 8;
|
|
va = vmap(lapicbase, 1024);
|
|
print("LAPIC: %.8lux %#p\n", lapicbase, va);
|
|
if(va == nil)
|
|
panic("acpiinit: cannot map lapic %.8lux", lapicbase);
|
|
|
|
machno = 0;
|
|
for(p = s; p < e; p += c){
|
|
c = p[1];
|
|
if(c < 2 || (p+c) > e)
|
|
break;
|
|
switch(*p){
|
|
case 0x00: /* Processor Local APIC */
|
|
if(p[3] > MaxAPICNO)
|
|
break;
|
|
if((a = xalloc(sizeof(Apic))) == nil)
|
|
panic("acpiinit: no memory for Apic");
|
|
a->type = PcmpPROCESSOR;
|
|
a->apicno = p[3];
|
|
a->paddr = lapicbase;
|
|
a->addr = va;
|
|
a->lintr[0] = ApicIMASK;
|
|
a->lintr[1] = ApicIMASK;
|
|
a->flags = p[4] & PcmpEN;
|
|
|
|
/* skip disabled processors */
|
|
if((a->flags & PcmpEN) == 0 || mpapic[a->apicno] != nil){
|
|
xfree(a);
|
|
break;
|
|
}
|
|
a->machno = machno++;
|
|
|
|
/*
|
|
* platform firmware should list the boot processor
|
|
* as the first processor entry in the MADT
|
|
*/
|
|
if(a->machno == 0)
|
|
a->flags |= PcmpBP;
|
|
|
|
mpapic[a->apicno] = a;
|
|
break;
|
|
case 0x01: /* I/O APIC */
|
|
if(p[2] > MaxAPICNO)
|
|
break;
|
|
if((a = xalloc(sizeof(Apic))) == nil)
|
|
panic("acpiinit: no memory for io Apic");
|
|
a->type = PcmpIOAPIC;
|
|
a->apicno = p[2];
|
|
a->paddr = get32(p+4);
|
|
if((a->addr = vmap(a->paddr, 1024)) == nil)
|
|
panic("acpiinit: cannot map ioapic %.8lux", a->paddr);
|
|
a->gsibase = get32(p+8);
|
|
a->flags = PcmpEN;
|
|
mpioapic[a->apicno] = a;
|
|
ioapicinit(a, a->apicno);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* need 2nd pass as vbox puts interrupt overrides
|
|
* *before* the ioapic entries (!)
|
|
*/
|
|
for(p = s; p < e; p += c){
|
|
c = p[1];
|
|
if(c < 2 || (p+c) > e)
|
|
break;
|
|
switch(*p){
|
|
case 0x02: /* Interrupt Source Override */
|
|
addirq(get32(p+4), BusISA, 0, p[3], get16(p+8));
|
|
break;
|
|
case 0x03: /* NMI Source */
|
|
case 0x04: /* Local APIC NMI */
|
|
case 0x05: /* Local APIC Address Override */
|
|
case 0x06: /* I/O SAPIC */
|
|
case 0x07: /* Local SAPIC */
|
|
case 0x08: /* Platform Interrupt Sources */
|
|
case 0x09: /* Processor Local x2APIC */
|
|
case 0x0A: /* x2APIC NMI */
|
|
case 0x0B: /* GIC */
|
|
case 0x0C: /* GICD */
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* find embedded controller */
|
|
amlenum(amlroot, "_HID", enumec, nil);
|
|
|
|
/* look for PCI interrupt mappings */
|
|
amlenum(amlroot, "_PRT", enumprt, nil);
|
|
|
|
/* add identity mapped legacy isa interrupts */
|
|
for(i=0; i<16; i++)
|
|
addirq(i, BusISA, 0, i, 0);
|
|
|
|
/* free the AML interpreter */
|
|
amlexit();
|
|
|
|
/*
|
|
* Ininitalize local APIC and start application processors.
|
|
*/
|
|
mpinit();
|
|
}
|
|
|
|
static void
|
|
acpireset(void)
|
|
{
|
|
uchar *p;
|
|
Tbl *t;
|
|
int i;
|
|
|
|
/* stop application processors */
|
|
mpshutdown();
|
|
|
|
/* locate and write platform reset register */
|
|
for(i=0; i < ntblmap; i++){
|
|
t = tblmap[i];
|
|
if(memcmp(t->sig, "FACP", 4) != 0)
|
|
continue;
|
|
if(get32(t->len) <= 128)
|
|
break;
|
|
p = (uchar*)t;
|
|
if((get32(p + 112) & (1<<10)) == 0)
|
|
break;
|
|
if(p[116+0] != IoSpace)
|
|
break;
|
|
outb(get32(p+116+4), p[128]);
|
|
break;
|
|
}
|
|
|
|
/* acpi shutdown failed, try generic reset */
|
|
archreset();
|
|
}
|
|
|
|
static int identify(void);
|
|
|
|
PCArch archacpi = {
|
|
.id= "ACPI",
|
|
.ident= identify,
|
|
.reset= acpireset,
|
|
.intrinit= acpiinit,
|
|
.intrenable= mpintrenable,
|
|
.intron= lapicintron,
|
|
.introff= lapicintroff,
|
|
.fastclock= i8253read,
|
|
.timerset= lapictimerset,
|
|
};
|
|
|
|
static long
|
|
readtbls(Chan*, void *v, long n, vlong o)
|
|
{
|
|
int i, l, m;
|
|
uchar *p;
|
|
Tbl *t;
|
|
|
|
maptables();
|
|
|
|
p = v;
|
|
for(i=0; n > 0 && i < ntblmap; i++){
|
|
t = tblmap[i];
|
|
l = get32(t->len);
|
|
if(o >= l){
|
|
o -= l;
|
|
continue;
|
|
}
|
|
m = l - o;
|
|
if(m > n)
|
|
m = n;
|
|
memmove(p, (uchar*)t + o, m);
|
|
p += m;
|
|
n -= m;
|
|
o = 0;
|
|
}
|
|
return p - (uchar*)v;
|
|
}
|
|
|
|
static int
|
|
identify(void)
|
|
{
|
|
uvlong pa;
|
|
char *cp;
|
|
|
|
if((cp = getconf("*acpi")) == nil)
|
|
return 1;
|
|
pa = (uintptr)strtoull(cp, nil, 16);
|
|
if(pa <= 1)
|
|
rsd = rsdsearch();
|
|
else {
|
|
memreserve(pa, sizeof(Rsd));
|
|
rsd = vmap(pa, sizeof(Rsd));
|
|
}
|
|
if(rsd == nil)
|
|
return 1;
|
|
if(checksum(rsd, 20) && checksum(rsd, 36))
|
|
return 1;
|
|
maptables();
|
|
addarchfile("acpitbls", 0444, readtbls, nil);
|
|
addarchfile("acpimem", 0600, readmem, writemem);
|
|
if(strcmp(cp, "0") == 0)
|
|
return 1;
|
|
if((cp = getconf("*nomp")) != nil && strcmp(cp, "0") != 0)
|
|
return 1;
|
|
if(m->havetsc && getconf("*notsc") == nil)
|
|
archacpi.fastclock = tscticks;
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
readpcicfg(Amlio *io, void *data, int n, int offset)
|
|
{
|
|
ulong r, x;
|
|
Pcidev *p;
|
|
uchar *a;
|
|
int i;
|
|
|
|
a = data;
|
|
p = io->aux;
|
|
if(p == nil)
|
|
return -1;
|
|
offset += io->off;
|
|
if(offset > 256)
|
|
return 0;
|
|
if(n+offset > 256)
|
|
n = 256-offset;
|
|
r = offset;
|
|
if(!(r & 3) && n == 4){
|
|
x = pcicfgr32(p, r);
|
|
PBIT32(a, x);
|
|
return 4;
|
|
}
|
|
if(!(r & 1) && n == 2){
|
|
x = pcicfgr16(p, r);
|
|
PBIT16(a, x);
|
|
return 2;
|
|
}
|
|
for(i = 0; i < n; i++){
|
|
x = pcicfgr8(p, r);
|
|
PBIT8(a, x);
|
|
a++;
|
|
r++;
|
|
}
|
|
return i;
|
|
}
|
|
|
|
static int
|
|
readec(Amlio *io, void *data, int n, int off)
|
|
{
|
|
int port, v;
|
|
uchar *p;
|
|
|
|
USED(io);
|
|
if(off < 0 || off >= 256)
|
|
return 0;
|
|
if(off+n > 256)
|
|
n = 256 - off;
|
|
p = data;
|
|
for(port = off; port < off+n; port++){
|
|
if((v = ecread(port)) < 0)
|
|
break;
|
|
*p++ = v;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
static int
|
|
writeec(Amlio *io, void *data, int n, int off)
|
|
{
|
|
int port;
|
|
uchar *p;
|
|
|
|
USED(io);
|
|
if(off < 0 || off+n > 256)
|
|
return -1;
|
|
p = data;
|
|
for(port = off; port < off+n; port++)
|
|
if(ecwrite(port, *p++) < 0)
|
|
break;
|
|
return n;
|
|
}
|
|
|
|
static int
|
|
writepcicfg(Amlio *io, void *data, int n, int offset)
|
|
{
|
|
ulong r, x;
|
|
Pcidev *p;
|
|
uchar *a;
|
|
int i;
|
|
|
|
a = data;
|
|
p = io->aux;
|
|
if(p == nil)
|
|
return -1;
|
|
offset += io->off;
|
|
if(offset > 256)
|
|
return 0;
|
|
if(n+offset > 256)
|
|
n = 256-offset;
|
|
r = offset;
|
|
if(!(r & 3) && n == 4){
|
|
x = GBIT32(a);
|
|
pcicfgw32(p, r, x);
|
|
return 4;
|
|
}
|
|
if(!(r & 1) && n == 2){
|
|
x = GBIT16(a);
|
|
pcicfgw16(p, r, x);
|
|
return 2;
|
|
}
|
|
for(i = 0; i < n; i++){
|
|
x = GBIT8(a);
|
|
pcicfgw8(p, r, x);
|
|
a++;
|
|
r++;
|
|
}
|
|
return i;
|
|
}
|
|
|
|
static int
|
|
readioport(Amlio *io, void *data, int len, int port)
|
|
{
|
|
uchar *a;
|
|
|
|
a = data;
|
|
port += io->off;
|
|
switch(len){
|
|
case 4:
|
|
PBIT32(a, inl(port));
|
|
return 4;
|
|
case 2:
|
|
PBIT16(a, ins(port));
|
|
return 2;
|
|
case 1:
|
|
PBIT8(a, inb(port));
|
|
return 1;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
writeioport(Amlio *io, void *data, int len, int port)
|
|
{
|
|
uchar *a;
|
|
|
|
a = data;
|
|
port += io->off;
|
|
switch(len){
|
|
case 4:
|
|
outl(port, GBIT32(a));
|
|
return 4;
|
|
case 2:
|
|
outs(port, GBIT16(a));
|
|
return 2;
|
|
case 1:
|
|
outb(port, GBIT8(a));
|
|
return 1;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
int
|
|
amlmapio(Amlio *io)
|
|
{
|
|
int tbdf;
|
|
Pcidev *pdev;
|
|
char buf[64];
|
|
|
|
switch(io->space){
|
|
default:
|
|
print("amlmapio: address space %x not implemented\n", io->space);
|
|
break;
|
|
case MemSpace:
|
|
if(memcheck(io->off, io->len) != io->len){
|
|
print("amlmapio: [%#p-%#p) overlaps usable memory\n",
|
|
(uintptr)io->off, (uintptr)(io->off+io->len));
|
|
break;
|
|
}
|
|
if((io->va = vmap(io->off, io->len)) == nil){
|
|
print("amlmapio: vmap failed\n");
|
|
break;
|
|
}
|
|
return 0;
|
|
case IoSpace:
|
|
snprint(buf, sizeof(buf), "%N", io->name);
|
|
if(ioalloc(io->off, io->len, 0, buf) < 0){
|
|
print("amlmapio: ioalloc failed\n");
|
|
break;
|
|
}
|
|
io->read = readioport;
|
|
io->write = writeioport;
|
|
return 0;
|
|
case PcicfgSpace:
|
|
if((tbdf = pciaddr(io->name)) < 0){
|
|
print("amlmapio: no address\n");
|
|
break;
|
|
}
|
|
if((pdev = pcimatchtbdf(tbdf)) == nil){
|
|
print("amlmapio: no device %T\n", tbdf);
|
|
break;
|
|
}
|
|
io->aux = pdev;
|
|
io->read = readpcicfg;
|
|
io->write = writepcicfg;
|
|
return 0;
|
|
case EbctlSpace:
|
|
io->read = readec;
|
|
io->write = writeec;
|
|
return 0;
|
|
}
|
|
print("amlmapio: mapping %N failed\n", io->name);
|
|
return -1;
|
|
}
|
|
|
|
void
|
|
amlunmapio(Amlio *io)
|
|
{
|
|
switch(io->space){
|
|
case MemSpace:
|
|
vunmap(io->va, io->len);
|
|
break;
|
|
case IoSpace:
|
|
iofree(io->off);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void*
|
|
amlalloc(int n){
|
|
void *p;
|
|
|
|
if((p = malloc(n)) == nil)
|
|
panic("amlalloc: no memory");
|
|
memset(p, 0, n);
|
|
return p;
|
|
}
|
|
|
|
void
|
|
amlfree(void *p){
|
|
free(p);
|
|
}
|
|
|
|
void
|
|
amldelay(int us)
|
|
{
|
|
microdelay(us);
|
|
}
|