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No commits in common. "4223c2a3266f64c34bd9538ab5d8265a3d0e6fe2" and "5506860da55f9cb5328a0f511c32ab023bf9c635" have entirely different histories.
4223c2a326 ... 5506860da5

14 changed files with 20 additions and 744 deletions
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9
sys/man/1/git
View file

@ -96,10 +96,6 @@ git/pull, git/rm, git/serve
.I expr .I expr
] ]
[ [
.B -n
.I count
]
[
.B -s .B -s
] ]
[ [
@ -388,11 +384,6 @@ The
.I -s .I -s
option shows a summary of the commit, instead of the full message. option shows a summary of the commit, instead of the full message.
The The
.I -n count
option stops printing messages after
.I count
messages.
The
.I -e expr .I -e expr
option shows commits matching the query expression provided. option shows commits matching the query expression provided.
The expression is in the syntax of The expression is in the syntax of

92
sys/src/9/imx8/ccm.c
View file

@ -1075,90 +1075,6 @@ enablepll(int input)
} }
} }
enum {
CCM_ANALOG_PLLOUT_MONITOR_CFG = 0x74/4,
PLLOUT_MONITOR_CLK_CKE = 1<<4,
CCM_ANALOG_FRAC_PLLOUT_DIV_CFG = 0x78/4,
CCM_ANALOG_SCCG_PLLOUT_DIV_CFG = 0x7C/4,
};
static struct {
uchar input;
uchar reg; /* divider register */
uchar shift; /* divider shift */
} anapllout_input[16] = {
[0] OSC_25M_REF_CLK,
[1] OSC_27M_REF_CLK,
/* [2] HDMI_PHY_27M_CLK */
/* [3] CLK1_P_N */
[4] OSC_32K_REF_CLK,
[5] AUDIO_PLL1_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 0,
[6] AUDIO_PLL2_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 4,
[7] GPU_PLL_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 12,
[8] VPU_PLL_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 16,
[9] VIDEO_PLL1_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 8,
[10] ARM_PLL_CLK, CCM_ANALOG_FRAC_PLLOUT_DIV_CFG, 20,
[11] SYSTEM_PLL1_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 0,
[12] SYSTEM_PLL2_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 4,
[13] SYSTEM_PLL3_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 8,
[14] VIDEO_PLL2_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 16,
[15] DRAM_PLL1_CLK, CCM_ANALOG_SCCG_PLLOUT_DIV_CFG, 12,
};
static void
setanapllout(int input, int freq)
{
int mux, div, reg;
for(mux = 0; mux < nelem(anapllout_input); mux++)
if(anapllout_input[mux].input == input)
goto Muxok;
panic("setanapllout: bad input clock\n");
return;
Muxok:
anatop[CCM_ANALOG_PLLOUT_MONITOR_CFG] = mux;
if(freq <= 0)
return;
div = input_clk_freq[input] / freq;
if(div < 1 || div > 8){
panic("setanapllout: divider out of range\n");
return;
}
enablepll(input);
reg = anapllout_input[mux].reg;
if(reg){
int shift = anapllout_input[mux].shift;
anatop[reg] = (anatop[reg] & ~(7<<shift)) | ((div-1)<<shift);
} else if(div != 1){
panic("setanapllout: bad frequency\n");
return;
}
anatop[CCM_ANALOG_PLLOUT_MONITOR_CFG] |= PLLOUT_MONITOR_CLK_CKE;
}
static int
getanapllout(void)
{
int mux, input, freq, reg, div;
u32int cfg = anatop[CCM_ANALOG_PLLOUT_MONITOR_CFG];
mux = cfg & 0xF;
input = anapllout_input[mux].input;
if(input == 0)
return 0;
freq = input_clk_freq[input];
if((cfg & PLLOUT_MONITOR_CLK_CKE) == 0)
freq = -freq;
reg = anapllout_input[mux].reg;
if(reg){
int shift = anapllout_input[mux].shift;
div = ((anatop[reg] >> shift) & 7)+1;
} else {
div = 1;
}
return freq / div;
}
static u32int static u32int
clkgate(Clock *gate, u32int val) clkgate(Clock *gate, u32int val)
{ {
@ -1414,11 +1330,6 @@ setclkrate(char *name, char *source, int freq)
{ {
int root, input; int root, input;
if(cistrcmp(name, "ccm_analog_pllout") == 0){
setanapllout(lookinputclk(source), freq);
return;
}
if((root = lookrootclk(name)) < 0) if((root = lookrootclk(name)) < 0)
panic("setclkrate: clock %s not defined", name); panic("setclkrate: clock %s not defined", name);
if(source == nil) if(source == nil)
@ -1435,9 +1346,6 @@ getclkrate(char *name)
{ {
int root, input; int root, input;
if(cistrcmp(name, "ccm_analog_pllout") == 0)
return getanapllout();
if((root = lookrootclk(name)) >= 0) if((root = lookrootclk(name)) >= 0)
return rootclkgetcfg(root, &input); return rootclkgetcfg(root, &input);

7
sys/src/9/imx8/fns.h
View file

@ -159,10 +159,3 @@ extern uint iomuxgpr(int gpr, uint set, uint mask);
#define GPIO_PIN(n, m) ((n)<<5 | (m)) #define GPIO_PIN(n, m) ((n)<<5 | (m))
extern void gpioout(uint pin, int set); extern void gpioout(uint pin, int set);
extern int gpioin(uint pin); extern int gpioin(uint pin);
/* pciimx */
extern int pcicfgrw8(int tbdf, int rno, int data, int read);
extern int pcicfgrw16(int tbdf, int rno, int data, int read);
extern int pcicfgrw32(int tbdf, int rno, int data, int read);
extern void pciintrenable(int tbdf, void (*f)(Ureg*, void*), void *a);
extern void pciintrdisable(int tbdf, void (*f)(Ureg*, void*), void *a);

11
sys/src/9/imx8/gic.c
View file

@ -254,11 +254,6 @@ intrenable(int irq, void (*f)(Ureg*, void*), void *a, int tbdf, char *)
u32int intid; u32int intid;
int cpu, prio; int cpu, prio;
if(BUSTYPE(tbdf) == BusPCI){
pciintrenable(tbdf, f, a);
return;
}
if(tbdf != BUSUNKNOWN) if(tbdf != BUSUNKNOWN)
return; return;
@ -311,10 +306,6 @@ intrenable(int irq, void (*f)(Ureg*, void*), void *a, int tbdf, char *)
} }
void void
intrdisable(int tbdf, void (*f)(Ureg*, void*), void *a, int, char*) intrdisable(int, void (*)(Ureg*, void*), void *, int, char*)
{ {
if(BUSTYPE(tbdf) == BusPCI){
pciintrdisable(tbdf, f, a);
return;
}
} }

5
sys/src/9/imx8/io.h
View file

@ -28,12 +28,7 @@ enum {
IRQsctr0 = SPI+47, IRQsctr0 = SPI+47,
IRQsctr1 = SPI+48, IRQsctr1 = SPI+48,
IRQpci2 = SPI+74,
IRQenet1 = SPI+118, IRQenet1 = SPI+118,
IRQpci1 = SPI+122,
}; };
#define BUSUNKNOWN (-1) #define BUSUNKNOWN (-1)
#define PCIWADDR(x) PADDR(x)

497
sys/src/9/imx8/pciimx.c
View file

@ -1,497 +0,0 @@
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/pci.h"
typedef struct Intvec Intvec;
struct Intvec
{
Pcidev *p;
void (*f)(Ureg*, void*);
void *a;
};
typedef struct Ctlr Ctlr;
struct Ctlr
{
uvlong mem_base;
uvlong mem_size;
uvlong cfg_base;
uvlong cfg_size;
uvlong io_base;
uvlong io_size;
int bno, ubn;
int irq;
u32int *dbi;
u32int *cfg;
Pcidev *bridge;
Lock;
Intvec vec[32];
};
static Ctlr ctlrs[2] = {
{
0x18000000, 0x7f00000,
0x1ff00000, 0x80000,
0x1ff80000, 0x10000,
0, 127, IRQpci1,
(u32int*)(VIRTIO + 0x3800000),
},
{
0x20000000, 0x7f00000,
0x27f00000, 0x80000,
0x27f80000, 0x10000,
128, 255, IRQpci2,
(u32int*)(VIRTIO + 0x3c00000),
},
};
enum {
IATU_MAX = 8,
IATU_INBOUND = 1<<0,
IATU_INDEX_SHIFT = 1,
IATU_OFFSET = 0x300000/4,
IATU_STRIDE = 0x100/4,
IATU_REGION_CTRL_1 = 0x00/4,
CTRL_1_FUNC_NUM_SHIFT = 20,
CTRL_1_FUNC_NUM_MASK = 7<<CTRL_1_FUNC_NUM_SHIFT,
CTRL_1_INCREASE_REGION_SIZ = 1<<13,
CTRL_1_ATTR_SHIFT = 9,
CTRL_1_ATTR_MASK = 3<<CTRL_1_ATTR_SHIFT,
CTRL_1_TD = 1<<8,
CTRL_1_TC_SHIFT = 5,
CTRL_1_TC_MASK = 7<<CTRL_1_TC_SHIFT,
CTRL_1_TYPE_SHIFT = 0,
CTRL_1_TYPE_MASK = 0x1F<<CTRL_1_TYPE_SHIFT,
CTRL_1_TYPE_MEM = 0x0<<CTRL_1_TYPE_SHIFT,
CTRL_1_TYPE_IO = 0x2<<CTRL_1_TYPE_SHIFT,
CTRL_1_TYPE_CFG0 = 0x4<<CTRL_1_TYPE_SHIFT,
CTRL_1_TYPE_CFG1 = 0x5<<CTRL_1_TYPE_SHIFT,
IATU_REGION_CTRL_2 = 0x04/4,
CTRL_2_REGION_EN = 1<<31,
CTRL_2_INVERT_MODE = 1<<29,
CTRL_2_CFG_SHIFT_MODE = 1<<28,
CTRL_2_DMA_BYPASS = 1<<27,
CTRL_2_HEADER_SUBSITUTE_EN = 1<<23,
CTRL_2_INHIBIT_PAYLOAD = 1<<22,
CTRL_2_SNP = 1<<20,
CTRL_2_FUNC_BYPASS = 1<<19,
CTRL_2_TAG_SUBSTITUTE_EN = 1<<16,
IATU_LWR_BSAE_ADDR = 0x08/4,
IATU_UPPER_BASE_ADDR = 0x0C/4,
IATU_LWR_LIMIT_ADDR = 0x10/4,
IATU_LWR_TARGET_ADDR = 0x14/4,
IATU_UPPER_TARGET_ADDR = 0x18/4,
IATU_UPPER_LIMIT_ADDR = 0x20/4, /* undocumented */
};
/* disable all iATU's */
static void
iatuinit(Ctlr *ctlr)
{
u32int *reg;
int index;
for(index=0; index < IATU_MAX; index++){
reg = &ctlr->dbi[IATU_OFFSET + IATU_STRIDE*index];
reg[IATU_REGION_CTRL_2] &= ~CTRL_2_REGION_EN;
}
}
static void
iatucfg(Ctlr *ctlr, int index, u32int type, uvlong target, uvlong base, uvlong size)
{
uvlong limit = base + size - 1;
u32int *reg;
assert(size > 0);
assert(index < IATU_MAX);
assert((index & IATU_INBOUND) == 0);
reg = &ctlr->dbi[IATU_OFFSET + IATU_STRIDE*index];
reg[IATU_REGION_CTRL_2] &= ~CTRL_2_REGION_EN;
reg[IATU_LWR_BSAE_ADDR] = base;
reg[IATU_UPPER_BASE_ADDR] = base >> 32;
reg[IATU_LWR_LIMIT_ADDR] = limit;
reg[IATU_UPPER_LIMIT_ADDR] = limit >> 32;
reg[IATU_LWR_TARGET_ADDR] = target;
reg[IATU_UPPER_TARGET_ADDR] = target >> 32;
type &= CTRL_1_TYPE_MASK;
if(((size-1)>>32) != 0)
type |= CTRL_1_INCREASE_REGION_SIZ;
reg[IATU_REGION_CTRL_1] = type;
reg[IATU_REGION_CTRL_2] = CTRL_2_REGION_EN;
while((reg[IATU_REGION_CTRL_2] & CTRL_2_REGION_EN) == 0)
microdelay(10);
}
static Ctlr*
bus2ctlr(int bno)
{
Ctlr *ctlr;
for(ctlr = ctlrs; ctlr < &ctlrs[nelem(ctlrs)]; ctlr++)
if(bno >= ctlr->bno && bno <= ctlr->ubn)
return ctlr;
return nil;
}
static void*
cfgaddr(int tbdf, int rno)
{
Ctlr *ctlr;
ctlr = bus2ctlr(BUSBNO(tbdf));
if(ctlr == nil)
return nil;
if(pciparentdev == nil){
if(BUSDNO(tbdf) != 0 || BUSFNO(tbdf) != 0)
return nil;
return (uchar*)ctlr->dbi + rno;
}
iatucfg(ctlr, 0<<IATU_INDEX_SHIFT,
pciparentdev->parent==nil? CTRL_1_TYPE_CFG0: CTRL_1_TYPE_CFG1,
BUSBNO(tbdf)<<24 | BUSDNO(tbdf)<<19 | BUSFNO(tbdf)<<16,
ctlr->cfg_base, ctlr->cfg_size);
return (uchar*)ctlr->cfg + rno;
}
int
pcicfgrw32(int tbdf, int rno, int data, int read)
{
u32int *p;
if((p = cfgaddr(tbdf, rno & ~3)) != nil){
if(read)
data = *p;
else
*p = data;
} else {
data = -1;
}
return data;
}
int
pcicfgrw16(int tbdf, int rno, int data, int read)
{
u16int *p;
if((p = cfgaddr(tbdf, rno & ~1)) != nil){
if(read)
data = *p;
else
*p = data;
} else {
data = -1;
}
return data;
}
int
pcicfgrw8(int tbdf, int rno, int data, int read)
{
u8int *p;
if((p = cfgaddr(tbdf, rno)) != nil){
if(read)
data = *p;
else
*p = data;
} else {
data = -1;
}
return data;
}
static u16int msimsg;
#define MSI_TARGET_ADDR PADDR(&msimsg)
enum {
MSI_CAP_ID = 0x50/4,
PCI_MSI_ENABLE = 1<<16,
MSI_CTRL_ADDR = 0x820/4,
MSI_CTRL_UPPER_ADDR = 0x824/4,
MSI_CTRL_INT_0_EN = 0x828/4,
MSI_CTRL_INT_0_MASK = 0x82C/4,
MSI_CTRL_INT_0_STATUS = 0x830/4,
MISC_CONTROL_1 = 0x8BC/4,
DBI_RO_WR_EN = 1<<0,
};
static void
pciinterrupt(Ureg *ureg, void *arg)
{
Ctlr *ctlr = arg;
Intvec *vec;
u32int status;
status = ctlr->dbi[MSI_CTRL_INT_0_STATUS];
if(status == 0)
return;
ctlr->dbi[MSI_CTRL_INT_0_STATUS] = status;
ilock(ctlr);
for(vec = ctlr->vec; status != 0 && vec < &ctlr->vec[nelem(ctlr->vec)]; vec++, status >>= 1){
if((status & 1) != 0 && vec->f != nil)
(*vec->f)(ureg, vec->a);
}
iunlock(ctlr);
}
static void
pciintrinit(Ctlr *ctlr)
{
ctlr->dbi[MSI_CTRL_INT_0_EN] = 0;
ctlr->dbi[MSI_CTRL_INT_0_MASK] = 0;
ctlr->dbi[MSI_CTRL_INT_0_STATUS] = -1;
ctlr->dbi[MSI_CTRL_ADDR] = MSI_TARGET_ADDR;
ctlr->dbi[MSI_CTRL_UPPER_ADDR] = MSI_TARGET_ADDR >> 32;
intrenable(ctlr->irq+0, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
intrenable(ctlr->irq+1, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
intrenable(ctlr->irq+2, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
intrenable(ctlr->irq+3, pciinterrupt, ctlr, BUSUNKNOWN, "pci");
ctlr->dbi[MSI_CAP_ID] |= PCI_MSI_ENABLE;
}
void
pciintrenable(int tbdf, void (*f)(Ureg*, void*), void *a)
{
Ctlr *ctlr;
Intvec *vec;
Pcidev *p;
ctlr = bus2ctlr(BUSBNO(tbdf));
if(ctlr == nil){
print("pciintrenable: %T: unknown controller\n", tbdf);
return;
}
if((p = pcimatchtbdf(tbdf)) == nil){
print("pciintrenable: %T: unknown device\n", tbdf);
return;
}
if(pcimsidisable(p) < 0){
print("pciintrenable: %T: device doesnt support vec\n", tbdf);
return;
}
ilock(ctlr);
for(vec = ctlr->vec; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++){
if(vec->p == p){
ctlr->dbi[MSI_CTRL_INT_0_EN] &= ~(1 << (vec - ctlr->vec));
vec->p = nil;
break;
}
}
for(vec = ctlr->vec; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++){
if(vec->p == nil){
vec->p = p;
vec->a = a;
vec->f = f;
break;
}
}
iunlock(ctlr);
if(vec >= &ctlr->vec[nelem(ctlr->vec)]){
print("pciintrenable: %T: out of isr slots\n", tbdf);
return;
}
ctlr->dbi[MSI_CTRL_INT_0_EN] |= (1 << (vec - ctlr->vec));
pcimsienable(p, MSI_TARGET_ADDR, vec - ctlr->vec);
}
void
pciintrdisable(int tbdf, void (*f)(Ureg*, void*), void *a)
{
Ctlr *ctlr;
Intvec *vec;
ctlr = bus2ctlr(BUSBNO(tbdf));
if(ctlr == nil){
print("pciintrenable: %T: unknown controller\n", tbdf);
return;
}
ilock(ctlr);
for(vec = ctlr->vec; vec < &ctlr->vec[nelem(ctlr->vec)]; vec++){
if(vec->p == nil)
continue;
if(vec->p->tbdf == tbdf && vec->f == f && vec->a == a){
ctlr->dbi[MSI_CTRL_INT_0_EN] &= ~(1 << (vec - ctlr->vec));
vec->f = nil;
vec->a = nil;
vec->p = nil;
break;
}
}
iunlock(ctlr);
}
static void
rootinit(Ctlr *ctlr)
{
uvlong base;
ulong ioa;
iatuinit(ctlr);
ctlr->cfg = vmap(ctlr->cfg_base, ctlr->cfg_size);
if(ctlr->cfg == nil)
return;
ctlr->dbi[MISC_CONTROL_1] |= DBI_RO_WR_EN;
/* bus number */
ctlr->dbi[PciPBN/4] &= ~0xFFFFFF;
ctlr->dbi[PciPBN/4] |= ctlr->bno | (ctlr->bno+1)<<8 | ctlr->ubn<<16;
/* command */
ctlr->dbi[PciPCR/4] &= ~0xFFFF;
ctlr->dbi[PciPCR/4] |= IOen | MEMen | MASen | SErrEn;
/* device class/subclass */
ctlr->dbi[PciRID/4] &= ~0xFFFF0000;
ctlr->dbi[PciRID/4] |= 0x06040000;
ctlr->dbi[PciBAR0/4] = 0;
ctlr->dbi[PciBAR1/4] = 0;
ctlr->dbi[MISC_CONTROL_1] &= ~DBI_RO_WR_EN;
ctlr->ubn = pciscan(ctlr->bno, &ctlr->bridge, nil);
if(ctlr->bridge == nil || ctlr->bridge->bridge == nil)
return;
pciintrinit(ctlr);
iatucfg(ctlr, 1<<IATU_INDEX_SHIFT, CTRL_1_TYPE_IO, ctlr->io_base, ctlr->io_base, ctlr->io_size);
iatucfg(ctlr, 2<<IATU_INDEX_SHIFT, CTRL_1_TYPE_MEM, ctlr->mem_base, ctlr->mem_base, ctlr->mem_size);
ioa = ctlr->io_base;
base = ctlr->mem_base;
pcibusmap(ctlr->bridge, &base, &ioa, 1);
pcihinv(ctlr->bridge);
}
static void
pcicfginit(void)
{
fmtinstall('T', tbdffmt);
rootinit(&ctlrs[0]);
rootinit(&ctlrs[1]);
}
enum {
SRC_PCIEPHY_RCR = 0x2C/4,
SRC_PCIE2_RCR = 0x48/4,
PCIE_CTRL_APP_XFER_PENDING = 1<<16,
PCIE_CTRL_APP_UNLOCK_MSG = 1<<15,
PCIE_CTRL_SYS_INT = 1<<14,
PCIE_CTRL_CFG_L1_AUX = 1<<12,
PCIE_CTRL_APPS_TURNOFF = 1<<11,
PCIE_CTRL_APPS_PME = 1<<10,
PCIE_CTRL_APPS_EXIT = 1<<9,
PCIE_CTRL_APPS_ENTER = 1<<8,
PCIE_CTRL_APPS_READY = 1<<7,
PCIE_CTRL_APPS_EN = 1<<6,
PCIE_CTRL_APPS_RST = 1<<5,
PCIE_CTRL_APPS_CLK_REQ = 1<<4,
PCIE_PERST = 1<<3,
PCIE_BTN = 1<<2,
PCIE_G_RST = 1<<1,
PCIE_PHY_POWER_ON_RESET_N = 1<<0,
};
static u32int *resetc = (u32int*)(VIRTIO + 0x390000);
void
pciimxlink(void)
{
resetc[SRC_PCIEPHY_RCR] |= PCIE_BTN | PCIE_G_RST;
resetc[SRC_PCIE2_RCR] |= PCIE_BTN | PCIE_G_RST;
resetc[SRC_PCIEPHY_RCR] |= PCIE_CTRL_APPS_EN;
resetc[SRC_PCIE2_RCR] |= PCIE_CTRL_APPS_EN;
setclkgate("pcie_clk_rst.auxclk", 0);
setclkgate("pcie2_clk_rst.auxclk", 0);
iomuxpad("pad_ecspi1_mosi", "gpio5_io07", "~LVTTL ~HYS ~PUE ~ODE FAST 45_OHM");
iomuxpad("pad_sai5_rxd2", "gpio3_io23", "~LVTTL ~HYS ~PUE ~ODE FAST 45_OHM");
gpioout(GPIO_PIN(5, 7), 0);
gpioout(GPIO_PIN(3, 23), 0);
powerup("pcie");
powerup("pcie2");
/* configure monitor CLK2 output internal reference clock for PCIE1 */
setclkrate("ccm_analog_pllout", "system_pll1_clk", 100*Mhz);
delay(10);
/* PCIE1_REF_USE_PAD=0 */
iomuxgpr(14, 0<<9, 1<<9);
/* PCIE2_REF_USE_PAD=1 */
iomuxgpr(16, 1<<9, 1<<9);
/* PCIE1_CTRL_DEVICE_TYPE=ROOT, PCIE2_CTRL_DEVICE_TYPE=ROOT */
iomuxgpr(12, 4<<12 | 4<<8, 0xF<<12 | 0xF<<8);
setclkrate("ccm_pcie1_ctrl_clk_root", "system_pll2_div4", 250*Mhz);
setclkrate("ccm_pcie2_ctrl_clk_root", "system_pll2_div4", 250*Mhz);
setclkrate("pcie_clk_rst.auxclk", "system_pll2_div10", 100*Mhz);
setclkrate("pcie2_clk_rst.auxclk", "system_pll2_div10", 100*Mhz);
setclkrate("pcie_phy.ref_alt_clk_p", "system_pll2_div10", 100*Mhz);
setclkrate("pcie2_phy.ref_alt_clk_p", "system_pll2_div10", 100*Mhz);
setclkgate("pcie_clk_rst.auxclk", 1);
setclkgate("pcie2_clk_rst.auxclk", 1);
/* PCIE1_CLKREQ_B_OVERRIDE=0 PCIE1_CLKREQ_B_OVERRIDE_EN=1 */
iomuxgpr(14, 1<<10, 3<<10);
/* PCIE2_CLKREQ_B_OVERRIDE=0 PCIE2_CLKREQ_B_OVERRIDE_EN=1 */
iomuxgpr(16, 1<<10, 3<<10);
delay(100);
gpioout(GPIO_PIN(5, 7), 1);
gpioout(GPIO_PIN(3, 23), 1);
delay(1);
resetc[SRC_PCIEPHY_RCR] &= ~(PCIE_BTN | PCIE_G_RST);
resetc[SRC_PCIE2_RCR] &= ~(PCIE_BTN | PCIE_G_RST);
pcicfginit();
}

2
sys/src/9/imx8/reform
View file

@ -27,7 +27,6 @@ link
ethermedium ethermedium
loopbackmedium loopbackmedium
i2cimx devi2c i2cimx devi2c
pciimx pci
ip ip
tcp tcp
udp udp
@ -45,7 +44,6 @@ misc
uartimx uartimx
iomux iomux
sdmmc usdhc sdmmc usdhc
sdnvme pci
port port
int cpuserver = 0; int cpuserver = 0;
bootdir bootdir

25
sys/src/9/port/sdnvme.c → sys/src/9/pc/sdnvme.c
View file

@ -135,7 +135,6 @@ qcmd(WS *ws, Ctlr *ctlr, int adm, u32int opc, u32int nsid, void *mptr, void *dat
e[5] = 0; e[5] = 0;
} }
if(len > 0){ if(len > 0){
dmaflush(1, data, len);
pa = PCIWADDR(data); pa = PCIWADDR(data);
e[6] = pa; e[6] = pa;
e[7] = pa>>32; e[7] = pa>>32;
@ -174,7 +173,6 @@ nvmeintr(Ureg *, void *arg)
phaseshift = 16 - cq->shift; phaseshift = 16 - cq->shift;
for(;;){ for(;;){
e = &cq->base[(cq->head & cq->mask)<<2]; e = &cq->base[(cq->head & cq->mask)<<2];
dmaflush(0, e, 32);
if(((e[3] ^ (cq->head << phaseshift)) & 0x10000) == 0) if(((e[3] ^ (cq->head << phaseshift)) & 0x10000) == 0)
break; break;
@ -206,12 +204,11 @@ wdone(void *arg)
} }
static u32int static u32int
wcmd(WS *ws, u32int *e) wcmd(WS *ws)
{ {
SQ *sq = ws->queue; SQ *sq = ws->queue;
Ctlr *ctlr = sq->ctlr; Ctlr *ctlr = sq->ctlr;
if(e != nil) dmaflush(1, e, 64);
coherence(); coherence();
ctlr->reg[DBell + ((sq-ctlr->sq)*2+0 << ctlr->dstrd)] = sq->tail & sq->mask; ctlr->reg[DBell + ((sq-ctlr->sq)*2+0 << ctlr->dstrd)] = sq->tail & sq->mask;
if(sq > ctlr->sq) { if(sq > ctlr->sq) {
@ -266,12 +263,11 @@ nvmebio(SDunit *u, int lun, int write, void *a, long count, uvlong lba)
e[13] = (count>n)<<6; /* sequential request */ e[13] = (count>n)<<6; /* sequential request */
e[14] = 0; e[14] = 0;
e[15] = 0; e[15] = 0;
checkstatus(wcmd(&ws, e), write ? "write" : "read"); checkstatus(wcmd(&ws), write ? "write" : "read");
p += n*s; p += n*s;
count -= n; count -= n;
lba += n; lba += n;
} }
if(!write) dmaflush(0, a, p - (uchar*)a);
return p - (uchar*)a; return p - (uchar*)a;
} }
@ -317,11 +313,10 @@ nvmeonline(SDunit *u)
e = qcmd(&ws, ctlr, 1, 0x06, ctlr->nsid[u->subno], nil, info, 0x1000); e = qcmd(&ws, ctlr, 1, 0x06, ctlr->nsid[u->subno], nil, info, 0x1000);
e[10] = 0; // identify namespace e[10] = 0; // identify namespace
if(wcmd(&ws, e) != 0){ if(wcmd(&ws) != 0){
free(info); free(info);
return 0; return 0;
} }
dmaflush(0, info, 0x1000);
p = info; p = info;
u->sectors = p[0] | p[1]<<8 | p[2]<<16 | p[3]<<24 u->sectors = p[0] | p[1]<<8 | p[2]<<16 | p[3]<<24
| (u64int)p[4]<<32 | (u64int)p[4]<<32
@ -410,7 +405,7 @@ setupqueues(Ctlr *ctlr)
e = qcmd(&ws, ctlr, 1, 0x05, 0, nil, cq->base, 1<<lgsize); e = qcmd(&ws, ctlr, 1, 0x05, 0, nil, cq->base, 1<<lgsize);
e[10] = (cq - ctlr->cq) | cq->mask<<16; e[10] = (cq - ctlr->cq) | cq->mask<<16;
e[11] = 3; /* IEN | PC */ e[11] = 3; /* IEN | PC */
checkstatus(wcmd(&ws, e), "create completion queue"); checkstatus(wcmd(&ws), "create completion queue");
st = 0; st = 0;
@ -421,7 +416,8 @@ setupqueues(Ctlr *ctlr)
e = qcmd(&ws, ctlr, 1, 0x01, 0, nil, sq->base, 0x1000); e = qcmd(&ws, ctlr, 1, 0x01, 0, nil, sq->base, 0x1000);
e[10] = i | sq->mask<<16; e[10] = i | sq->mask<<16;
e[11] = (cq - ctlr->cq)<<16 | 1; /* CQID<<16 | PC */ e[11] = (cq - ctlr->cq)<<16 | 1; /* CQID<<16 | PC */
st = wcmd(&ws, e);
st = wcmd(&ws);
if(st != 0){ if(st != 0){
free(sq->base); free(sq->base);
free(sq->wait); free(sq->wait);
@ -455,14 +451,11 @@ identify(Ctlr *ctlr)
e = qcmd(&ws, ctlr, 1, 0x06, 0, nil, ctlr->ident, 0x1000); e = qcmd(&ws, ctlr, 1, 0x06, 0, nil, ctlr->ident, 0x1000);
e[10] = 1; // identify controller e[10] = 1; // identify controller
checkstatus(wcmd(&ws, e), "identify controller"); checkstatus(wcmd(&ws), "identify controller");
dmaflush(0, ctlr->ident, 0x1000);
e = qcmd(&ws, ctlr, 1, 0x06, 0, nil, ctlr->nsid, 0x1000); e = qcmd(&ws, ctlr, 1, 0x06, 0, nil, ctlr->nsid, 0x1000);
e[10] = 2; // namespace list e[10] = 2; // namespace list
if(wcmd(&ws, e) == 0) if(wcmd(&ws) != 0)
dmaflush(0, ctlr->nsid, 0x1000);
else
ctlr->nsid[0] = 1; /* assume namespace #1 */ ctlr->nsid[0] = 1; /* assume namespace #1 */
ctlr->nnsid = 0; ctlr->nnsid = 0;
@ -539,12 +532,10 @@ nvmeenable(SDev *sd)
} }
pa = PCIWADDR(cqalloc(ctlr, &ctlr->cq[0], ctlr->mpsshift)); pa = PCIWADDR(cqalloc(ctlr, &ctlr->cq[0], ctlr->mpsshift));
dmaflush(1, ctlr->cq[0].base, 1<<ctlr->mpsshift);
ctlr->reg[ACQBase0] = pa; ctlr->reg[ACQBase0] = pa;
ctlr->reg[ACQBase1] = pa>>32; ctlr->reg[ACQBase1] = pa>>32;
pa = PCIWADDR(sqalloc(ctlr, &ctlr->sq[0], ctlr->mpsshift)); pa = PCIWADDR(sqalloc(ctlr, &ctlr->sq[0], ctlr->mpsshift));
dmaflush(1, ctlr->sq[0].base, 1<<ctlr->mpsshift);
ctlr->reg[ASQBase0] = pa; ctlr->reg[ASQBase0] = pa;
ctlr->reg[ASQBase1] = pa>>32; ctlr->reg[ASQBase1] = pa>>32;

22
sys/src/9/port/pci.c
View file

@ -16,7 +16,6 @@ struct Pcisiz
}; };
int pcimaxdno; int pcimaxdno;
Pcidev *pciparentdev;
static Lock pcicfglock; static Lock pcicfglock;
static Pcidev *pcilist, **pcitail; static Pcidev *pcilist, **pcitail;
@ -114,8 +113,6 @@ pcicfgr8(Pcidev* p, int rno)
int data; int data;
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
data = pcicfgrw8(p->tbdf, rno, 0, 1); data = pcicfgrw8(p->tbdf, rno, 0, 1);
iunlock(&pcicfglock); iunlock(&pcicfglock);
@ -125,8 +122,6 @@ void
pcicfgw8(Pcidev* p, int rno, int data) pcicfgw8(Pcidev* p, int rno, int data)
{ {
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
pcicfgrw8(p->tbdf, rno, data, 0); pcicfgrw8(p->tbdf, rno, data, 0);
iunlock(&pcicfglock); iunlock(&pcicfglock);
} }
@ -136,8 +131,6 @@ pcicfgr16(Pcidev* p, int rno)
int data; int data;
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
data = pcicfgrw16(p->tbdf, rno, 0, 1); data = pcicfgrw16(p->tbdf, rno, 0, 1);
iunlock(&pcicfglock); iunlock(&pcicfglock);
@ -147,8 +140,6 @@ void
pcicfgw16(Pcidev* p, int rno, int data) pcicfgw16(Pcidev* p, int rno, int data)
{ {
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
pcicfgrw16(p->tbdf, rno, data, 0); pcicfgrw16(p->tbdf, rno, data, 0);
iunlock(&pcicfglock); iunlock(&pcicfglock);
} }
@ -158,8 +149,6 @@ pcicfgr32(Pcidev* p, int rno)
int data; int data;
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
data = pcicfgrw32(p->tbdf, rno, 0, 1); data = pcicfgrw32(p->tbdf, rno, 0, 1);
iunlock(&pcicfglock); iunlock(&pcicfglock);
@ -169,8 +158,6 @@ void
pcicfgw32(Pcidev* p, int rno, int data) pcicfgw32(Pcidev* p, int rno, int data)
{ {
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
pcicfgrw32(p->tbdf, rno, data, 0); pcicfgrw32(p->tbdf, rno, data, 0);
iunlock(&pcicfglock); iunlock(&pcicfglock);
} }
@ -182,7 +169,6 @@ pcibarsize(Pcidev *p, int rno)
int v; int v;
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
v = pcicfgrw32(p->tbdf, rno, 0, 1); v = pcicfgrw32(p->tbdf, rno, 0, 1);
pcicfgrw32(p->tbdf, rno, -1, 0); pcicfgrw32(p->tbdf, rno, -1, 0);
@ -220,8 +206,6 @@ void
pcisetbar(Pcidev *p, int rno, uvlong bar) pcisetbar(Pcidev *p, int rno, uvlong bar)
{ {
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
pcicfgrw32(p->tbdf, rno, bar, 0); pcicfgrw32(p->tbdf, rno, bar, 0);
if((bar&7) == 4 && rno >= PciBAR0 && rno < PciBAR0+4*(nelem(p->mem)-1)) if((bar&7) == 4 && rno >= PciBAR0 && rno < PciBAR0+4*(nelem(p->mem)-1))
pcicfgrw32(p->tbdf, rno+4, bar>>32, 0); pcicfgrw32(p->tbdf, rno+4, bar>>32, 0);
@ -232,8 +216,6 @@ void
pcisetwin(Pcidev *p, uvlong base, uvlong limit) pcisetwin(Pcidev *p, uvlong base, uvlong limit)
{ {
ilock(&pcicfglock); ilock(&pcicfglock);
pciparentdev = p->parent;
if(base & 1){ if(base & 1){
pcicfgrw16(p->tbdf, PciIBR, (limit & 0xF000)|((base & 0xF000)>>8), 0); pcicfgrw16(p->tbdf, PciIBR, (limit & 0xF000)|((base & 0xF000)>>8), 0);
pcicfgrw32(p->tbdf, PciIUBR, (limit & 0xFFFF0000)|(base>>16), 0); pcicfgrw32(p->tbdf, PciIUBR, (limit & 0xFFFF0000)|(base>>16), 0);
@ -552,15 +534,12 @@ pciscan(int bno, Pcidev** list, Pcidev *parent)
tbdf = MKBUS(BusPCI, bno, dno, fno); tbdf = MKBUS(BusPCI, bno, dno, fno);
lock(&pcicfglock); lock(&pcicfglock);
pciparentdev = parent;
l = pcicfgrw32(tbdf, PciVID, 0, 1); l = pcicfgrw32(tbdf, PciVID, 0, 1);
unlock(&pcicfglock); unlock(&pcicfglock);
if(l == 0xFFFFFFFF || l == 0) if(l == 0xFFFFFFFF || l == 0)
continue; continue;
p = pcidevalloc(); p = pcidevalloc();
p->parent = parent;
p->tbdf = tbdf; p->tbdf = tbdf;
p->vid = l; p->vid = l;
p->did = l>>16; p->did = l>>16;
@ -643,6 +622,7 @@ pciscan(int bno, Pcidev** list, Pcidev *parent)
break; break;
} }
p->parent = parent;
if(head != nil) if(head != nil)
*tail = p; *tail = p;
else else

1
sys/src/9/port/pci.h
View file

@ -223,7 +223,6 @@ enum
}; };
extern int pcimaxdno; extern int pcimaxdno;
extern Pcidev *pciparentdev;
extern void pcidevfree(Pcidev* pcidev); extern void pcidevfree(Pcidev* pcidev);

65
sys/src/cmd/git/compat Normal file → Executable file
View file

@ -94,7 +94,7 @@ fn cmd_rev-parse{
echo `{dcmd git9/branch | sed s@^heads/@@g} echo `{dcmd git9/branch | sed s@^heads/@@g}
shift shift
case * case *
die unknown option $opt dprint option $opt
} }
shift shift
} }
@ -112,15 +112,6 @@ fn cmd_show-ref{
echo `{cat $gitroot/.git/refs/$b} refs/$b echo `{cat $gitroot/.git/refs/$b} refs/$b
} }
fn cmd_rev-parse{
switch($1){
case --git-dir
echo `{git/conf -r}^/.git
case *
die 'unknown rev-parse '$*
}
}
fn cmd_remote{ fn cmd_remote{
if({! ~ $#* 3 && ! ~ $#* 4} || ! ~ $1 add) if({! ~ $#* 3 && ! ~ $#* 4} || ! ~ $1 add)
die unimplemented remote cmd $* die unimplemented remote cmd $*
@ -134,44 +125,6 @@ fn cmd_remote{
} }
} }
fn cmd_log{
count=()
format=''
while(~ $1 -*){
switch($1){
case --format
format=$2
shift
case '--format='*
format=`{echo $1 | sed 's/--format=//g'}
case -n
count=-n$2
shift
case -n*
count=$1
case *
dprint option $opt
}
shift
}
@{cd $gitroot && git/fs}
switch($format){
case ''
git/log $count
case '%H:%ct'
for(c in `{git/log -s $count| awk '{print $1}'})
echo $c:`{mtime $gitroot/.git/fs/object/$c/msg}
case '%h %cd'
for(c in `{git/log -s $count| awk '{print $1}'})
echo $c `{date `{mtime $gitroot/.git/fs/object/$c/msg}}
}
}
fn cmd_show{
cmd_log -n1 $*
}
fn cmd_ls-remote{ fn cmd_ls-remote{
if(~ $1 -q) if(~ $1 -q)
shift shift
@ -185,9 +138,6 @@ fn cmd_version{
echo git version 2.2.0 echo git version 2.2.0
} }
fn cmd_status{
echo
}
fn usage{ fn usage{
echo 'git <command> <args>' >[1=2] echo 'git <command> <args>' >[1=2]
@ -208,20 +158,11 @@ if(~ $0 *compat){
exec rc exec rc
} }
if(~ $#gitcompatdebug 1)
echo running $* >>/tmp/gitlog
if(~ $1 -c)
shift 2
if(~ $1 -c*)
shift 1
if(! test -f '/env/fn#cmd_'$1) if(! test -f '/env/fn#cmd_'$1)
die git $1: commmand not implemented die git $1: commmand not implemented
if(! ~ $1 init && ! ~ $1 clone) if(! ~ $1 init && ! ~ $1 clone)
gitroot=`{git/conf -r} || die repo gitroot=`{git/conf -r} || die repo
if(~ $#gitcompatdebug 1) echo $* >/tmp/gitlog
cmd_$1 $*(2-) | tee >>/tmp/gitlog cmd_$1 $*(2-)
if not
cmd_$1 $*(2-)
exit '' exit ''

8
sys/src/cmd/git/log.c
View file

@ -14,7 +14,6 @@ Biobuf *out;
char *queryexpr; char *queryexpr;
char *commitid; char *commitid;
int shortlog; int shortlog;
int msgcount = -1;
Objset done; Objset done;
Objq objq; Objq objq;
@ -181,7 +180,7 @@ showquery(char *q)
if((n = resolverefs(&h, q)) == -1) if((n = resolverefs(&h, q)) == -1)
sysfatal("resolve: %r"); sysfatal("resolve: %r");
for(i = 0; i < n && (msgcount == -1 || msgcount-- > 0); i++){ for(i = 0; i < n; i++){
if((o = readobject(h[i])) == nil) if((o = readobject(h[i])) == nil)
sysfatal("read %H: %r", h[i]); sysfatal("read %H: %r", h[i]);
show(o); show(o);
@ -207,7 +206,7 @@ showcommits(char *c)
qinit(&objq); qinit(&objq);
osinit(&done); osinit(&done);
qput(&objq, o, 0); qput(&objq, o, 0);
while(qpop(&objq, &e) && (msgcount == -1 || msgcount-- > 0)){ while(qpop(&objq, &e)){
show(e.o); show(e.o);
for(i = 0; i < e.o->commit->nparent; i++){ for(i = 0; i < e.o->commit->nparent; i++){
if(oshas(&done, e.o->commit->parent[i])) if(oshas(&done, e.o->commit->parent[i]))
@ -244,9 +243,6 @@ main(int argc, char **argv)
case 's': case 's':
shortlog++; shortlog++;
break; break;
case 'n':
msgcount = atoi(EARGF(usage()));
break;
default: default:
usage(); usage();
break; break;

8
sys/src/cmd/gopher/gopher.c
View file

@ -129,7 +129,7 @@ rendermenu(Link *l, Biobuf *bp)
char *s, *f[5], *t; char *s, *f[5], *t;
Gmenu *m; Gmenu *m;
Link *n; Link *n;
int type, c; int type;
m = malloc(sizeof *m); m = malloc(sizeof *m);
if(m==nil) if(m==nil)
@ -143,7 +143,7 @@ rendermenu(Link *l, Biobuf *bp)
if(s==nil || s[0]=='.') if(s==nil || s[0]=='.')
break; break;
type = seltype(s[0]); type = seltype(s[0]);
c = getfields(s+1, f, 5, 0, "\t\r\n"); getfields(s+1, f, 5, 0, "\t\r\n");
switch(type){ switch(type){
case Tinfo: case Tinfo:
break; break;
@ -151,10 +151,6 @@ rendermenu(Link *l, Biobuf *bp)
n = mklink(strdup(f[1]+4), nil, Thtml); /* +4 skip URL: */ n = mklink(strdup(f[1]+4), nil, Thtml); /* +4 skip URL: */
break; break;
default: default:
if(type < 0 && c < 3){
fprint(2, "skipping invalid menu line '%s'\n", s);
continue;
}
n = mklink(netmkaddr(f[2], "tcp", f[3]), strdup(f[1]), type); n = mklink(netmkaddr(f[2], "tcp", f[3]), strdup(f[1]), type);
break; break;
} }

12
sys/src/cmd/patch.c
View file

@ -287,13 +287,13 @@ hunk:
while(1){ while(1){
if((ln = readline(f, &lnum)) == nil){ if((ln = readline(f, &lnum)) == nil){
if(oldcnt != h.oldcnt || newcnt != h.newcnt) if(oldcnt != h.oldcnt || newcnt != h.newcnt)
sysfatal("%s:%d: malformed hunk: mismatched counts", name, lnum); sysfatal("%s:%d: malformed hunk", name, lnum);
addhunk(p, &h); addhunk(p, &h);
break; break;
} }
switch(ln[0]){ switch(ln[0]){
default: default:
sysfatal("%s:%d: malformed hunk: leading junk", name, lnum); sysfatal("%s:%d: malformed hunk2", name, lnum);
goto out; goto out;
case '-': case '-':
addold(&h, ln); addold(&h, ln);
@ -303,12 +303,6 @@ hunk:
addnew(&h, ln); addnew(&h, ln);
newcnt++; newcnt++;
break; break;
case '\n':
addold(&h, " \n");
addnew(&h, " \n");
oldcnt++;
newcnt++;
break;
case ' ': case ' ':
addold(&h, ln); addold(&h, ln);
addnew(&h, ln); addnew(&h, ln);
@ -318,7 +312,7 @@ hunk:
} }
free(ln); free(ln);
if(oldcnt > h.oldcnt || newcnt > h.newcnt) if(oldcnt > h.oldcnt || newcnt > h.newcnt)
sysfatal("%s:%d: malformed hunk: oversized hunk", name, lnum); sysfatal("%s:%d: malformed hunk", name, lnum);
if(oldcnt < h.oldcnt || newcnt < h.newcnt) if(oldcnt < h.oldcnt || newcnt < h.newcnt)
continue; continue;